1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree file for Cortina systems Gemini 3 * Device Tree file for Cortina systems Gemini SoC
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/irq 6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clo 7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-res 8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 10
11 / { 11 / {
12 soc { 12 soc {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 ranges; 15 ranges;
16 compatible = "simple-bus"; 16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>; 17 interrupt-parent = <&intcon>;
18 18
19 flash: flash@30000000 { 19 flash: flash@30000000 {
20 compatible = "cortina, 20 compatible = "cortina,gemini-flash", "cfi-flash";
21 syscon = <&syscon>; 21 syscon = <&syscon>;
22 pinctrl-names = "defau 22 pinctrl-names = "default";
23 pinctrl-0 = <&pflash_d 23 pinctrl-0 = <&pflash_default_pins>;
24 bank-width = <2>; 24 bank-width = <2>;
25 status = "disabled"; 25 status = "disabled";
26 }; 26 };
27 27
28 syscon: syscon@40000000 { 28 syscon: syscon@40000000 {
29 compatible = "cortina, 29 compatible = "cortina,gemini-syscon",
30 "syscon", 30 "syscon", "simple-mfd";
31 reg = <0x40000000 0x10 31 reg = <0x40000000 0x1000>;
32 #clock-cells = <1>; 32 #clock-cells = <1>;
33 #reset-cells = <1>; 33 #reset-cells = <1>;
34 34
35 syscon-reboot { 35 syscon-reboot {
36 compatible = " 36 compatible = "syscon-reboot";
37 regmap = <&sys 37 regmap = <&syscon>;
38 /* GLOBAL_RESE 38 /* GLOBAL_RESET register */
39 offset = <0x0c 39 offset = <0x0c>;
40 /* RESET_GLOBA 40 /* RESET_GLOBAL | RESET_CPU1 */
41 mask = <0xC000 41 mask = <0xC0000000>;
42 }; 42 };
43 43
44 pinctrl { 44 pinctrl {
45 compatible = " 45 compatible = "cortina,gemini-pinctrl";
46 regmap = <&sys 46 regmap = <&syscon>;
47 /* Hog the DRA 47 /* Hog the DRAM pins */
48 pinctrl-names 48 pinctrl-names = "default";
49 pinctrl-0 = <& 49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
50 <& 50 <&vcontrol_default_pins>;
51 51
52 dram_default_p 52 dram_default_pins: pinctrl-dram {
53 mux { 53 mux {
54 54 function = "dram";
55 55 groups = "dramgrp";
56 }; 56 };
57 }; 57 };
58 rtc_default_pi 58 rtc_default_pins: pinctrl-rtc {
59 mux { 59 mux {
60 60 function = "rtc";
61 61 groups = "rtcgrp";
62 }; 62 };
63 }; 63 };
64 power_default_ 64 power_default_pins: pinctrl-power {
65 mux { 65 mux {
66 66 function = "power";
67 67 groups = "powergrp";
68 }; 68 };
69 }; 69 };
70 cir_default_pi 70 cir_default_pins: pinctrl-cir {
71 mux { 71 mux {
72 72 function = "cir";
73 73 groups = "cirgrp";
74 }; 74 };
75 }; 75 };
76 system_default 76 system_default_pins: pinctrl-system {
77 mux { 77 mux {
78 78 function = "system";
79 79 groups = "systemgrp";
80 }; 80 };
81 }; 81 };
82 vcontrol_defau 82 vcontrol_default_pins: pinctrl-vcontrol {
83 mux { 83 mux {
84 84 function = "vcontrol";
85 85 groups = "vcontrolgrp";
86 }; 86 };
87 }; 87 };
88 ice_default_pi 88 ice_default_pins: pinctrl-ice {
89 mux { 89 mux {
90 90 function = "ice";
91 91 groups = "icegrp";
92 }; 92 };
93 }; 93 };
94 uart_default_p 94 uart_default_pins: pinctrl-uart {
95 mux { 95 mux {
96 96 function = "uart";
97 97 groups = "uartrxtxgrp";
98 }; 98 };
99 }; 99 };
100 pflash_default 100 pflash_default_pins: pinctrl-pflash {
101 mux { 101 mux {
102 102 function = "pflash";
103 103 groups = "pflashgrp";
104 }; 104 };
105 }; 105 };
106 usb_default_pi 106 usb_default_pins: pinctrl-usb {
107 mux { 107 mux {
108 108 function = "usb";
109 109 groups = "usbgrp";
110 }; 110 };
111 }; 111 };
112 gmii_default_p 112 gmii_default_pins: pinctrl-gmii {
113 /* 113 /*
114 * Onl 114 * Only activate GMAC0 by default since
115 * GMA 115 * GMAC1 will overlap with 8 GPIO lines
116 * gpi 116 * gpio2a, gpio2b. Overlay groups with
117 * "gm 117 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
118 * bot 118 * both ethernet interfaces.
119 */ 119 */
120 mux { 120 mux {
121 121 function = "gmii";
122 122 groups = "gmii_gmac0_grp";
123 }; 123 };
124 }; 124 };
125 pci_default_pi 125 pci_default_pins: pinctrl-pci {
126 mux { 126 mux {
127 127 function = "pci";
128 128 groups = "pcigrp";
129 }; 129 };
130 }; 130 };
131 sata_default_p 131 sata_default_pins: pinctrl-sata {
132 mux { 132 mux {
133 133 function = "sata";
134 134 groups = "satagrp";
135 }; 135 };
136 }; 136 };
137 /* Activate bo 137 /* Activate both groups of pins for this state */
138 sata_and_ide_p 138 sata_and_ide_pins: pinctrl-sata-ide {
139 mux0 { 139 mux0 {
140 140 function = "sata";
141 141 groups = "satagrp";
142 }; 142 };
143 mux1 { 143 mux1 {
144 144 function = "ide";
145 145 groups = "idegrp";
146 }; 146 };
147 }; 147 };
148 tvc_default_pi 148 tvc_default_pins: pinctrl-tvc {
149 mux { 149 mux {
150 150 function = "tvc";
151 151 groups = "tvcgrp";
152 }; 152 };
153 }; 153 };
154 }; 154 };
155 }; 155 };
156 156
157 watchdog@41000000 { 157 watchdog@41000000 {
158 compatible = "cortina, 158 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
159 reg = <0x41000000 0x10 159 reg = <0x41000000 0x1000>;
160 interrupts = <3 IRQ_TY 160 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
161 resets = <&syscon GEMI 161 resets = <&syscon GEMINI_RESET_WDOG>;
162 clocks = <&syscon GEMI 162 clocks = <&syscon GEMINI_CLK_APB>;
163 clock-names = "PCLK"; 163 clock-names = "PCLK";
164 }; 164 };
165 165
166 uart0: serial@42000000 { 166 uart0: serial@42000000 {
167 compatible = "ns16550a 167 compatible = "ns16550a";
168 reg = <0x42000000 0x10 168 reg = <0x42000000 0x100>;
169 resets = <&syscon GEMI 169 resets = <&syscon GEMINI_RESET_UART>;
170 clocks = <&syscon GEMI 170 clocks = <&syscon GEMINI_CLK_UART>;
171 interrupts = <18 IRQ_T 171 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
172 pinctrl-names = "defau 172 pinctrl-names = "default";
173 pinctrl-0 = <&uart_def 173 pinctrl-0 = <&uart_default_pins>;
174 reg-shift = <2>; 174 reg-shift = <2>;
175 }; 175 };
176 176
177 timer@43000000 { 177 timer@43000000 {
178 compatible = "faraday, 178 compatible = "faraday,fttmr010";
179 reg = <0x43000000 0x10 179 reg = <0x43000000 0x1000>;
180 interrupt-parent = <&i 180 interrupt-parent = <&intcon>;
181 interrupts = <14 IRQ_T 181 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
182 <15 IRQ_T 182 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
183 <16 IRQ_T 183 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
184 resets = <&syscon GEMI 184 resets = <&syscon GEMINI_RESET_TIMER>;
185 /* APB clock or RTC cl 185 /* APB clock or RTC clock */
186 clocks = <&syscon GEMI 186 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
187 clock-names = "PCLK", 187 clock-names = "PCLK", "EXTCLK";
188 syscon = <&syscon>; 188 syscon = <&syscon>;
189 }; 189 };
190 190
191 rtc@45000000 { 191 rtc@45000000 {
192 compatible = "cortina, 192 compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
193 reg = <0x45000000 0x10 193 reg = <0x45000000 0x100>;
194 interrupts = <17 IRQ_T 194 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
195 resets = <&syscon GEMI 195 resets = <&syscon GEMINI_RESET_RTC>;
196 clocks = <&syscon GEMI 196 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
197 clock-names = "PCLK", 197 clock-names = "PCLK", "EXTCLK";
198 pinctrl-names = "defau 198 pinctrl-names = "default";
199 pinctrl-0 = <&rtc_defa 199 pinctrl-0 = <&rtc_default_pins>;
200 }; 200 };
201 201
202 sata: sata@46000000 { 202 sata: sata@46000000 {
203 compatible = "cortina, 203 compatible = "cortina,gemini-sata-bridge";
204 reg = <0x46000000 0x10 204 reg = <0x46000000 0x100>;
205 resets = <&syscon GEMI 205 resets = <&syscon GEMINI_RESET_SATA0>,
206 <&syscon GEMI 206 <&syscon GEMINI_RESET_SATA1>;
207 reset-names = "sata0", 207 reset-names = "sata0", "sata1";
208 clocks = <&syscon GEMI 208 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
209 <&syscon GEMI 209 <&syscon GEMINI_CLK_GATE_SATA1>;
210 clock-names = "SATA0_P 210 clock-names = "SATA0_PCLK", "SATA1_PCLK";
211 /* 211 /*
212 * This defines the sp 212 * This defines the special "ide" state that needs
213 * to be explicitly en 213 * to be explicitly enabled to enable the IDE pins,
214 * as these pins are n 214 * as these pins are normally used for other things.
215 */ 215 */
216 pinctrl-names = "defau 216 pinctrl-names = "default", "ide";
217 pinctrl-0 = <&sata_def 217 pinctrl-0 = <&sata_default_pins>;
218 pinctrl-1 = <&sata_and 218 pinctrl-1 = <&sata_and_ide_pins>;
219 syscon = <&syscon>; 219 syscon = <&syscon>;
220 status = "disabled"; 220 status = "disabled";
221 }; 221 };
222 222
223 intcon: interrupt-controller@4 223 intcon: interrupt-controller@48000000 {
224 compatible = "faraday, 224 compatible = "faraday,ftintc010";
225 reg = <0x48000000 0x10 225 reg = <0x48000000 0x1000>;
226 resets = <&syscon GEMI 226 resets = <&syscon GEMINI_RESET_INTCON0>;
227 interrupt-controller; 227 interrupt-controller;
228 #interrupt-cells = <2> 228 #interrupt-cells = <2>;
229 }; 229 };
230 230
231 power-controller@4b000000 { 231 power-controller@4b000000 {
232 compatible = "cortina, 232 compatible = "cortina,gemini-power-controller";
233 reg = <0x4b000000 0x10 233 reg = <0x4b000000 0x100>;
234 interrupts = <26 IRQ_T 234 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
235 pinctrl-names = "defau 235 pinctrl-names = "default";
236 pinctrl-0 = <&power_de 236 pinctrl-0 = <&power_default_pins>;
237 }; 237 };
238 238
239 gpio0: gpio@4d000000 { 239 gpio0: gpio@4d000000 {
240 compatible = "cortina, 240 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
241 reg = <0x4d000000 0x10 241 reg = <0x4d000000 0x100>;
242 interrupts = <22 IRQ_T 242 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
243 resets = <&syscon GEMI 243 resets = <&syscon GEMINI_RESET_GPIO0>;
244 clocks = <&syscon GEMI 244 clocks = <&syscon GEMINI_CLK_APB>;
245 gpio-controller; 245 gpio-controller;
246 #gpio-cells = <2>; 246 #gpio-cells = <2>;
247 interrupt-controller; 247 interrupt-controller;
248 #interrupt-cells = <2> 248 #interrupt-cells = <2>;
249 }; 249 };
250 250
251 gpio1: gpio@4e000000 { 251 gpio1: gpio@4e000000 {
252 compatible = "cortina, 252 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
253 reg = <0x4e000000 0x10 253 reg = <0x4e000000 0x100>;
254 interrupts = <23 IRQ_T 254 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
255 resets = <&syscon GEMI 255 resets = <&syscon GEMINI_RESET_GPIO1>;
256 clocks = <&syscon GEMI 256 clocks = <&syscon GEMINI_CLK_APB>;
257 gpio-controller; 257 gpio-controller;
258 #gpio-cells = <2>; 258 #gpio-cells = <2>;
259 interrupt-controller; 259 interrupt-controller;
260 #interrupt-cells = <2> 260 #interrupt-cells = <2>;
261 }; 261 };
262 262
263 gpio2: gpio@4f000000 { 263 gpio2: gpio@4f000000 {
264 compatible = "cortina, 264 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
265 reg = <0x4f000000 0x10 265 reg = <0x4f000000 0x100>;
266 interrupts = <24 IRQ_T 266 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
267 resets = <&syscon GEMI 267 resets = <&syscon GEMINI_RESET_GPIO2>;
268 clocks = <&syscon GEMI 268 clocks = <&syscon GEMINI_CLK_APB>;
269 gpio-controller; 269 gpio-controller;
270 #gpio-cells = <2>; 270 #gpio-cells = <2>;
271 interrupt-controller; 271 interrupt-controller;
272 #interrupt-cells = <2> 272 #interrupt-cells = <2>;
273 }; 273 };
274 274
275 pci@50000000 { 275 pci@50000000 {
276 compatible = "cortina, 276 compatible = "cortina,gemini-pci", "faraday,ftpci100";
277 /* 277 /*
278 * The first 256 bytes 278 * The first 256 bytes in the IO range is actually used
279 * to configure the ho 279 * to configure the host bridge.
280 */ 280 */
281 reg = <0x50000000 0x10 281 reg = <0x50000000 0x100>;
282 resets = <&syscon GEMI 282 resets = <&syscon GEMINI_RESET_PCI>;
283 clocks = <&syscon GEMI 283 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
284 clock-names = "PCLK", 284 clock-names = "PCLK", "PCICLK";
285 pinctrl-names = "defau 285 pinctrl-names = "default";
286 pinctrl-0 = <&pci_defa 286 pinctrl-0 = <&pci_default_pins>;
287 device_type = "pci"; 287 device_type = "pci";
288 #address-cells = <3>; 288 #address-cells = <3>;
289 #size-cells = <2>; 289 #size-cells = <2>;
290 status = "disabled"; 290 status = "disabled";
291 291
292 #interrupt-cells = <1> 292 #interrupt-cells = <1>;
293 interrupt-map-mask = < 293 interrupt-map-mask = <0xf800 0 0 7>;
294 interrupt-map = 294 interrupt-map =
295 <0x4800 0 0 1 295 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
296 <0x4800 0 0 2 296 <0x4800 0 0 2 &pci_intc 1>,
297 <0x4800 0 0 3 297 <0x4800 0 0 3 &pci_intc 2>,
298 <0x4800 0 0 4 298 <0x4800 0 0 4 &pci_intc 3>,
299 <0x5000 0 0 1 299 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
300 <0x5000 0 0 2 300 <0x5000 0 0 2 &pci_intc 2>,
301 <0x5000 0 0 3 301 <0x5000 0 0 3 &pci_intc 3>,
302 <0x5000 0 0 4 302 <0x5000 0 0 4 &pci_intc 0>,
303 <0x5800 0 0 1 303 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
304 <0x5800 0 0 2 304 <0x5800 0 0 2 &pci_intc 3>,
305 <0x5800 0 0 3 305 <0x5800 0 0 3 &pci_intc 0>,
306 <0x5800 0 0 4 306 <0x5800 0 0 4 &pci_intc 1>,
307 <0x6000 0 0 1 307 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
308 <0x6000 0 0 2 308 <0x6000 0 0 2 &pci_intc 0>,
309 <0x6000 0 0 3 309 <0x6000 0 0 3 &pci_intc 1>,
310 <0x6000 0 0 4 310 <0x6000 0 0 4 &pci_intc 2>;
311 311
312 bus-range = <0x00 0xff 312 bus-range = <0x00 0xff>;
313 /* PCI ranges mappings 313 /* PCI ranges mappings */
314 ranges = 314 ranges =
315 /* 1MiB I/O space 0x50 315 /* 1MiB I/O space 0x50000000-0x500fffff */
316 <0x01000000 0 0 316 <0x01000000 0 0 0x50000000 0 0x00100000>,
317 /* 128MiB non-prefetch 317 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
318 <0x02000000 0 0x580000 318 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
319 319
320 /* DMA ranges */ 320 /* DMA ranges */
321 dma-ranges = 321 dma-ranges =
322 /* 128MiB at 0x0000000 322 /* 128MiB at 0x00000000-0x07ffffff */
323 <0x02000000 0 0x000000 323 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
324 /* 64MiB at 0x00000000 324 /* 64MiB at 0x00000000-0x03ffffff */
325 <0x02000000 0 0x000000 325 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
326 /* 64MiB at 0x00000000 326 /* 64MiB at 0x00000000-0x03ffffff */
327 <0x02000000 0 0x000000 327 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
328 328
329 /* 329 /*
330 * This PCI host bridg 330 * This PCI host bridge variant has a cascaded interrupt
331 * controller embedded 331 * controller embedded in the host bridge.
332 */ 332 */
333 pci_intc: interrupt-co 333 pci_intc: interrupt-controller {
334 interrupt-pare 334 interrupt-parent = <&intcon>;
335 interrupts = < 335 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-cont 336 interrupt-controller;
337 #address-cells 337 #address-cells = <0>;
338 #interrupt-cel 338 #interrupt-cells = <1>;
339 }; 339 };
340 }; 340 };
341 341
342 ethernet: ethernet@60000000 { 342 ethernet: ethernet@60000000 {
343 compatible = "cortina, 343 compatible = "cortina,gemini-ethernet";
344 reg = <0x60000000 0x40 344 reg = <0x60000000 0x4000>, /* Global registers, queue */
345 <0x60004000 0x20 345 <0x60004000 0x2000>, /* V-bit */
346 <0x60006000 0x20 346 <0x60006000 0x2000>; /* A-bit */
347 pinctrl-names = "defau 347 pinctrl-names = "default";
348 pinctrl-0 = <&gmii_def 348 pinctrl-0 = <&gmii_default_pins>;
349 status = "disabled"; 349 status = "disabled";
350 #address-cells = <1>; 350 #address-cells = <1>;
351 #size-cells = <1>; 351 #size-cells = <1>;
352 ranges; 352 ranges;
353 353
354 gmac0: ethernet-port@0 354 gmac0: ethernet-port@0 {
355 compatible = " 355 compatible = "cortina,gemini-ethernet-port";
356 reg = <0x60008 356 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
357 <0x6000a 357 <0x6000a000 0x2000>; /* Port 0 GMAC */
358 interrupt-pare 358 interrupt-parent = <&intcon>;
359 interrupts = < 359 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
360 resets = <&sys 360 resets = <&syscon GEMINI_RESET_GMAC0>;
361 clocks = <&sys 361 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
362 clock-names = 362 clock-names = "PCLK";
363 }; 363 };
364 364
365 gmac1: ethernet-port@1 365 gmac1: ethernet-port@1 {
366 compatible = " 366 compatible = "cortina,gemini-ethernet-port";
367 reg = <0x6000c 367 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
368 <0x6000e 368 <0x6000e000 0x2000>; /* Port 1 GMAC */
369 interrupt-pare 369 interrupt-parent = <&intcon>;
370 interrupts = < 370 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
371 resets = <&sys 371 resets = <&syscon GEMINI_RESET_GMAC1>;
372 clocks = <&sys 372 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
373 clock-names = 373 clock-names = "PCLK";
374 }; 374 };
375 }; 375 };
376 376
377 crypto: crypto@62000000 { 377 crypto: crypto@62000000 {
378 compatible = "cortina, 378 compatible = "cortina,sl3516-crypto";
379 reg = <0x62000000 0x10 379 reg = <0x62000000 0x10000>;
380 interrupts = <7 IRQ_TY 380 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
381 resets = <&syscon GEMI 381 resets = <&syscon GEMINI_RESET_SECURITY>;
382 clocks = <&syscon GEMI 382 clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
383 }; 383 };
384 384
385 ide0: ide@63000000 { 385 ide0: ide@63000000 {
386 compatible = "cortina, 386 compatible = "cortina,gemini-pata", "faraday,ftide010";
387 reg = <0x63000000 0x10 387 reg = <0x63000000 0x1000>;
388 interrupts = <4 IRQ_TY 388 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
389 resets = <&syscon GEMI 389 resets = <&syscon GEMINI_RESET_IDE>;
390 clocks = <&syscon GEMI 390 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
391 clock-names = "PCLK"; 391 clock-names = "PCLK";
392 sata = <&sata>; 392 sata = <&sata>;
393 status = "disabled"; 393 status = "disabled";
394 #address-cells = <1>; 394 #address-cells = <1>;
395 #size-cells = <0>; 395 #size-cells = <0>;
396 }; 396 };
397 397
398 ide1: ide@63400000 { 398 ide1: ide@63400000 {
399 compatible = "cortina, 399 compatible = "cortina,gemini-pata", "faraday,ftide010";
400 reg = <0x63400000 0x10 400 reg = <0x63400000 0x1000>;
401 interrupts = <5 IRQ_TY 401 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
402 resets = <&syscon GEMI 402 resets = <&syscon GEMINI_RESET_IDE>;
403 clocks = <&syscon GEMI 403 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
404 clock-names = "PCLK"; 404 clock-names = "PCLK";
405 sata = <&sata>; 405 sata = <&sata>;
406 status = "disabled"; 406 status = "disabled";
407 #address-cells = <1>; 407 #address-cells = <1>;
408 #size-cells = <0>; 408 #size-cells = <0>;
409 }; 409 };
410 410
411 dma-controller@67000000 { 411 dma-controller@67000000 {
412 compatible = "faraday, 412 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
413 /* Faraday Technology 413 /* Faraday Technology FTDMAC020 variant */
414 arm,primecell-periphid 414 arm,primecell-periphid = <0x0003b080>;
415 reg = <0x67000000 0x10 415 reg = <0x67000000 0x1000>;
416 interrupts = <9 IRQ_TY 416 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
417 resets = <&syscon GEMI 417 resets = <&syscon GEMINI_RESET_DMAC>;
418 clocks = <&syscon GEMI 418 clocks = <&syscon GEMINI_CLK_AHB>;
419 clock-names = "apb_pcl 419 clock-names = "apb_pclk";
420 /* Bus interface AHB1 420 /* Bus interface AHB1 (AHB0) is totally tilted */
421 lli-bus-interface-ahb2 421 lli-bus-interface-ahb2;
422 mem-bus-interface-ahb2 422 mem-bus-interface-ahb2;
423 memcpy-burst-size = <2 423 memcpy-burst-size = <256>;
424 memcpy-bus-width = <32 424 memcpy-bus-width = <32>;
425 #dma-cells = <2>; 425 #dma-cells = <2>;
426 }; 426 };
427 427
428 display-controller@6a000000 { 428 display-controller@6a000000 {
429 compatible = "cortina, 429 compatible = "cortina,gemini-tvc", "faraday,tve200";
430 reg = <0x6a000000 0x10 430 reg = <0x6a000000 0x1000>;
431 interrupts = <13 IRQ_T 431 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
432 resets = <&syscon GEMI 432 resets = <&syscon GEMINI_RESET_TVC>;
433 clocks = <&syscon GEMI 433 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
434 <&syscon GEMI 434 <&syscon GEMINI_CLK_TVC>;
435 clock-names = "PCLK", 435 clock-names = "PCLK", "TVE";
436 pinctrl-names = "defau 436 pinctrl-names = "default";
437 pinctrl-0 = <&tvc_defa 437 pinctrl-0 = <&tvc_default_pins>;
438 status = "disabled"; 438 status = "disabled";
439 }; 439 };
440 440
441 usb0: usb@68000000 { 441 usb0: usb@68000000 {
442 compatible = "cortina, 442 compatible = "cortina,gemini-usb", "faraday,fotg200";
443 reg = <0x68000000 0x10 443 reg = <0x68000000 0x1000>;
444 interrupts = <10 IRQ_T 444 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
445 resets = <&syscon GEMI 445 resets = <&syscon GEMINI_RESET_USB0>;
446 clocks = <&syscon GEMI 446 clocks = <&syscon GEMINI_CLK_GATE_USB0>;
447 clock-names = "PCLK"; 447 clock-names = "PCLK";
448 /* 448 /*
449 * This will claim pin 449 * This will claim pins for USB0 and USB1 at the same
450 * time as they are us 450 * time as they are using some common pins. If you for
451 * some reason have a 451 * some reason have a system using USB1 at 96000000 but
452 * NOT using USB0 at 6 452 * NOT using USB0 at 68000000 you wll have to add the
453 * usb_default_pins to 453 * usb_default_pins to the USB controller at 96000000
454 * in your .dts for th 454 * in your .dts for the board.
455 */ 455 */
456 pinctrl-names = "defau 456 pinctrl-names = "default";
457 pinctrl-0 = <&usb_defa 457 pinctrl-0 = <&usb_default_pins>;
458 /* Default to host mod 458 /* Default to host mode */
459 dr_mode = "host"; 459 dr_mode = "host";
460 syscon = <&syscon>; 460 syscon = <&syscon>;
461 status = "disabled"; 461 status = "disabled";
462 }; 462 };
463 463
464 usb1: usb@69000000 { 464 usb1: usb@69000000 {
465 compatible = "cortina, 465 compatible = "cortina,gemini-usb", "faraday,fotg200";
466 reg = <0x69000000 0x10 466 reg = <0x69000000 0x1000>;
467 interrupts = <11 IRQ_T 467 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
468 resets = <&syscon GEMI 468 resets = <&syscon GEMINI_RESET_USB1>;
469 clocks = <&syscon GEMI 469 clocks = <&syscon GEMINI_CLK_GATE_USB1>;
470 clock-names = "PCLK"; 470 clock-names = "PCLK";
471 syscon = <&syscon>; 471 syscon = <&syscon>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 }; 474 };
475 }; 475 };
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