1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * HiSilicon Ltd. Hi3620 SoC
4 *
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
7 *
8 * Author: Haojian Zhuang <haojian.zhuang@linar
9 */
10
11 #include <dt-bindings/clock/hi3620-clock.h>
12
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 serial3 = &uart3;
22 serial4 = &uart4;
23 };
24
25 pclk: clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35 enable-method = "hisilicon,hi3
36
37 cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cort
40 reg = <0x0>;
41 next-level-cache = <&L
42 };
43
44 cpu@1 {
45 compatible = "arm,cort
46 device_type = "cpu";
47 reg = <1>;
48 next-level-cache = <&L
49 };
50
51 cpu@2 {
52 compatible = "arm,cort
53 device_type = "cpu";
54 reg = <2>;
55 next-level-cache = <&L
56 };
57
58 cpu@3 {
59 compatible = "arm,cort
60 device_type = "cpu";
61 reg = <3>;
62 next-level-cache = <&L
63 };
64 };
65
66 amba-bus {
67
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 ranges = <0 0xfc000000 0x20000
73
74 L2: cache-controller {
75 compatible = "arm,pl31
76 reg = <0x100000 0x1000
77 interrupts = <0 15 4>;
78 cache-unified;
79 cache-level = <2>;
80 };
81
82 gic: interrupt-controller@1000
83 compatible = "arm,cort
84 #interrupt-cells = <3>
85 #address-cells = <0>;
86 interrupt-controller;
87 /* gic dist base, gic
88 reg = <0x1000 0x1000>,
89 };
90
91 sysctrl: system-controller@802
92 compatible = "hisilico
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x802000 0
96 reg = <0x802000 0x1000
97
98 smp-offset = <0x31c>;
99 resume-offset = <0x308
100 reboot-offset = <0x4>;
101
102 clock: clock@0 {
103 compatible = "
104 reg = <0 0x100
105 #clock-cells =
106 };
107 };
108
109 dual_timer0: dual_timer@800000
110 compatible = "arm,sp80
111 reg = <0x800000 0x1000
112 /* timer00 & timer01 *
113 interrupts = <0 0 4>,
114 clocks = <&clock HI362
115 <&clock HI362
116 <&clock HI362
117 clock-names = "timer0c
118 status = "disabled";
119 };
120
121 dual_timer1: dual_timer@801000
122 compatible = "arm,sp80
123 reg = <0x801000 0x1000
124 /* timer10 & timer11 *
125 interrupts = <0 2 4>,
126 clocks = <&clock HI362
127 <&clock HI362
128 <&clock HI362
129 clock-names = "timer0c
130 status = "disabled";
131 };
132
133 dual_timer2: dual_timer@a01000
134 compatible = "arm,sp80
135 reg = <0xa01000 0x1000
136 /* timer20 & timer21 *
137 interrupts = <0 4 4>,
138 clocks = <&clock HI362
139 <&clock HI362
140 <&clock HI362
141 clock-names = "timer0l
142 status = "disabled";
143 };
144
145 dual_timer3: dual_timer@a02000
146 compatible = "arm,sp80
147 reg = <0xa02000 0x1000
148 /* timer30 & timer31 *
149 interrupts = <0 6 4>,
150 clocks = <&clock HI362
151 <&clock HI362
152 <&clock HI362
153 clock-names = "timer0c
154 status = "disabled";
155 };
156
157 dual_timer4: dual_timer@a03000
158 compatible = "arm,sp80
159 reg = <0xa03000 0x1000
160 /* timer40 & timer41 *
161 interrupts = <0 96 4>,
162 clocks = <&clock HI362
163 <&clock HI362
164 <&clock HI362
165 clock-names = "timer0c
166 status = "disabled";
167 };
168
169 timer5: timer@600 {
170 compatible = "arm,cort
171 reg = <0x600 0x20>;
172 interrupts = <1 13 0xf
173 };
174
175 uart0: serial@b00000 {
176 compatible = "arm,pl01
177 reg = <0xb00000 0x1000
178 interrupts = <0 20 4>;
179 clocks = <&clock HI362
180 clock-names = "uartclk
181 status = "disabled";
182 };
183
184 uart1: serial@b01000 {
185 compatible = "arm,pl01
186 reg = <0xb01000 0x1000
187 interrupts = <0 21 4>;
188 clocks = <&clock HI362
189 clock-names = "uartclk
190 status = "disabled";
191 };
192
193 uart2: serial@b02000 {
194 compatible = "arm,pl01
195 reg = <0xb02000 0x1000
196 interrupts = <0 22 4>;
197 clocks = <&clock HI362
198 clock-names = "uartclk
199 status = "disabled";
200 };
201
202 uart3: serial@b03000 {
203 compatible = "arm,pl01
204 reg = <0xb03000 0x1000
205 interrupts = <0 23 4>;
206 clocks = <&clock HI362
207 clock-names = "uartclk
208 status = "disabled";
209 };
210
211 uart4: serial@b04000 {
212 compatible = "arm,pl01
213 reg = <0xb04000 0x1000
214 interrupts = <0 24 4>;
215 clocks = <&clock HI362
216 clock-names = "uartclk
217 status = "disabled";
218 };
219
220 gpio0: gpio@806000 {
221 compatible = "arm,pl06
222 reg = <0x806000 0x1000
223 interrupts = <0 64 0x4
224 gpio-controller;
225 #gpio-cells = <2>;
226 gpio-ranges = < &pmx0
227 &pmx0
228 interrupt-controller;
229 #interrupt-cells = <2>
230 clocks = <&clock HI362
231 clock-names = "apb_pcl
232 };
233
234 gpio1: gpio@807000 {
235 compatible = "arm,pl06
236 reg = <0x807000 0x1000
237 interrupts = <0 65 0x4
238 gpio-controller;
239 #gpio-cells = <2>;
240 gpio-ranges = < &pmx0
241 &pmx0
242 &pmx0
243 interrupt-controller;
244 #interrupt-cells = <2>
245 clocks = <&clock HI362
246 clock-names = "apb_pcl
247 };
248
249 gpio2: gpio@808000 {
250 compatible = "arm,pl06
251 reg = <0x808000 0x1000
252 interrupts = <0 66 0x4
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio-ranges = < &pmx0
256 &pmx0
257 &pmx0
258 interrupt-controller;
259 #interrupt-cells = <2>
260 clocks = <&clock HI362
261 clock-names = "apb_pcl
262 };
263
264 gpio3: gpio@809000 {
265 compatible = "arm,pl06
266 reg = <0x809000 0x1000
267 interrupts = <0 67 0x4
268 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-ranges = < &pmx0
271 &pmx0
272 &pmx0
273 interrupt-controller;
274 #interrupt-cells = <2>
275 clocks = <&clock HI362
276 clock-names = "apb_pcl
277 };
278
279 gpio4: gpio@80a000 {
280 compatible = "arm,pl06
281 reg = <0x80a000 0x1000
282 interrupts = <0 68 0x4
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = < &pmx0
286 &pmx0
287 &pmx0
288 interrupt-controller;
289 #interrupt-cells = <2>
290 clocks = <&clock HI362
291 clock-names = "apb_pcl
292 };
293
294 gpio5: gpio@80b000 {
295 compatible = "arm,pl06
296 reg = <0x80b000 0x1000
297 interrupts = <0 69 0x4
298 gpio-controller;
299 #gpio-cells = <2>;
300 gpio-ranges = < &pmx0
301 &pmx0
302 &pmx0
303 interrupt-controller;
304 #interrupt-cells = <2>
305 clocks = <&clock HI362
306 clock-names = "apb_pcl
307 };
308
309 gpio6: gpio@80c000 {
310 compatible = "arm,pl06
311 reg = <0x80c000 0x1000
312 interrupts = <0 70 0x4
313 gpio-controller;
314 #gpio-cells = <2>;
315 gpio-ranges = < &pmx0
316 &pmx0
317 &pmx0
318 interrupt-controller;
319 #interrupt-cells = <2>
320 clocks = <&clock HI362
321 clock-names = "apb_pcl
322 };
323
324 gpio7: gpio@80d000 {
325 compatible = "arm,pl06
326 reg = <0x80d000 0x1000
327 interrupts = <0 71 0x4
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = < &pmx0
331 &pmx0
332 &pmx0
333 interrupt-controller;
334 #interrupt-cells = <2>
335 clocks = <&clock HI362
336 clock-names = "apb_pcl
337 };
338
339 gpio8: gpio@80e000 {
340 compatible = "arm,pl06
341 reg = <0x80e000 0x1000
342 interrupts = <0 72 0x4
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = < &pmx0
346 &pmx0
347 &pmx0
348 interrupt-controller;
349 #interrupt-cells = <2>
350 clocks = <&clock HI362
351 clock-names = "apb_pcl
352 };
353
354 gpio9: gpio@80f000 {
355 compatible = "arm,pl06
356 reg = <0x80f000 0x1000
357 interrupts = <0 73 0x4
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = < &pmx0
361 &pmx0
362 &pmx0
363 interrupt-controller;
364 #interrupt-cells = <2>
365 clocks = <&clock HI362
366 clock-names = "apb_pcl
367 };
368
369 gpio10: gpio@810000 {
370 compatible = "arm,pl06
371 reg = <0x810000 0x1000
372 interrupts = <0 74 0x4
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = < &pmx0
376 &pmx0
377 interrupt-controller;
378 #interrupt-cells = <2>
379 clocks = <&clock HI362
380 clock-names = "apb_pcl
381 };
382
383 gpio11: gpio@811000 {
384 compatible = "arm,pl06
385 reg = <0x811000 0x1000
386 interrupts = <0 75 0x4
387 gpio-controller;
388 #gpio-cells = <2>;
389 gpio-ranges = < &pmx0
390 &pmx0
391 &pmx0
392 interrupt-controller;
393 #interrupt-cells = <2>
394 clocks = <&clock HI362
395 clock-names = "apb_pcl
396 };
397
398 gpio12: gpio@812000 {
399 compatible = "arm,pl06
400 reg = <0x812000 0x1000
401 interrupts = <0 76 0x4
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-ranges = < &pmx0
405 &pmx0
406 &pmx0
407 interrupt-controller;
408 #interrupt-cells = <2>
409 clocks = <&clock HI362
410 clock-names = "apb_pcl
411 };
412
413 gpio13: gpio@813000 {
414 compatible = "arm,pl06
415 reg = <0x813000 0x1000
416 interrupts = <0 77 0x4
417 gpio-controller;
418 #gpio-cells = <2>;
419 gpio-ranges = < &pmx0
420 &pmx0
421 &pmx0
422 interrupt-controller;
423 #interrupt-cells = <2>
424 clocks = <&clock HI362
425 clock-names = "apb_pcl
426 };
427
428 gpio14: gpio@814000 {
429 compatible = "arm,pl06
430 reg = <0x814000 0x1000
431 interrupts = <0 78 0x4
432 gpio-controller;
433 #gpio-cells = <2>;
434 gpio-ranges = < &pmx0
435 &pmx0
436 &pmx0
437 interrupt-controller;
438 #interrupt-cells = <2>
439 clocks = <&clock HI362
440 clock-names = "apb_pcl
441 };
442
443 gpio15: gpio@815000 {
444 compatible = "arm,pl06
445 reg = <0x815000 0x1000
446 interrupts = <0 79 0x4
447 gpio-controller;
448 #gpio-cells = <2>;
449 gpio-ranges = < &pmx0
450 &pmx0
451 &pmx0
452 interrupt-controller;
453 #interrupt-cells = <2>
454 clocks = <&clock HI362
455 clock-names = "apb_pcl
456 };
457
458 gpio16: gpio@816000 {
459 compatible = "arm,pl06
460 reg = <0x816000 0x1000
461 interrupts = <0 80 0x4
462 gpio-controller;
463 #gpio-cells = <2>;
464 gpio-ranges = < &pmx0
465 &pmx0
466 &pmx0
467 interrupt-controller;
468 #interrupt-cells = <2>
469 clocks = <&clock HI362
470 clock-names = "apb_pcl
471 };
472
473 gpio17: gpio@817000 {
474 compatible = "arm,pl06
475 reg = <0x817000 0x1000
476 interrupts = <0 81 0x4
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = < &pmx0
480 &pmx0
481 &pmx0
482 interrupt-controller;
483 #interrupt-cells = <2>
484 clocks = <&clock HI362
485 clock-names = "apb_pcl
486 };
487
488 gpio18: gpio@818000 {
489 compatible = "arm,pl06
490 reg = <0x818000 0x1000
491 interrupts = <0 82 0x4
492 gpio-controller;
493 #gpio-cells = <2>;
494 gpio-ranges = < &pmx0
495 &pmx0
496 &pmx0
497 interrupt-controller;
498 #interrupt-cells = <2>
499 clocks = <&clock HI362
500 clock-names = "apb_pcl
501 };
502
503 gpio19: gpio@819000 {
504 compatible = "arm,pl06
505 reg = <0x819000 0x1000
506 interrupts = <0 83 0x4
507 gpio-controller;
508 #gpio-cells = <2>;
509 gpio-ranges = < &pmx0
510 &pmx0
511 interrupt-controller;
512 #interrupt-cells = <2>
513 clocks = <&clock HI362
514 clock-names = "apb_pcl
515 };
516
517 gpio20: gpio@81a000 {
518 compatible = "arm,pl06
519 reg = <0x81a000 0x1000
520 interrupts = <0 84 0x4
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = < &pmx0
524 &pmx0
525 interrupt-controller;
526 #interrupt-cells = <2>
527 clocks = <&clock HI362
528 clock-names = "apb_pcl
529 };
530
531 gpio21: gpio@81b000 {
532 compatible = "arm,pl06
533 reg = <0x81b000 0x1000
534 interrupts = <0 85 0x4
535 gpio-controller;
536 #gpio-cells = <2>;
537 gpio-ranges = < &pmx0
538 interrupt-controller;
539 #interrupt-cells = <2>
540 clocks = <&clock HI362
541 clock-names = "apb_pcl
542 };
543
544 pmx0: pinmux@803000 {
545 compatible = "pinctrl-
546 reg = <0x803000 0x188>
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #pinctrl-cells = <1>;
550 #gpio-range-cells = <3
551
552 pinctrl-single,registe
553 pinctrl-single,functio
554 /* pin base, nr pins &
555 pinctrl-single,gpio-ra
556
557
558
559
560 range: gpio-range {
561 #pinctrl-singl
562 };
563 };
564
565 pmx1: pinmux@803800 {
566 compatible = "pinconf-
567 reg = <0x803800 0x2dc>
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #pinctrl-cells = <1>;
571
572 pinctrl-single,registe
573 };
574 };
575 };
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