1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2014 Linaro Ltd. 4 * Copyright (c) 2013-2014 HiSilicon Limited. 5 */ 6 7 /dts-v1/; 8 #include "hisi-x5hd2.dtsi" 9 10 / { 11 model = "Hisilicon HIX5HD2 Development 12 compatible = "hisilicon,hix5hd2"; 13 14 chosen { 15 stdout-path = "serial0:115200n 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 enable-method = "hisilicon,hix 22 23 cpu@0 { 24 compatible = "arm,cort 25 device_type = "cpu"; 26 reg = <0>; 27 next-level-cache = <&l 28 }; 29 30 cpu@1 { 31 compatible = "arm,cort 32 device_type = "cpu"; 33 reg = <1>; 34 next-level-cache = <&l 35 }; 36 }; 37 38 memory@0 { 39 device_type = "memory"; 40 reg = <0x00000000 0x80000000>; 41 }; 42 }; 43 44 &timer0 { 45 status = "okay"; 46 }; 47 48 &uart0 { 49 status = "okay"; 50 }; 51 52 &gmac0 { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 phy-handle = <&phy2>; 56 phy-mode = "mii"; 57 /* Placeholder, overwritten by bootloa 58 mac-address = [00 00 00 00 00 00]; 59 status = "okay"; 60 61 phy2: ethernet-phy@2 { 62 reg = <2>; 63 }; 64 }; 65 66 &gmac1 { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 phy-handle = <&phy1>; 70 phy-mode = "rgmii"; 71 /* Placeholder, overwritten by bootloa 72 mac-address = [00 00 00 00 00 00]; 73 status = "okay"; 74 75 phy1: ethernet-phy@1 { 76 reg = <1>; 77 }; 78 }; 79 80 &ahci { 81 phys = <&sata_phy>; 82 phy-names = "sata-phy"; 83 };
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