1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (c) 2020 HiSilicon Limited. 3 * Copyright (c) 2020 HiSilicon Limited.
4 * 4 *
5 * DTS file for Hisilicon SD5203 Board 5 * DTS file for Hisilicon SD5203 Board
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 / { 10 / {
11 model = "Hisilicon SD5203"; 11 model = "Hisilicon SD5203";
12 compatible = "H836ASDJ", "hisilicon,sd 12 compatible = "H836ASDJ", "hisilicon,sd5203";
13 interrupt-parent = <&vic>; 13 interrupt-parent = <&vic>;
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 16
17 chosen { 17 chosen {
18 bootargs = "console=ttyS0,9600 18 bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
19 }; 19 };
20 20
21 aliases { 21 aliases {
22 serial0 = &uart0; 22 serial0 = &uart0;
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu0 { 29 cpu0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,arm9 31 compatible = "arm,arm926ej-s";
32 reg = <0x0>; 32 reg = <0x0>;
33 }; 33 };
34 }; 34 };
35 35
36 memory@30000000 { 36 memory@30000000 {
37 device_type = "memory"; 37 device_type = "memory";
38 reg = <0x30000000 0x8000000>; 38 reg = <0x30000000 0x8000000>;
39 }; 39 };
40 40
41 soc { 41 soc {
42 #address-cells = <1>; 42 #address-cells = <1>;
43 #size-cells = <1>; 43 #size-cells = <1>;
44 compatible = "simple-bus"; 44 compatible = "simple-bus";
45 ranges; 45 ranges;
46 46
47 vic: interrupt-controller@1013 47 vic: interrupt-controller@10130000 {
48 compatible = "snps,dw- 48 compatible = "snps,dw-apb-ictl";
49 reg = <0x10130000 0x10 49 reg = <0x10130000 0x1000>;
50 interrupt-controller; 50 interrupt-controller;
51 #interrupt-cells = <1> 51 #interrupt-cells = <1>;
52 }; 52 };
53 53
54 refclk125mhz: refclk125mhz { 54 refclk125mhz: refclk125mhz {
55 compatible = "fixed-cl 55 compatible = "fixed-clock";
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 clock-frequency = <125 57 clock-frequency = <125000000>;
58 }; 58 };
59 59
60 timer0: timer@16002000 { 60 timer0: timer@16002000 {
61 compatible = "arm,sp80 61 compatible = "arm,sp804", "arm,primecell";
62 reg = <0x16002000 0x10 62 reg = <0x16002000 0x1000>;
63 interrupts = <4>; 63 interrupts = <4>;
64 clocks = <&refclk125mh 64 clocks = <&refclk125mhz>;
65 clock-names = "apb_pcl 65 clock-names = "apb_pclk";
66 }; 66 };
67 67
68 timer1: timer@16003000 { 68 timer1: timer@16003000 {
69 compatible = "arm,sp80 69 compatible = "arm,sp804", "arm,primecell";
70 reg = <0x16003000 0x10 70 reg = <0x16003000 0x1000>;
71 interrupts = <5>; 71 interrupts = <5>;
72 clocks = <&refclk125mh 72 clocks = <&refclk125mhz>;
73 clock-names = "apb_pcl 73 clock-names = "apb_pclk";
74 }; 74 };
75 75
76 uart0: serial@1600d000 { 76 uart0: serial@1600d000 {
77 compatible = "snps,dw- 77 compatible = "snps,dw-apb-uart";
78 reg = <0x1600d000 0x10 78 reg = <0x1600d000 0x1000>;
79 bus_id = "uart0"; 79 bus_id = "uart0";
80 clocks = <&refclk125mh 80 clocks = <&refclk125mhz>;
81 clock-names = "baudclk 81 clock-names = "baudclk", "apb_pclk";
82 reg-shift = <2>; 82 reg-shift = <2>;
83 interrupts = <17>; 83 interrupts = <17>;
84 }; 84 };
85 85
86 uart1: serial@1600c000 { 86 uart1: serial@1600c000 {
87 compatible = "snps,dw- 87 compatible = "snps,dw-apb-uart";
88 reg = <0x1600c000 0x10 88 reg = <0x1600c000 0x1000>;
89 clocks = <&refclk125mh 89 clocks = <&refclk125mhz>;
90 clock-names = "baudclk 90 clock-names = "baudclk", "apb_pclk";
91 reg-shift = <2>; 91 reg-shift = <2>;
92 interrupts = <16>; 92 interrupts = <16>;
93 status = "disabled"; 93 status = "disabled";
94 }; 94 };
95 }; 95 };
96 }; 96 };
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