1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2012 Altera <www.altera.com> 3 * Copyright (C) 2012 Altera <www.altera.com>
4 */ 4 */
5 5
6 #include <dt-bindings/reset/altr,rst-mgr.h> 6 #include <dt-bindings/reset/altr,rst-mgr.h>
7 7
8 / { 8 / {
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 11
12 aliases { 12 aliases {
13 serial0 = &uart0; 13 serial0 = &uart0;
14 serial1 = &uart1; 14 serial1 = &uart1;
15 timer0 = &timer0; 15 timer0 = &timer0;
16 timer1 = &timer1; 16 timer1 = &timer1;
17 timer2 = &timer2; 17 timer2 = &timer2;
18 timer3 = &timer3; 18 timer3 = &timer3;
19 }; 19 };
20 20
21 cpus { 21 cpus {
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <0>; 23 #size-cells = <0>;
24 enable-method = "altr,socfpga- 24 enable-method = "altr,socfpga-smp";
25 25
26 cpu0: cpu@0 { 26 cpu0: cpu@0 {
27 compatible = "arm,cort 27 compatible = "arm,cortex-a9";
28 device_type = "cpu"; 28 device_type = "cpu";
29 reg = <0>; 29 reg = <0>;
30 next-level-cache = <&L 30 next-level-cache = <&L2>;
31 }; 31 };
32 cpu1: cpu@1 { 32 cpu1: cpu@1 {
33 compatible = "arm,cort 33 compatible = "arm,cortex-a9";
34 device_type = "cpu"; 34 device_type = "cpu";
35 reg = <1>; 35 reg = <1>;
36 next-level-cache = <&L 36 next-level-cache = <&L2>;
37 }; 37 };
38 }; 38 };
39 39
40 pmu: pmu@ff111000 { 40 pmu: pmu@ff111000 {
41 compatible = "arm,cortex-a9-pm 41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>; 42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, 44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>, 45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>; 46 <0xff113000 0x1000>;
47 }; 47 };
48 48
49 intc: interrupt-controller@fffed000 { 49 intc: interrupt-controller@fffed000 {
50 compatible = "arm,cortex-a9-gi 50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>; 51 #interrupt-cells = <3>;
52 interrupt-controller; 52 interrupt-controller;
53 reg = <0xfffed000 0x1000>, 53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>; 54 <0xfffec100 0x100>;
55 }; 55 };
56 56
57 soc { 57 soc {
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <1>; 59 #size-cells = <1>;
60 compatible = "simple-bus"; 60 compatible = "simple-bus";
61 device_type = "soc"; 61 device_type = "soc";
62 interrupt-parent = <&intc>; 62 interrupt-parent = <&intc>;
63 ranges; 63 ranges;
64 64
65 amba { 65 amba {
66 compatible = "simple-b 66 compatible = "simple-bus";
67 #address-cells = <1>; 67 #address-cells = <1>;
68 #size-cells = <1>; 68 #size-cells = <1>;
69 ranges; 69 ranges;
70 70
71 pdma: pdma@ffe01000 { 71 pdma: pdma@ffe01000 {
72 compatible = " 72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01 73 reg = <0xffe01000 0x1000>;
74 interrupts = < 74 interrupts = <0 104 4>,
75 < 75 <0 105 4>,
76 < 76 <0 106 4>,
77 < 77 <0 107 4>,
78 < 78 <0 108 4>,
79 < 79 <0 109 4>,
80 < 80 <0 110 4>,
81 < 81 <0 111 4>;
82 #dma-cells = < 82 #dma-cells = <1>;
83 clocks = <&l4_ 83 clocks = <&l4_main_clk>;
84 clock-names = 84 clock-names = "apb_pclk";
85 resets = <&rst 85 resets = <&rst DMA_RESET>;
86 reset-names = 86 reset-names = "dma";
87 }; 87 };
88 }; 88 };
89 89
90 base_fpga_region { 90 base_fpga_region {
91 compatible = "fpga-reg 91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0> 92 fpga-mgr = <&fpgamgr0>;
93 93
94 #address-cells = <0x1> 94 #address-cells = <0x1>;
95 #size-cells = <0x1>; 95 #size-cells = <0x1>;
96 }; 96 };
97 97
98 can0: can@ffc00000 { 98 can0: can@ffc00000 {
99 compatible = "bosch,d_ 99 compatible = "bosch,d_can";
100 reg = <0xffc00000 0x10 100 reg = <0xffc00000 0x1000>;
101 interrupts = <0 131 4> 101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
102 clocks = <&can0_clk>; 102 clocks = <&can0_clk>;
103 resets = <&rst CAN0_RE 103 resets = <&rst CAN0_RESET>;
104 status = "disabled"; 104 status = "disabled";
105 }; 105 };
106 106
107 can1: can@ffc01000 { 107 can1: can@ffc01000 {
108 compatible = "bosch,d_ 108 compatible = "bosch,d_can";
109 reg = <0xffc01000 0x10 109 reg = <0xffc01000 0x1000>;
110 interrupts = <0 135 4> 110 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
111 clocks = <&can1_clk>; 111 clocks = <&can1_clk>;
112 resets = <&rst CAN1_RE 112 resets = <&rst CAN1_RESET>;
113 status = "disabled"; 113 status = "disabled";
114 }; 114 };
115 115
116 clkmgr@ffd04000 { 116 clkmgr@ffd04000 {
117 compatible = " 117 compatible = "altr,clk-mgr";
118 reg = <0xffd04 118 reg = <0xffd04000 0x1000>;
119 119
120 clocks { 120 clocks {
121 #addre 121 #address-cells = <1>;
122 #size- 122 #size-cells = <0>;
123 123
124 osc1: 124 osc1: osc1 {
125 125 #clock-cells = <0>;
126 126 compatible = "fixed-clock";
127 }; 127 };
128 128
129 osc2: 129 osc2: osc2 {
130 130 #clock-cells = <0>;
131 131 compatible = "fixed-clock";
132 }; 132 };
133 133
134 f2s_pe 134 f2s_periph_ref_clk: f2s_periph_ref_clk {
135 135 #clock-cells = <0>;
136 136 compatible = "fixed-clock";
137 }; 137 };
138 138
139 f2s_sd 139 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
140 140 #clock-cells = <0>;
141 141 compatible = "fixed-clock";
142 }; 142 };
143 143
144 main_p 144 main_pll: main_pll@40 {
145 145 #address-cells = <1>;
146 146 #size-cells = <0>;
147 147 #clock-cells = <0>;
148 148 compatible = "altr,socfpga-pll-clock";
149 149 clocks = <&osc1>;
150 150 reg = <0x40>;
151 151
152 152 mpuclk: mpuclk@48 {
153 153 #clock-cells = <0>;
154 154 compatible = "altr,socfpga-perip-clk";
155 155 clocks = <&main_pll>;
156 156 div-reg = <0xe0 0 9>;
157 157 reg = <0x48>;
158 158 };
159 159
160 160 mainclk: mainclk@4c {
161 161 #clock-cells = <0>;
162 162 compatible = "altr,socfpga-perip-clk";
163 163 clocks = <&main_pll>;
164 164 div-reg = <0xe4 0 9>;
165 165 reg = <0x4C>;
166 166 };
167 167
168 168 dbg_base_clk: dbg_base_clk@50 {
169 169 #clock-cells = <0>;
170 170 compatible = "altr,socfpga-perip-clk";
171 171 clocks = <&main_pll>, <&osc1>;
172 172 div-reg = <0xe8 0 9>;
173 173 reg = <0x50>;
174 174 };
175 175
176 176 main_qspi_clk: main_qspi_clk@54 {
177 177 #clock-cells = <0>;
178 178 compatible = "altr,socfpga-perip-clk";
179 179 clocks = <&main_pll>;
180 180 reg = <0x54>;
181 181 };
182 182
183 183 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
184 184 #clock-cells = <0>;
185 185 compatible = "altr,socfpga-perip-clk";
186 186 clocks = <&main_pll>;
187 187 reg = <0x58>;
188 188 };
189 189
190 190 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
191 191 #clock-cells = <0>;
192 192 compatible = "altr,socfpga-perip-clk";
193 193 clocks = <&main_pll>;
194 194 reg = <0x5C>;
195 195 };
196 }; 196 };
197 197
198 periph 198 periph_pll: periph_pll@80 {
199 199 #address-cells = <1>;
200 200 #size-cells = <0>;
201 201 #clock-cells = <0>;
202 202 compatible = "altr,socfpga-pll-clock";
203 203 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
204 204 reg = <0x80>;
205 205
206 206 emac0_clk: emac0_clk@88 {
207 207 #clock-cells = <0>;
208 208 compatible = "altr,socfpga-perip-clk";
209 209 clocks = <&periph_pll>;
210 210 reg = <0x88>;
211 211 };
212 212
213 213 emac1_clk: emac1_clk@8c {
214 214 #clock-cells = <0>;
215 215 compatible = "altr,socfpga-perip-clk";
216 216 clocks = <&periph_pll>;
217 217 reg = <0x8C>;
218 218 };
219 219
220 220 per_qspi_clk: per_qsi_clk@90 {
221 221 #clock-cells = <0>;
222 222 compatible = "altr,socfpga-perip-clk";
223 223 clocks = <&periph_pll>;
224 224 reg = <0x90>;
225 225 };
226 226
227 227 per_nand_mmc_clk: per_nand_mmc_clk@94 {
228 228 #clock-cells = <0>;
229 229 compatible = "altr,socfpga-perip-clk";
230 230 clocks = <&periph_pll>;
231 231 reg = <0x94>;
232 232 };
233 233
234 234 per_base_clk: per_base_clk@98 {
235 235 #clock-cells = <0>;
236 236 compatible = "altr,socfpga-perip-clk";
237 237 clocks = <&periph_pll>;
238 238 reg = <0x98>;
239 239 };
240 240
241 241 h2f_usr1_clk: h2f_usr1_clk@9c {
242 242 #clock-cells = <0>;
243 243 compatible = "altr,socfpga-perip-clk";
244 244 clocks = <&periph_pll>;
245 245 reg = <0x9C>;
246 246 };
247 }; 247 };
248 248
249 sdram_ 249 sdram_pll: sdram_pll@c0 {
250 250 #address-cells = <1>;
251 251 #size-cells = <0>;
252 252 #clock-cells = <0>;
253 253 compatible = "altr,socfpga-pll-clock";
254 254 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
255 255 reg = <0xC0>;
256 256
257 257 ddr_dqs_clk: ddr_dqs_clk@c8 {
258 258 #clock-cells = <0>;
259 259 compatible = "altr,socfpga-perip-clk";
260 260 clocks = <&sdram_pll>;
261 261 reg = <0xC8>;
262 262 };
263 263
264 264 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
265 265 #clock-cells = <0>;
266 266 compatible = "altr,socfpga-perip-clk";
267 267 clocks = <&sdram_pll>;
268 268 reg = <0xCC>;
269 269 };
270 270
271 271 ddr_dq_clk: ddr_dq_clk@d0 {
272 272 #clock-cells = <0>;
273 273 compatible = "altr,socfpga-perip-clk";
274 274 clocks = <&sdram_pll>;
275 275 reg = <0xD0>;
276 276 };
277 277
278 278 h2f_usr2_clk: h2f_usr2_clk@d4 {
279 279 #clock-cells = <0>;
280 280 compatible = "altr,socfpga-perip-clk";
281 281 clocks = <&sdram_pll>;
282 282 reg = <0xD4>;
283 283 };
284 }; 284 };
285 285
286 mpu_pe 286 mpu_periph_clk: mpu_periph_clk {
287 287 #clock-cells = <0>;
288 288 compatible = "altr,socfpga-perip-clk";
289 289 clocks = <&mpuclk>;
290 290 fixed-divider = <4>;
291 }; 291 };
292 292
293 mpu_l2 293 mpu_l2_ram_clk: mpu_l2_ram_clk {
294 294 #clock-cells = <0>;
295 295 compatible = "altr,socfpga-perip-clk";
296 296 clocks = <&mpuclk>;
297 297 fixed-divider = <2>;
298 }; 298 };
299 299
300 l4_mai 300 l4_main_clk: l4_main_clk {
301 301 #clock-cells = <0>;
302 302 compatible = "altr,socfpga-gate-clk";
303 303 clocks = <&mainclk>;
304 304 clk-gate = <0x60 0>;
305 }; 305 };
306 306
307 l3_mai 307 l3_main_clk: l3_main_clk {
308 308 #clock-cells = <0>;
309 309 compatible = "altr,socfpga-perip-clk";
310 310 clocks = <&mainclk>;
311 311 fixed-divider = <1>;
312 }; 312 };
313 313
314 l3_mp_ 314 l3_mp_clk: l3_mp_clk {
315 315 #clock-cells = <0>;
316 316 compatible = "altr,socfpga-gate-clk";
317 317 clocks = <&mainclk>;
318 318 div-reg = <0x64 0 2>;
319 319 clk-gate = <0x60 1>;
320 }; 320 };
321 321
322 l3_sp_ 322 l3_sp_clk: l3_sp_clk {
323 323 #clock-cells = <0>;
324 324 compatible = "altr,socfpga-gate-clk";
325 325 clocks = <&l3_mp_clk>;
326 326 div-reg = <0x64 2 2>;
327 }; 327 };
328 328
329 l4_mp_ 329 l4_mp_clk: l4_mp_clk {
330 330 #clock-cells = <0>;
331 331 compatible = "altr,socfpga-gate-clk";
332 332 clocks = <&mainclk>, <&per_base_clk>;
333 333 div-reg = <0x64 4 3>;
334 334 clk-gate = <0x60 2>;
335 }; 335 };
336 336
337 l4_sp_ 337 l4_sp_clk: l4_sp_clk {
338 338 #clock-cells = <0>;
339 339 compatible = "altr,socfpga-gate-clk";
340 340 clocks = <&mainclk>, <&per_base_clk>;
341 341 div-reg = <0x64 7 3>;
342 342 clk-gate = <0x60 3>;
343 }; 343 };
344 344
345 dbg_at 345 dbg_at_clk: dbg_at_clk {
346 346 #clock-cells = <0>;
347 347 compatible = "altr,socfpga-gate-clk";
348 348 clocks = <&dbg_base_clk>;
349 349 div-reg = <0x68 0 2>;
350 350 clk-gate = <0x60 4>;
351 }; 351 };
352 352
353 dbg_cl 353 dbg_clk: dbg_clk {
354 354 #clock-cells = <0>;
355 355 compatible = "altr,socfpga-gate-clk";
356 356 clocks = <&dbg_at_clk>;
357 357 div-reg = <0x68 2 2>;
358 358 clk-gate = <0x60 5>;
359 }; 359 };
360 360
361 dbg_tr 361 dbg_trace_clk: dbg_trace_clk {
362 362 #clock-cells = <0>;
363 363 compatible = "altr,socfpga-gate-clk";
364 364 clocks = <&dbg_base_clk>;
365 365 div-reg = <0x6C 0 3>;
366 366 clk-gate = <0x60 6>;
367 }; 367 };
368 368
369 dbg_ti 369 dbg_timer_clk: dbg_timer_clk {
370 370 #clock-cells = <0>;
371 371 compatible = "altr,socfpga-gate-clk";
372 372 clocks = <&dbg_base_clk>;
373 373 clk-gate = <0x60 7>;
374 }; 374 };
375 375
376 cfg_cl 376 cfg_clk: cfg_clk {
377 377 #clock-cells = <0>;
378 378 compatible = "altr,socfpga-gate-clk";
379 379 clocks = <&cfg_h2f_usr0_clk>;
380 380 clk-gate = <0x60 8>;
381 }; 381 };
382 382
383 h2f_us 383 h2f_user0_clk: h2f_user0_clk {
384 384 #clock-cells = <0>;
385 385 compatible = "altr,socfpga-gate-clk";
386 386 clocks = <&cfg_h2f_usr0_clk>;
387 387 clk-gate = <0x60 9>;
388 }; 388 };
389 389
390 emac_0 390 emac_0_clk: emac_0_clk {
391 391 #clock-cells = <0>;
392 392 compatible = "altr,socfpga-gate-clk";
393 393 clocks = <&emac0_clk>;
394 394 clk-gate = <0xa0 0>;
395 }; 395 };
396 396
397 emac_1 397 emac_1_clk: emac_1_clk {
398 398 #clock-cells = <0>;
399 399 compatible = "altr,socfpga-gate-clk";
400 400 clocks = <&emac1_clk>;
401 401 clk-gate = <0xa0 1>;
402 }; 402 };
403 403
404 usb_mp 404 usb_mp_clk: usb_mp_clk {
405 405 #clock-cells = <0>;
406 406 compatible = "altr,socfpga-gate-clk";
407 407 clocks = <&per_base_clk>;
408 408 clk-gate = <0xa0 2>;
409 409 div-reg = <0xa4 0 3>;
410 }; 410 };
411 411
412 spi_m_ 412 spi_m_clk: spi_m_clk {
413 413 #clock-cells = <0>;
414 414 compatible = "altr,socfpga-gate-clk";
415 415 clocks = <&per_base_clk>;
416 416 clk-gate = <0xa0 3>;
417 417 div-reg = <0xa4 3 3>;
418 }; 418 };
419 419
420 can0_c 420 can0_clk: can0_clk {
421 421 #clock-cells = <0>;
422 422 compatible = "altr,socfpga-gate-clk";
423 423 clocks = <&per_base_clk>;
424 424 clk-gate = <0xa0 4>;
425 425 div-reg = <0xa4 6 3>;
426 }; 426 };
427 427
428 can1_c 428 can1_clk: can1_clk {
429 429 #clock-cells = <0>;
430 430 compatible = "altr,socfpga-gate-clk";
431 431 clocks = <&per_base_clk>;
432 432 clk-gate = <0xa0 5>;
433 433 div-reg = <0xa4 9 3>;
434 }; 434 };
435 435
436 gpio_d 436 gpio_db_clk: gpio_db_clk {
437 437 #clock-cells = <0>;
438 438 compatible = "altr,socfpga-gate-clk";
439 439 clocks = <&per_base_clk>;
440 440 clk-gate = <0xa0 6>;
441 441 div-reg = <0xa8 0 24>;
442 }; 442 };
443 443
444 h2f_us 444 h2f_user1_clk: h2f_user1_clk {
445 445 #clock-cells = <0>;
446 446 compatible = "altr,socfpga-gate-clk";
447 447 clocks = <&h2f_usr1_clk>;
448 448 clk-gate = <0xa0 7>;
449 }; 449 };
450 450
451 sdmmc_ 451 sdmmc_clk: sdmmc_clk {
452 452 #clock-cells = <0>;
453 453 compatible = "altr,socfpga-gate-clk";
454 454 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
455 455 clk-gate = <0xa0 8>;
456 }; 456 };
457 457
458 sdmmc_ 458 sdmmc_clk_divided: sdmmc_clk_divided {
459 459 #clock-cells = <0>;
460 460 compatible = "altr,socfpga-gate-clk";
461 461 clocks = <&sdmmc_clk>;
462 462 clk-gate = <0xa0 8>;
463 463 fixed-divider = <4>;
464 }; 464 };
465 465
466 nand_x 466 nand_x_clk: nand_x_clk {
467 467 #clock-cells = <0>;
468 468 compatible = "altr,socfpga-gate-clk";
469 469 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
470 470 clk-gate = <0xa0 9>;
471 }; 471 };
472 472
473 nand_e 473 nand_ecc_clk: nand_ecc_clk {
474 474 #clock-cells = <0>;
475 475 compatible = "altr,socfpga-gate-clk";
476 476 clocks = <&nand_x_clk>;
477 477 clk-gate = <0xa0 9>;
478 }; 478 };
479 479
480 nand_c 480 nand_clk: nand_clk {
481 481 #clock-cells = <0>;
482 482 compatible = "altr,socfpga-gate-clk";
483 483 clocks = <&nand_x_clk>;
484 484 clk-gate = <0xa0 10>;
485 485 fixed-divider = <4>;
486 }; 486 };
487 487
488 qspi_c 488 qspi_clk: qspi_clk {
489 489 #clock-cells = <0>;
490 490 compatible = "altr,socfpga-gate-clk";
491 491 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
492 492 clk-gate = <0xa0 11>;
493 }; 493 };
494 494
495 ddr_dq 495 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
496 496 #clock-cells = <0>;
497 497 compatible = "altr,socfpga-gate-clk";
498 498 clocks = <&ddr_dqs_clk>;
499 499 clk-gate = <0xd8 0>;
500 }; 500 };
501 501
502 ddr_2x 502 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
503 503 #clock-cells = <0>;
504 504 compatible = "altr,socfpga-gate-clk";
505 505 clocks = <&ddr_2x_dqs_clk>;
506 506 clk-gate = <0xd8 1>;
507 }; 507 };
508 508
509 ddr_dq 509 ddr_dq_clk_gate: ddr_dq_clk_gate {
510 510 #clock-cells = <0>;
511 511 compatible = "altr,socfpga-gate-clk";
512 512 clocks = <&ddr_dq_clk>;
513 513 clk-gate = <0xd8 2>;
514 }; 514 };
515 515
516 h2f_us 516 h2f_user2_clk: h2f_user2_clk {
517 517 #clock-cells = <0>;
518 518 compatible = "altr,socfpga-gate-clk";
519 519 clocks = <&h2f_usr2_clk>;
520 520 clk-gate = <0xd8 3>;
521 }; 521 };
522 522
523 }; 523 };
524 }; 524 };
525 525
526 fpga_bridge0: fpga_bridge@ff40 526 fpga_bridge0: fpga_bridge@ff400000 {
527 compatible = "altr,soc 527 compatible = "altr,socfpga-lwhps2fpga-bridge";
528 reg = <0xff400000 0x10 528 reg = <0xff400000 0x100000>;
529 resets = <&rst LWHPS2F 529 resets = <&rst LWHPS2FPGA_RESET>;
530 clocks = <&l4_main_clk 530 clocks = <&l4_main_clk>;
531 status = "disabled"; 531 status = "disabled";
532 }; 532 };
533 533
534 fpga_bridge1: fpga_bridge@ff50 534 fpga_bridge1: fpga_bridge@ff500000 {
535 compatible = "altr,soc 535 compatible = "altr,socfpga-hps2fpga-bridge";
536 reg = <0xff500000 0x10 536 reg = <0xff500000 0x10000>;
537 resets = <&rst HPS2FPG 537 resets = <&rst HPS2FPGA_RESET>;
538 clocks = <&l4_main_clk 538 clocks = <&l4_main_clk>;
539 status = "disabled"; 539 status = "disabled";
540 }; 540 };
541 541
542 fpga_bridge2: fpga-bridge@ff60 542 fpga_bridge2: fpga-bridge@ff600000 {
543 compatible = "altr,soc 543 compatible = "altr,socfpga-fpga2hps-bridge";
544 reg = <0xff600000 0x10 544 reg = <0xff600000 0x100000>;
545 resets = <&rst FPGA2HP 545 resets = <&rst FPGA2HPS_RESET>;
546 clocks = <&l4_main_clk 546 clocks = <&l4_main_clk>;
547 status = "disabled"; 547 status = "disabled";
548 }; 548 };
549 549
550 fpga_bridge3: fpga-bridge@ffc2 550 fpga_bridge3: fpga-bridge@ffc25080 {
551 compatible = "altr,soc 551 compatible = "altr,socfpga-fpga2sdram-bridge";
552 reg = <0xffc25080 0x4> 552 reg = <0xffc25080 0x4>;
553 status = "disabled"; 553 status = "disabled";
554 }; 554 };
555 555
556 fpgamgr0: fpgamgr@ff706000 { 556 fpgamgr0: fpgamgr@ff706000 {
557 compatible = "altr,soc 557 compatible = "altr,socfpga-fpga-mgr";
558 reg = <0xff706000 0x10 558 reg = <0xff706000 0x1000
559 0xffb90000 0x4> 559 0xffb90000 0x4>;
560 interrupts = <0 175 4> 560 interrupts = <0 175 4>;
561 }; 561 };
562 562
563 socfpga_axi_setup: stmmac-axi- 563 socfpga_axi_setup: stmmac-axi-config {
564 snps,wr_osr_lmt = <0xf 564 snps,wr_osr_lmt = <0xf>;
565 snps,rd_osr_lmt = <0xf 565 snps,rd_osr_lmt = <0xf>;
566 snps,blen = <0 0 0 0 1 566 snps,blen = <0 0 0 0 16 0 0>;
567 }; 567 };
568 568
569 gmac0: ethernet@ff700000 { 569 gmac0: ethernet@ff700000 {
570 compatible = "altr,soc 570 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
571 altr,sysmgr-syscon = < 571 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
572 reg = <0xff700000 0x20 572 reg = <0xff700000 0x2000>;
573 interrupts = <0 115 4> 573 interrupts = <0 115 4>;
574 interrupt-names = "mac 574 interrupt-names = "macirq";
575 mac-address = [00 00 0 575 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
576 clocks = <&emac_0_clk> 576 clocks = <&emac_0_clk>;
577 clock-names = "stmmace 577 clock-names = "stmmaceth";
578 resets = <&rst EMAC0_R 578 resets = <&rst EMAC0_RESET>;
579 reset-names = "stmmace 579 reset-names = "stmmaceth";
580 snps,multicast-filter- 580 snps,multicast-filter-bins = <256>;
581 snps,perfect-filter-en 581 snps,perfect-filter-entries = <128>;
582 tx-fifo-depth = <4096> 582 tx-fifo-depth = <4096>;
583 rx-fifo-depth = <4096> 583 rx-fifo-depth = <4096>;
584 snps,axi-config = <&so 584 snps,axi-config = <&socfpga_axi_setup>;
585 status = "disabled"; 585 status = "disabled";
586 }; 586 };
587 587
588 gmac1: ethernet@ff702000 { 588 gmac1: ethernet@ff702000 {
589 compatible = "altr,soc 589 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
590 altr,sysmgr-syscon = < 590 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
591 reg = <0xff702000 0x20 591 reg = <0xff702000 0x2000>;
592 interrupts = <0 120 4> 592 interrupts = <0 120 4>;
593 interrupt-names = "mac 593 interrupt-names = "macirq";
594 mac-address = [00 00 0 594 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
595 clocks = <&emac_1_clk> 595 clocks = <&emac_1_clk>;
596 clock-names = "stmmace 596 clock-names = "stmmaceth";
597 resets = <&rst EMAC1_R 597 resets = <&rst EMAC1_RESET>;
598 reset-names = "stmmace 598 reset-names = "stmmaceth";
599 snps,multicast-filter- 599 snps,multicast-filter-bins = <256>;
600 snps,perfect-filter-en 600 snps,perfect-filter-entries = <128>;
601 tx-fifo-depth = <4096> 601 tx-fifo-depth = <4096>;
602 rx-fifo-depth = <4096> 602 rx-fifo-depth = <4096>;
603 snps,axi-config = <&so 603 snps,axi-config = <&socfpga_axi_setup>;
604 status = "disabled"; 604 status = "disabled";
605 }; 605 };
606 606
607 gpio0: gpio@ff708000 { 607 gpio0: gpio@ff708000 {
608 #address-cells = <1>; 608 #address-cells = <1>;
609 #size-cells = <0>; 609 #size-cells = <0>;
610 compatible = "snps,dw- 610 compatible = "snps,dw-apb-gpio";
611 reg = <0xff708000 0x10 611 reg = <0xff708000 0x1000>;
612 clocks = <&l4_mp_clk>; 612 clocks = <&l4_mp_clk>;
613 resets = <&rst GPIO0_R 613 resets = <&rst GPIO0_RESET>;
614 status = "disabled"; 614 status = "disabled";
615 615
616 porta: gpio-controller 616 porta: gpio-controller@0 {
617 compatible = " 617 compatible = "snps,dw-apb-gpio-port";
618 gpio-controlle 618 gpio-controller;
619 #gpio-cells = 619 #gpio-cells = <2>;
620 snps,nr-gpios 620 snps,nr-gpios = <29>;
621 reg = <0>; 621 reg = <0>;
622 interrupt-cont 622 interrupt-controller;
623 #interrupt-cel 623 #interrupt-cells = <2>;
624 interrupts = < 624 interrupts = <0 164 4>;
625 }; 625 };
626 }; 626 };
627 627
628 gpio1: gpio@ff709000 { 628 gpio1: gpio@ff709000 {
629 #address-cells = <1>; 629 #address-cells = <1>;
630 #size-cells = <0>; 630 #size-cells = <0>;
631 compatible = "snps,dw- 631 compatible = "snps,dw-apb-gpio";
632 reg = <0xff709000 0x10 632 reg = <0xff709000 0x1000>;
633 clocks = <&l4_mp_clk>; 633 clocks = <&l4_mp_clk>;
634 resets = <&rst GPIO1_R 634 resets = <&rst GPIO1_RESET>;
635 status = "disabled"; 635 status = "disabled";
636 636
637 portb: gpio-controller 637 portb: gpio-controller@0 {
638 compatible = " 638 compatible = "snps,dw-apb-gpio-port";
639 gpio-controlle 639 gpio-controller;
640 #gpio-cells = 640 #gpio-cells = <2>;
641 snps,nr-gpios 641 snps,nr-gpios = <29>;
642 reg = <0>; 642 reg = <0>;
643 interrupt-cont 643 interrupt-controller;
644 #interrupt-cel 644 #interrupt-cells = <2>;
645 interrupts = < 645 interrupts = <0 165 4>;
646 }; 646 };
647 }; 647 };
648 648
649 gpio2: gpio@ff70a000 { 649 gpio2: gpio@ff70a000 {
650 #address-cells = <1>; 650 #address-cells = <1>;
651 #size-cells = <0>; 651 #size-cells = <0>;
652 compatible = "snps,dw- 652 compatible = "snps,dw-apb-gpio";
653 reg = <0xff70a000 0x10 653 reg = <0xff70a000 0x1000>;
654 clocks = <&l4_mp_clk>; 654 clocks = <&l4_mp_clk>;
655 resets = <&rst GPIO2_R 655 resets = <&rst GPIO2_RESET>;
656 status = "disabled"; 656 status = "disabled";
657 657
658 portc: gpio-controller 658 portc: gpio-controller@0 {
659 compatible = " 659 compatible = "snps,dw-apb-gpio-port";
660 gpio-controlle 660 gpio-controller;
661 #gpio-cells = 661 #gpio-cells = <2>;
662 snps,nr-gpios 662 snps,nr-gpios = <27>;
663 reg = <0>; 663 reg = <0>;
664 interrupt-cont 664 interrupt-controller;
665 #interrupt-cel 665 #interrupt-cells = <2>;
666 interrupts = < 666 interrupts = <0 166 4>;
667 }; 667 };
668 }; 668 };
669 669
670 i2c0: i2c@ffc04000 { 670 i2c0: i2c@ffc04000 {
671 #address-cells = <1>; 671 #address-cells = <1>;
672 #size-cells = <0>; 672 #size-cells = <0>;
673 compatible = "snps,des 673 compatible = "snps,designware-i2c";
674 reg = <0xffc04000 0x10 674 reg = <0xffc04000 0x1000>;
675 resets = <&rst I2C0_RE 675 resets = <&rst I2C0_RESET>;
676 clocks = <&l4_sp_clk>; 676 clocks = <&l4_sp_clk>;
677 interrupts = <0 158 0x 677 interrupts = <0 158 0x4>;
678 status = "disabled"; 678 status = "disabled";
679 }; 679 };
680 680
681 i2c1: i2c@ffc05000 { 681 i2c1: i2c@ffc05000 {
682 #address-cells = <1>; 682 #address-cells = <1>;
683 #size-cells = <0>; 683 #size-cells = <0>;
684 compatible = "snps,des 684 compatible = "snps,designware-i2c";
685 reg = <0xffc05000 0x10 685 reg = <0xffc05000 0x1000>;
686 resets = <&rst I2C1_RE 686 resets = <&rst I2C1_RESET>;
687 clocks = <&l4_sp_clk>; 687 clocks = <&l4_sp_clk>;
688 interrupts = <0 159 0x 688 interrupts = <0 159 0x4>;
689 status = "disabled"; 689 status = "disabled";
690 }; 690 };
691 691
692 i2c2: i2c@ffc06000 { 692 i2c2: i2c@ffc06000 {
693 #address-cells = <1>; 693 #address-cells = <1>;
694 #size-cells = <0>; 694 #size-cells = <0>;
695 compatible = "snps,des 695 compatible = "snps,designware-i2c";
696 reg = <0xffc06000 0x10 696 reg = <0xffc06000 0x1000>;
697 resets = <&rst I2C2_RE 697 resets = <&rst I2C2_RESET>;
698 clocks = <&l4_sp_clk>; 698 clocks = <&l4_sp_clk>;
699 interrupts = <0 160 0x 699 interrupts = <0 160 0x4>;
700 status = "disabled"; 700 status = "disabled";
701 }; 701 };
702 702
703 i2c3: i2c@ffc07000 { 703 i2c3: i2c@ffc07000 {
704 #address-cells = <1>; 704 #address-cells = <1>;
705 #size-cells = <0>; 705 #size-cells = <0>;
706 compatible = "snps,des 706 compatible = "snps,designware-i2c";
707 reg = <0xffc07000 0x10 707 reg = <0xffc07000 0x1000>;
708 resets = <&rst I2C3_RE 708 resets = <&rst I2C3_RESET>;
709 clocks = <&l4_sp_clk>; 709 clocks = <&l4_sp_clk>;
710 interrupts = <0 161 0x 710 interrupts = <0 161 0x4>;
711 status = "disabled"; 711 status = "disabled";
712 }; 712 };
713 713
714 eccmgr: eccmgr { 714 eccmgr: eccmgr {
715 compatible = "altr,soc 715 compatible = "altr,socfpga-ecc-manager";
716 #address-cells = <1>; 716 #address-cells = <1>;
717 #size-cells = <1>; 717 #size-cells = <1>;
718 ranges; 718 ranges;
719 719
720 l2-ecc@ffd08140 { 720 l2-ecc@ffd08140 {
721 compatible = " 721 compatible = "altr,socfpga-l2-ecc";
722 reg = <0xffd08 722 reg = <0xffd08140 0x4>;
723 interrupts = < 723 interrupts = <0 36 1>, <0 37 1>;
724 }; 724 };
725 725
726 ocram-ecc@ffd08144 { 726 ocram-ecc@ffd08144 {
727 compatible = " 727 compatible = "altr,socfpga-ocram-ecc";
728 reg = <0xffd08 728 reg = <0xffd08144 0x4>;
729 iram = <&ocram 729 iram = <&ocram>;
730 interrupts = < 730 interrupts = <0 178 1>, <0 179 1>;
731 }; 731 };
732 }; 732 };
733 733
734 L2: cache-controller@fffef000 734 L2: cache-controller@fffef000 {
735 compatible = "arm,pl31 735 compatible = "arm,pl310-cache";
736 reg = <0xfffef000 0x10 736 reg = <0xfffef000 0x1000>;
737 interrupts = <0 38 0x0 737 interrupts = <0 38 0x04>;
738 cache-unified; 738 cache-unified;
739 cache-level = <2>; 739 cache-level = <2>;
740 arm,tag-latency = <1 1 740 arm,tag-latency = <1 1 1>;
741 arm,data-latency = <2 741 arm,data-latency = <2 1 1>;
742 prefetch-data = <1>; 742 prefetch-data = <1>;
743 prefetch-instr = <1>; 743 prefetch-instr = <1>;
744 arm,shared-override; 744 arm,shared-override;
745 arm,double-linefill = 745 arm,double-linefill = <1>;
746 arm,double-linefill-in 746 arm,double-linefill-incr = <0>;
747 arm,double-linefill-wr 747 arm,double-linefill-wrap = <1>;
748 arm,prefetch-drop = <0 748 arm,prefetch-drop = <0>;
749 arm,prefetch-offset = 749 arm,prefetch-offset = <7>;
750 }; 750 };
751 751
752 l3regs@ff800000 { 752 l3regs@ff800000 {
753 compatible = "altr,l3r 753 compatible = "altr,l3regs", "syscon";
754 reg = <0xff800000 0x10 754 reg = <0xff800000 0x1000>;
755 }; 755 };
756 756
757 mmc: mmc@ff704000 { 757 mmc: mmc@ff704000 {
758 compatible = "altr,soc 758 compatible = "altr,socfpga-dw-mshc";
759 reg = <0xff704000 0x10 759 reg = <0xff704000 0x1000>;
760 interrupts = <0 139 4> 760 interrupts = <0 139 4>;
761 fifo-depth = <0x400>; 761 fifo-depth = <0x400>;
762 #address-cells = <1>; 762 #address-cells = <1>;
763 #size-cells = <0>; 763 #size-cells = <0>;
764 clocks = <&l4_mp_clk>, 764 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
765 clock-names = "biu", " 765 clock-names = "biu", "ciu";
766 resets = <&rst SDMMC_R 766 resets = <&rst SDMMC_RESET>;
767 altr,sysmgr-syscon = < 767 altr,sysmgr-syscon = <&sysmgr 0x108 3>;
768 status = "disabled"; 768 status = "disabled";
769 }; 769 };
770 770
771 nand0: nand-controller@ff90000 771 nand0: nand-controller@ff900000 {
772 #address-cells = <0x1> 772 #address-cells = <0x1>;
773 #size-cells = <0x0>; 773 #size-cells = <0x0>;
774 compatible = "altr,soc 774 compatible = "altr,socfpga-denali-nand";
775 reg = <0xff900000 0x10 775 reg = <0xff900000 0x100000>,
776 <0xffb80000 0x10 776 <0xffb80000 0x10000>;
777 reg-names = "nand_data 777 reg-names = "nand_data", "denali_reg";
778 interrupts = <0x0 0x90 778 interrupts = <0x0 0x90 0x4>;
779 clocks = <&nand_clk>, 779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
780 clock-names = "nand", 780 clock-names = "nand", "nand_x", "ecc";
781 resets = <&rst NAND_RE 781 resets = <&rst NAND_RESET>;
782 status = "disabled"; 782 status = "disabled";
783 }; 783 };
784 784
785 ocram: sram@ffff0000 { 785 ocram: sram@ffff0000 {
786 compatible = "mmio-sra 786 compatible = "mmio-sram";
787 reg = <0xffff0000 0x10 787 reg = <0xffff0000 0x10000>;
788 }; 788 };
789 789
790 qspi: spi@ff705000 { 790 qspi: spi@ff705000 {
791 compatible = "intel,so 791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
792 #address-cells = <1>; 792 #address-cells = <1>;
793 #size-cells = <0>; 793 #size-cells = <0>;
794 reg = <0xff705000 0x10 794 reg = <0xff705000 0x1000>,
795 <0xffa00000 0x10 795 <0xffa00000 0x1000>;
796 interrupts = <0 151 4> 796 interrupts = <0 151 4>;
797 cdns,fifo-depth = <128 797 cdns,fifo-depth = <128>;
798 cdns,fifo-width = <4>; 798 cdns,fifo-width = <4>;
799 cdns,trigger-address = 799 cdns,trigger-address = <0x00000000>;
800 clocks = <&qspi_clk>; 800 clocks = <&qspi_clk>;
801 resets = <&rst QSPI_RE 801 resets = <&rst QSPI_RESET>;
802 status = "disabled"; 802 status = "disabled";
803 }; 803 };
804 804
805 rst: rstmgr@ffd05000 { 805 rst: rstmgr@ffd05000 {
806 #reset-cells = <1>; 806 #reset-cells = <1>;
807 compatible = "altr,rst 807 compatible = "altr,rst-mgr";
808 reg = <0xffd05000 0x10 808 reg = <0xffd05000 0x1000>;
809 altr,modrst-offset = < 809 altr,modrst-offset = <0x10>;
810 }; 810 };
811 811
812 scu: snoop-control-unit@fffec0 812 scu: snoop-control-unit@fffec000 {
813 compatible = "arm,cort 813 compatible = "arm,cortex-a9-scu";
814 reg = <0xfffec000 0x10 814 reg = <0xfffec000 0x100>;
815 }; 815 };
816 816
817 sdr: sdr@ffc25000 { 817 sdr: sdr@ffc25000 {
818 compatible = "altr,sdr 818 compatible = "altr,sdr-ctl", "syscon";
819 reg = <0xffc25000 0x10 819 reg = <0xffc25000 0x1000>;
820 resets = <&rst SDR_RES 820 resets = <&rst SDR_RESET>;
821 }; 821 };
822 822
823 sdramedac { 823 sdramedac {
824 compatible = "altr,sdr 824 compatible = "altr,sdram-edac";
825 altr,sdr-syscon = <&sd 825 altr,sdr-syscon = <&sdr>;
826 interrupts = <0 39 4>; 826 interrupts = <0 39 4>;
827 }; 827 };
828 828
829 spi0: spi@fff00000 { 829 spi0: spi@fff00000 {
830 compatible = "snps,dw- 830 compatible = "snps,dw-apb-ssi";
831 #address-cells = <1>; 831 #address-cells = <1>;
832 #size-cells = <0>; 832 #size-cells = <0>;
833 reg = <0xfff00000 0x10 833 reg = <0xfff00000 0x1000>;
834 interrupts = <0 154 4> 834 interrupts = <0 154 4>;
835 num-cs = <4>; 835 num-cs = <4>;
836 clocks = <&spi_m_clk>; 836 clocks = <&spi_m_clk>;
837 resets = <&rst SPIM0_R 837 resets = <&rst SPIM0_RESET>;
838 reset-names = "spi"; 838 reset-names = "spi";
839 status = "disabled"; 839 status = "disabled";
840 }; 840 };
841 841
842 spi1: spi@fff01000 { 842 spi1: spi@fff01000 {
843 compatible = "snps,dw- 843 compatible = "snps,dw-apb-ssi";
844 #address-cells = <1>; 844 #address-cells = <1>;
845 #size-cells = <0>; 845 #size-cells = <0>;
846 reg = <0xfff01000 0x10 846 reg = <0xfff01000 0x1000>;
847 interrupts = <0 155 4> 847 interrupts = <0 155 4>;
848 num-cs = <4>; 848 num-cs = <4>;
849 clocks = <&spi_m_clk>; 849 clocks = <&spi_m_clk>;
850 resets = <&rst SPIM1_R 850 resets = <&rst SPIM1_RESET>;
851 reset-names = "spi"; 851 reset-names = "spi";
852 status = "disabled"; 852 status = "disabled";
853 }; 853 };
854 854
855 sysmgr: sysmgr@ffd08000 { 855 sysmgr: sysmgr@ffd08000 {
856 compatible = "altr,sys 856 compatible = "altr,sys-mgr", "syscon";
857 reg = <0xffd08000 0x40 857 reg = <0xffd08000 0x4000>;
858 }; 858 };
859 859
860 /* Local timer */ 860 /* Local timer */
861 timer@fffec600 { 861 timer@fffec600 {
862 compatible = "arm,cort 862 compatible = "arm,cortex-a9-twd-timer";
863 reg = <0xfffec600 0x10 863 reg = <0xfffec600 0x100>;
864 interrupts = <1 13 0xf 864 interrupts = <1 13 0xf01>;
865 clocks = <&mpu_periph_ 865 clocks = <&mpu_periph_clk>;
866 }; 866 };
867 867
868 timer0: timer0@ffc08000 { 868 timer0: timer0@ffc08000 {
869 compatible = "snps,dw- 869 compatible = "snps,dw-apb-timer";
870 interrupts = <0 167 4> 870 interrupts = <0 167 4>;
871 reg = <0xffc08000 0x10 871 reg = <0xffc08000 0x1000>;
872 clocks = <&l4_sp_clk>; 872 clocks = <&l4_sp_clk>;
873 clock-names = "timer"; 873 clock-names = "timer";
874 resets = <&rst SPTIMER 874 resets = <&rst SPTIMER0_RESET>;
875 reset-names = "timer"; 875 reset-names = "timer";
876 }; 876 };
877 877
878 timer1: timer1@ffc09000 { 878 timer1: timer1@ffc09000 {
879 compatible = "snps,dw- 879 compatible = "snps,dw-apb-timer";
880 interrupts = <0 168 4> 880 interrupts = <0 168 4>;
881 reg = <0xffc09000 0x10 881 reg = <0xffc09000 0x1000>;
882 clocks = <&l4_sp_clk>; 882 clocks = <&l4_sp_clk>;
883 clock-names = "timer"; 883 clock-names = "timer";
884 resets = <&rst SPTIMER 884 resets = <&rst SPTIMER1_RESET>;
885 reset-names = "timer"; 885 reset-names = "timer";
886 }; 886 };
887 887
888 timer2: timer2@ffd00000 { 888 timer2: timer2@ffd00000 {
889 compatible = "snps,dw- 889 compatible = "snps,dw-apb-timer";
890 interrupts = <0 169 4> 890 interrupts = <0 169 4>;
891 reg = <0xffd00000 0x10 891 reg = <0xffd00000 0x1000>;
892 clocks = <&osc1>; 892 clocks = <&osc1>;
893 clock-names = "timer"; 893 clock-names = "timer";
894 resets = <&rst OSC1TIM 894 resets = <&rst OSC1TIMER0_RESET>;
895 reset-names = "timer"; 895 reset-names = "timer";
896 }; 896 };
897 897
898 timer3: timer3@ffd01000 { 898 timer3: timer3@ffd01000 {
899 compatible = "snps,dw- 899 compatible = "snps,dw-apb-timer";
900 interrupts = <0 170 4> 900 interrupts = <0 170 4>;
901 reg = <0xffd01000 0x10 901 reg = <0xffd01000 0x1000>;
902 clocks = <&osc1>; 902 clocks = <&osc1>;
903 clock-names = "timer"; 903 clock-names = "timer";
904 resets = <&rst OSC1TIM 904 resets = <&rst OSC1TIMER1_RESET>;
905 reset-names = "timer"; 905 reset-names = "timer";
906 }; 906 };
907 907
908 uart0: serial@ffc02000 { 908 uart0: serial@ffc02000 {
909 compatible = "snps,dw- 909 compatible = "snps,dw-apb-uart";
910 reg = <0xffc02000 0x10 910 reg = <0xffc02000 0x1000>;
911 interrupts = <0 162 4> 911 interrupts = <0 162 4>;
912 reg-shift = <2>; 912 reg-shift = <2>;
913 reg-io-width = <4>; 913 reg-io-width = <4>;
914 clocks = <&l4_sp_clk>; 914 clocks = <&l4_sp_clk>;
915 dmas = <&pdma 28>, 915 dmas = <&pdma 28>,
916 <&pdma 29>; 916 <&pdma 29>;
917 dma-names = "tx", "rx" 917 dma-names = "tx", "rx";
918 resets = <&rst UART0_R 918 resets = <&rst UART0_RESET>;
919 }; 919 };
920 920
921 uart1: serial@ffc03000 { 921 uart1: serial@ffc03000 {
922 compatible = "snps,dw- 922 compatible = "snps,dw-apb-uart";
923 reg = <0xffc03000 0x10 923 reg = <0xffc03000 0x1000>;
924 interrupts = <0 163 4> 924 interrupts = <0 163 4>;
925 reg-shift = <2>; 925 reg-shift = <2>;
926 reg-io-width = <4>; 926 reg-io-width = <4>;
927 clocks = <&l4_sp_clk>; 927 clocks = <&l4_sp_clk>;
928 dmas = <&pdma 30>, 928 dmas = <&pdma 30>,
929 <&pdma 31>; 929 <&pdma 31>;
930 dma-names = "tx", "rx" 930 dma-names = "tx", "rx";
931 resets = <&rst UART1_R 931 resets = <&rst UART1_RESET>;
932 }; 932 };
933 933
934 usbphy0: usbphy { 934 usbphy0: usbphy {
935 #phy-cells = <0>; 935 #phy-cells = <0>;
936 compatible = "usb-nop- 936 compatible = "usb-nop-xceiv";
937 status = "okay"; 937 status = "okay";
938 }; 938 };
939 939
940 usb0: usb@ffb00000 { 940 usb0: usb@ffb00000 {
941 compatible = "snps,dwc 941 compatible = "snps,dwc2";
942 reg = <0xffb00000 0xff 942 reg = <0xffb00000 0xffff>;
943 interrupts = <0 125 4> 943 interrupts = <0 125 4>;
944 clocks = <&usb_mp_clk> 944 clocks = <&usb_mp_clk>;
945 clock-names = "otg"; 945 clock-names = "otg";
946 resets = <&rst USB0_RE 946 resets = <&rst USB0_RESET>;
947 reset-names = "dwc2"; 947 reset-names = "dwc2";
948 phys = <&usbphy0>; 948 phys = <&usbphy0>;
949 phy-names = "usb2-phy" 949 phy-names = "usb2-phy";
950 status = "disabled"; 950 status = "disabled";
951 }; 951 };
952 952
953 usb1: usb@ffb40000 { 953 usb1: usb@ffb40000 {
954 compatible = "snps,dwc 954 compatible = "snps,dwc2";
955 reg = <0xffb40000 0xff 955 reg = <0xffb40000 0xffff>;
956 interrupts = <0 128 4> 956 interrupts = <0 128 4>;
957 clocks = <&usb_mp_clk> 957 clocks = <&usb_mp_clk>;
958 clock-names = "otg"; 958 clock-names = "otg";
959 resets = <&rst USB1_RE 959 resets = <&rst USB1_RESET>;
960 reset-names = "dwc2"; 960 reset-names = "dwc2";
961 phys = <&usbphy0>; 961 phys = <&usbphy0>;
962 phy-names = "usb2-phy" 962 phy-names = "usb2-phy";
963 status = "disabled"; 963 status = "disabled";
964 }; 964 };
965 965
966 watchdog0: watchdog@ffd02000 { 966 watchdog0: watchdog@ffd02000 {
967 compatible = "snps,dw- 967 compatible = "snps,dw-wdt";
968 reg = <0xffd02000 0x10 968 reg = <0xffd02000 0x1000>;
969 interrupts = <0 171 4> 969 interrupts = <0 171 4>;
970 clocks = <&osc1>; 970 clocks = <&osc1>;
971 resets = <&rst L4WD0_R 971 resets = <&rst L4WD0_RESET>;
972 status = "disabled"; 972 status = "disabled";
973 }; 973 };
974 974
975 watchdog1: watchdog@ffd03000 { 975 watchdog1: watchdog@ffd03000 {
976 compatible = "snps,dw- 976 compatible = "snps,dw-wdt";
977 reg = <0xffd03000 0x10 977 reg = <0xffd03000 0x1000>;
978 interrupts = <0 172 4> 978 interrupts = <0 172 4>;
979 clocks = <&osc1>; 979 clocks = <&osc1>;
980 resets = <&rst L4WD1_R 980 resets = <&rst L4WD1_RESET>;
981 status = "disabled"; 981 status = "disabled";
982 }; 982 };
983 }; 983 };
984 }; 984 };
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