1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for Marvell Armada 388 eva 3 * Device Tree file for Marvell Armada 388 evaluation board
4 * (DB-88F6820) 4 * (DB-88F6820)
5 * 5 *
6 * Copyright (C) 2014 Marvell 6 * Copyright (C) 2014 Marvell
7 * 7 *
8 * Thomas Petazzoni <thomas.petazzoni@free-elec 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "armada-388.dtsi" 12 #include "armada-388.dtsi"
13 13
14 / { 14 / {
15 model = "Marvell Armada 385 Developmen 15 model = "Marvell Armada 385 Development Board";
16 compatible = "marvell,a385-db", "marve 16 compatible = "marvell,a385-db", "marvell,armada388",
17 "marvell,armada385", "marvell, 17 "marvell,armada385", "marvell,armada380";
18 18
19 chosen { 19 chosen {
20 stdout-path = "serial0:115200n 20 stdout-path = "serial0:115200n8";
21 }; 21 };
22 22
23 memory { 23 memory {
24 device_type = "memory"; 24 device_type = "memory";
25 reg = <0x00000000 0x10000000>; 25 reg = <0x00000000 0x10000000>; /* 256 MB */
26 }; 26 };
27 27
28 soc { 28 soc {
29 ranges = <MBUS_ID(0xf0, 0x01) 29 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
30 MBUS_ID(0x01, 0x1d) 30 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
31 MBUS_ID(0x09, 0x19) 31 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
32 MBUS_ID(0x09, 0x15) 32 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
33 MBUS_ID(0x0c, 0x04) 33 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
34 34
35 internal-regs { 35 internal-regs {
36 i2c@11000 { 36 i2c@11000 {
37 status = "okay 37 status = "okay";
38 clock-frequenc 38 clock-frequency = <100000>;
39 audio_codec: a 39 audio_codec: audio-codec@4a {
40 #sound 40 #sound-dai-cells = <0>;
41 compat 41 compatible = "cirrus,cs42l51";
42 reg = 42 reg = <0x4a>;
43 }; 43 };
44 }; 44 };
45 45
46 i2c@11100 { 46 i2c@11100 {
47 status = "okay 47 status = "okay";
48 clock-frequenc 48 clock-frequency = <100000>;
49 }; 49 };
50 50
51 serial@12000 { 51 serial@12000 {
52 status = "okay 52 status = "okay";
53 }; 53 };
54 54
55 ethernet@30000 { 55 ethernet@30000 {
56 status = "okay 56 status = "okay";
57 phy = <&phy1>; 57 phy = <&phy1>;
58 phy-mode = "rg 58 phy-mode = "rgmii-id";
59 buffer-manager 59 buffer-manager = <&bm>;
60 bm,pool-long = 60 bm,pool-long = <2>;
61 bm,pool-short 61 bm,pool-short = <3>;
62 }; 62 };
63 63
64 usb@58000 { 64 usb@58000 {
65 status = "okay 65 status = "okay";
66 }; 66 };
67 67
68 ethernet@70000 { 68 ethernet@70000 {
69 status = "okay 69 status = "okay";
70 phy = <&phy0>; 70 phy = <&phy0>;
71 phy-mode = "rg 71 phy-mode = "rgmii-id";
72 buffer-manager 72 buffer-manager = <&bm>;
73 bm,pool-long = 73 bm,pool-long = <0>;
74 bm,pool-short 74 bm,pool-short = <1>;
75 }; 75 };
76 76
77 mdio@72004 { 77 mdio@72004 {
78 phy0: ethernet 78 phy0: ethernet-phy@0 {
79 reg = 79 reg = <0>;
80 }; 80 };
81 81
82 phy1: ethernet 82 phy1: ethernet-phy@1 {
83 reg = 83 reg = <1>;
84 }; 84 };
85 }; 85 };
86 86
87 sata@a8000 { 87 sata@a8000 {
88 status = "okay 88 status = "okay";
89 }; 89 };
90 90
91 sata@e0000 { 91 sata@e0000 {
92 status = "okay 92 status = "okay";
93 }; 93 };
94 94
95 bm@c8000 { 95 bm@c8000 {
96 status = "okay 96 status = "okay";
97 }; 97 };
98 98
99 sdhci@d8000 { 99 sdhci@d8000 {
100 broken-cd; 100 broken-cd;
101 wp-inverted; 101 wp-inverted;
102 bus-width = <8 102 bus-width = <8>;
103 status = "okay 103 status = "okay";
104 no-1-8-v; 104 no-1-8-v;
105 }; 105 };
106 106
107 audio-controller@e8000 107 audio-controller@e8000 {
108 pinctrl-0 = <& 108 pinctrl-0 = <&i2s_pins>;
109 pinctrl-names 109 pinctrl-names = "default";
110 status = "disa 110 status = "disabled";
111 }; 111 };
112 112
113 usb3@f0000 { 113 usb3@f0000 {
114 status = "okay 114 status = "okay";
115 }; 115 };
116 116
117 usb3@f8000 { 117 usb3@f8000 {
118 status = "okay 118 status = "okay";
119 }; 119 };
120 }; 120 };
121 121
122 bm-bppi { 122 bm-bppi {
123 status = "okay"; 123 status = "okay";
124 }; 124 };
125 125
126 pcie { 126 pcie {
127 status = "okay"; 127 status = "okay";
128 /* 128 /*
129 * The two PCIe units 129 * The two PCIe units are accessible through
130 * standard PCIe slots 130 * standard PCIe slots on the board.
131 */ 131 */
132 pcie@1,0 { 132 pcie@1,0 {
133 /* Port 0, Lan 133 /* Port 0, Lane 0 */
134 status = "okay 134 status = "okay";
135 }; 135 };
136 pcie@2,0 { 136 pcie@2,0 {
137 /* Port 1, Lan 137 /* Port 1, Lane 0 */
138 status = "okay 138 status = "okay";
139 }; 139 };
140 }; 140 };
141 }; 141 };
142 142
143 sound { 143 sound {
144 compatible = "simple-audio-car 144 compatible = "simple-audio-card";
145 simple-audio-card,name = "Arma 145 simple-audio-card,name = "Armada 385 DB Audio";
146 simple-audio-card,mclk-fs = <2 146 simple-audio-card,mclk-fs = <256>;
147 simple-audio-card,widgets = 147 simple-audio-card,widgets =
148 "Headphone", "Out Jack 148 "Headphone", "Out Jack",
149 "Line", "In Jack"; 149 "Line", "In Jack";
150 simple-audio-card,routing = 150 simple-audio-card,routing =
151 "Out Jack", "HPL", 151 "Out Jack", "HPL",
152 "Out Jack", "HPR", 152 "Out Jack", "HPR",
153 "AIN1L", "In Jack", 153 "AIN1L", "In Jack",
154 "AIN1R", "In Jack"; 154 "AIN1R", "In Jack";
155 status = "disabled"; 155 status = "disabled";
156 156
157 simple-audio-card,dai-link@0 { 157 simple-audio-card,dai-link@0 {
158 format = "i2s"; 158 format = "i2s";
159 cpu { 159 cpu {
160 sound-dai = <& 160 sound-dai = <&audio_controller 0>;
161 }; 161 };
162 162
163 codec { 163 codec {
164 sound-dai = <& 164 sound-dai = <&audio_codec>;
165 }; 165 };
166 }; 166 };
167 167
168 simple-audio-card,dai-link@1 { 168 simple-audio-card,dai-link@1 {
169 format = "i2s"; 169 format = "i2s";
170 cpu { 170 cpu {
171 sound-dai = <& 171 sound-dai = <&audio_controller 1>;
172 }; 172 };
173 173
174 codec { 174 codec {
175 sound-dai = <& 175 sound-dai = <&spdif_out>;
176 }; 176 };
177 }; 177 };
178 178
179 simple-audio-card,dai-link@2 { 179 simple-audio-card,dai-link@2 {
180 format = "i2s"; 180 format = "i2s";
181 cpu { 181 cpu {
182 sound-dai = <& 182 sound-dai = <&audio_controller 1>;
183 }; 183 };
184 184
185 codec { 185 codec {
186 sound-dai = <& 186 sound-dai = <&spdif_in>;
187 }; 187 };
188 }; 188 };
189 }; 189 };
190 190
191 spdif_out: spdif-out { 191 spdif_out: spdif-out {
192 #sound-dai-cells = <0>; 192 #sound-dai-cells = <0>;
193 compatible = "linux,spdif-dit" 193 compatible = "linux,spdif-dit";
194 }; 194 };
195 195
196 spdif_in: spdif-in { 196 spdif_in: spdif-in {
197 #sound-dai-cells = <0>; 197 #sound-dai-cells = <0>;
198 compatible = "linux,spdif-dir" 198 compatible = "linux,spdif-dir";
199 }; 199 };
200 }; 200 };
201 201
202 &spi0 { 202 &spi0 {
203 status = "okay"; 203 status = "okay";
204 204
205 flash@0 { 205 flash@0 {
206 #address-cells = <1>; 206 #address-cells = <1>;
207 #size-cells = <1>; 207 #size-cells = <1>;
208 compatible = "w25q32", "jedec, 208 compatible = "w25q32", "jedec,spi-nor";
209 reg = <0>; /* Chip select 0 */ 209 reg = <0>; /* Chip select 0 */
210 spi-max-frequency = <108000000 210 spi-max-frequency = <108000000>;
211 }; 211 };
212 }; 212 };
213 213
214 &nand_controller { 214 &nand_controller {
215 status = "okay"; 215 status = "okay";
216 216
217 nand@0 { 217 nand@0 {
218 reg = <0>; 218 reg = <0>;
219 label = "pxa3xx_nand-0"; 219 label = "pxa3xx_nand-0";
220 nand-rb = <0>; 220 nand-rb = <0>;
221 marvell,nand-keep-config; 221 marvell,nand-keep-config;
222 nand-on-flash-bbt; 222 nand-on-flash-bbt;
223 nand-ecc-strength = <4>; 223 nand-ecc-strength = <4>;
224 nand-ecc-step-size = <512>; 224 nand-ecc-step-size = <512>;
225 225
226 partitions { 226 partitions {
227 compatible = "fixed-pa 227 compatible = "fixed-partitions";
228 #address-cells = <1>; 228 #address-cells = <1>;
229 #size-cells = <1>; 229 #size-cells = <1>;
230 230
231 partition@0 { 231 partition@0 {
232 label = "U-Boo 232 label = "U-Boot";
233 reg = <0 0x800 233 reg = <0 0x800000>;
234 }; 234 };
235 partition@800000 { 235 partition@800000 {
236 label = "Linux 236 label = "Linux";
237 reg = <0x80000 237 reg = <0x800000 0x800000>;
238 }; 238 };
239 partition@1000000 { 239 partition@1000000 {
240 label = "Files 240 label = "Filesystem";
241 reg = <0x10000 241 reg = <0x1000000 0x3f000000>;
242 }; 242 };
243 }; 243 };
244 }; 244 };
245 }; 245 };
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