1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree file for Marvell Armada 388 Ref
4 * (RD-88F6820-AP)
5 *
6 * Copyright (C) 2014 Marvell
7 *
8 * Gregory CLEMENT <gregory.clement@free-electr
9 * Thomas Petazzoni <thomas.petazzoni@free-elec
10 */
11
12 /dts-v1/;
13 #include "armada-388.dtsi"
14
15 / {
16 model = "Marvell Armada 385 Reference
17 compatible = "marvell,a385-rd", "marve
18 "marvell,armada385","marvell,a
19
20 chosen {
21 stdout-path = "serial0:115200n
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x10000000>;
27 };
28
29 soc {
30 ranges = <MBUS_ID(0xf0, 0x01)
31 MBUS_ID(0x01, 0x1d)
32 MBUS_ID(0x09, 0x19)
33 MBUS_ID(0x09, 0x15)
34
35 internal-regs {
36 i2c@11000 {
37 status = "okay
38 clock-frequenc
39 };
40
41 sdhci@d8000 {
42 pinctrl-names
43 pinctrl-0 = <&
44 broken-cd;
45 no-1-8-v;
46 wp-inverted;
47 bus-width = <8
48 status = "okay
49 };
50
51 serial@12000 {
52 status = "okay
53 };
54
55 ethernet@30000 {
56 status = "okay
57 phy = <&phy0>;
58 phy-mode = "rg
59 };
60
61 ethernet@70000 {
62 status = "okay
63 phy = <&phy1>;
64 phy-mode = "rg
65 };
66
67
68 mdio@72004 {
69 phy0: ethernet
70 reg =
71 };
72
73 phy1: ethernet
74 reg =
75 };
76 };
77
78 usb3@f0000 {
79 status = "okay
80 };
81 };
82
83 pcie {
84 status = "okay";
85 /*
86 * One PCIe units is a
87 * standard PCIe slot
88 */
89 pcie@1,0 {
90 /* Port 0, Lan
91 status = "okay
92 };
93 };
94 };
95 };
96
97 &spi0 {
98 status = "okay";
99
100 flash@0 {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 compatible = "st,m25p128", "je
104 reg = <0>; /* Chip select 0 */
105 spi-max-frequency = <108000000
106 };
107 };
108
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