1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electr
9 * Thomas Petazzoni <thomas.petazzoni@free-elec
10 */
11
12 #include <dt-bindings/interrupt-controller/arm
13 #include <dt-bindings/interrupt-controller/irq
14
15 #define MBUS_ID(target,attributes) (((target)
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 model = "Marvell Armada 38x family SoC
22 compatible = "marvell,armada380";
23
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 };
30
31 pmu {
32 compatible = "arm,cortex-a9-pm
33 interrupts-extended = <&mpic 3
34 };
35
36 soc {
37 compatible = "marvell,armada38
38 #address-cells = <2>;
39 #size-cells = <1>;
40 controller = <&mbusc>;
41 interrupt-parent = <&gic>;
42 pcie-mem-aperture = <0xe000000
43 pcie-io-aperture = <0xe800000
44
45 bootrom {
46 compatible = "marvell,
47 reg = <MBUS_ID(0x01, 0
48 };
49
50 devbus_bootcs: devbus-bootcs {
51 compatible = "marvell,
52 reg = <MBUS_ID(0xf0, 0
53 ranges = <0 MBUS_ID(0x
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
59
60 devbus_cs0: devbus-cs0 {
61 compatible = "marvell,
62 reg = <MBUS_ID(0xf0, 0
63 ranges = <0 MBUS_ID(0x
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
69
70 devbus_cs1: devbus-cs1 {
71 compatible = "marvell,
72 reg = <MBUS_ID(0xf0, 0
73 ranges = <0 MBUS_ID(0x
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
79
80 devbus_cs2: devbus-cs2 {
81 compatible = "marvell,
82 reg = <MBUS_ID(0xf0, 0
83 ranges = <0 MBUS_ID(0x
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
89
90 devbus_cs3: devbus-cs3 {
91 compatible = "marvell,
92 reg = <MBUS_ID(0xf0, 0
93 ranges = <0 MBUS_ID(0x
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
99
100 internal-regs {
101 compatible = "simple-b
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0 MBUS_ID(0x
105
106 sdramc: sdramc@1400 {
107 compatible = "
108 reg = <0x1400
109 };
110
111 L2: cache-controller@8
112 compatible = "
113 reg = <0x8000
114 cache-unified;
115 cache-level =
116 arm,double-lin
117 arm,double-lin
118 arm,double-lin
119 prefetch-data
120 };
121
122 scu@c000 {
123 compatible = "
124 reg = <0xc000
125 };
126
127 timer@c200 {
128 compatible = "
129 reg = <0xc200
130 interrupts = <
131 clocks = <&cor
132 };
133
134 timer@c600 {
135 compatible = "
136 reg = <0xc600
137 interrupts = <
138 clocks = <&cor
139 };
140
141 gic: interrupt-control
142 compatible = "
143 #interrupt-cel
144 #size-cells =
145 interrupt-cont
146 reg = <0xd000
147 <0xc100
148 };
149
150 i2c0: i2c@11000 {
151 compatible = "
152 reg = <0x11000
153 #address-cells
154 #size-cells =
155 interrupts = <
156 clocks = <&cor
157 status = "disa
158 };
159
160 i2c1: i2c@11100 {
161 compatible = "
162 reg = <0x11100
163 #address-cells
164 #size-cells =
165 interrupts = <
166 clocks = <&cor
167 status = "disa
168 };
169
170 uart0: serial@12000 {
171 compatible = "
172 reg = <0x12000
173 reg-shift = <2
174 interrupts = <
175 reg-io-width =
176 clocks = <&cor
177 status = "disa
178 };
179
180 uart1: serial@12100 {
181 compatible = "
182 reg = <0x12100
183 reg-shift = <2
184 interrupts = <
185 reg-io-width =
186 clocks = <&cor
187 status = "disa
188 };
189
190 pinctrl: pinctrl@18000
191 reg = <0x18000
192
193 ge0_rgmii_pins
194 marvel
195
196
197
198 marvel
199 };
200
201 ge1_rgmii_pins
202 marvel
203
204
205
206 marvel
207 };
208
209 i2c0_pins: i2c
210 marvel
211 marvel
212 };
213
214 mdio_pins: mdi
215 marvel
216 marvel
217 };
218
219 ref_clk0_pins:
220 marvel
221 marvel
222 };
223
224 ref_clk1_pins:
225 marvel
226 marvel
227 };
228
229 spi0_pins: spi
230 marvel
231
232 marvel
233 };
234
235 spi1_pins: spi
236 marvel
237
238 marvel
239 };
240
241 nand_pins: nan
242 marvel
243
244
245
246
247 marvel
248 };
249
250 nand_rb: nand-
251 marvel
252 marvel
253 };
254
255 uart0_pins: ua
256 marvel
257 marvel
258 };
259
260 uart1_pins: ua
261 marvel
262 marvel
263 };
264
265 sdhci_pins: sd
266 marvel
267
268
269
270 marvel
271 };
272
273 sata0_pins: sa
274 marvel
275 marvel
276 };
277
278 sata1_pins: sa
279 marvel
280 marvel
281 };
282
283 sata2_pins: sa
284 marvel
285 marvel
286 };
287
288 sata3_pins: sa
289 marvel
290 marvel
291 };
292
293 i2s_pins: i2s-
294 marvel
295
296
297 marvel
298 };
299
300 spdif_pins: sp
301 marvel
302 marvel
303 };
304 };
305
306 gpio0: gpio@18100 {
307 compatible = "
308 "
309 reg = <0x18100
310 reg-names = "g
311 ngpios = <32>;
312 gpio-controlle
313 gpio-ranges =
314 #gpio-cells =
315 #pwm-cells = <
316 interrupt-cont
317 #interrupt-cel
318 interrupts = <
319 <
320 <
321 <
322 clocks = <&cor
323 };
324
325 gpio1: gpio@18140 {
326 compatible = "
327 "
328 reg = <0x18140
329 reg-names = "g
330 ngpios = <28>;
331 gpio-controlle
332 gpio-ranges =
333 #gpio-cells =
334 #pwm-cells = <
335 interrupt-cont
336 #interrupt-cel
337 interrupts = <
338 <
339 <
340 <
341 clocks = <&cor
342 };
343
344 systemc: system-contro
345 compatible = "
346 "
347 reg = <0x18200
348 };
349
350 gateclk: clock-gating-
351 compatible = "
352 reg = <0x18220
353 clocks = <&cor
354 #clock-cells =
355 };
356
357 comphy: phy@18300 {
358 compatible = "
359 reg-names = "c
360 reg = <0x18300
361 #address-cells
362 #size-cells =
363
364 comphy0: phy@0
365 reg =
366 #phy-c
367 };
368
369 comphy1: phy@1
370 reg =
371 #phy-c
372 };
373
374 comphy2: phy@2
375 reg =
376 #phy-c
377 };
378
379 comphy3: phy@3
380 reg =
381 #phy-c
382 };
383
384 comphy4: phy@4
385 reg =
386 #phy-c
387 };
388
389 comphy5: phy@5
390 reg =
391 #phy-c
392 };
393 };
394
395 coreclk: mvebu-sar@186
396 compatible = "
397 reg = <0x18600
398 #clock-cells =
399 };
400
401 mbusc: mbus-controller
402 compatible = "
403 reg = <0x20000
404 <0x20250
405 };
406
407 mpic: interrupt-contro
408 compatible = "
409 reg = <0x20a00
410 #interrupt-cel
411 interrupt-cont
412 msi-controller
413 interrupts = <
414 };
415
416 timer: timer@20300 {
417 compatible = "
418 "
419 reg = <0x20300
420 interrupts-ext
421
422
423
424
425
426 clocks = <&cor
427 clock-names =
428 };
429
430 watchdog: watchdog@203
431 compatible = "
432 reg = <0x20300
433 clocks = <&cor
434 clock-names =
435 interrupts-ext
436
437 };
438
439 cpurst: cpurst@20800 {
440 compatible = "
441 reg = <0x20800
442 };
443
444 mpcore-soc-ctrl@20d20
445 compatible = "
446 reg = <0x20d20
447 };
448
449 coherencyfab: coherenc
450 compatible = "
451 reg = <0x21010
452 };
453
454 pmsu: pmsu@22000 {
455 compatible = "
456 reg = <0x22000
457 };
458
459 /*
460 * As a special except
461 * register address" r
462 * placed here to ensu
463 * registered as the f
464 * the network subsyst
465 * interfaces using DT
466 * the ordering of int
467 * from the one used i
468 * labeling of interfa
469 * is very confusing f
470 */
471 eth0: ethernet@70000 {
472 compatible = "
473 reg = <0x70000
474 interrupts-ext
475 clocks = <&gat
476 tx-csum-limit
477 status = "disa
478 };
479
480 eth1: ethernet@30000 {
481 compatible = "
482 reg = <0x30000
483 interrupts-ext
484 clocks = <&gat
485 status = "disa
486 };
487
488 eth2: ethernet@34000 {
489 compatible = "
490 reg = <0x34000
491 interrupts-ext
492 clocks = <&gat
493 status = "disa
494 };
495
496 usb0: usb@58000 {
497 compatible = "
498 reg = <0x58000
499 interrupts = <
500 clocks = <&gat
501 status = "disa
502 };
503
504 xor0: xor@60800 {
505 compatible = "
506 reg = <0x60800
507 0x60a00
508 clocks = <&gat
509 status = "okay
510
511 xor00 {
512 interr
513 dmacap
514 dmacap
515 };
516 xor01 {
517 interr
518 dmacap
519 dmacap
520 dmacap
521 };
522 };
523
524 xor1: xor@60900 {
525 compatible = "
526 reg = <0x60900
527 0x60b00
528 clocks = <&gat
529 status = "okay
530
531 xor10 {
532 interr
533 dmacap
534 dmacap
535 };
536 xor11 {
537 interr
538 dmacap
539 dmacap
540 dmacap
541 };
542 };
543
544 mdio: mdio@72004 {
545 #address-cells
546 #size-cells =
547 compatible = "
548 reg = <0x72004
549 clocks = <&gat
550 };
551
552 cesa: crypto@90000 {
553 compatible = "
554 reg = <0x90000
555 reg-names = "r
556 interrupts = <
557 <
558 clocks = <&gat
559 <&gat
560 clock-names =
561
562 marvell,crypto
563
564 marvell,crypto
565 };
566
567 rtc: rtc@a3800 {
568 compatible = "
569 reg = <0xa3800
570 reg-names = "r
571 interrupts = <
572 };
573
574 ahci0: sata@a8000 {
575 compatible = "
576 reg = <0xa8000
577 interrupts = <
578 clocks = <&gat
579 status = "disa
580 };
581
582 bm: bm@c8000 {
583 compatible = "
584 reg = <0xc8000
585 clocks = <&gat
586 internal-mem =
587 status = "disa
588 };
589
590 ahci1: sata@e0000 {
591 compatible = "
592 reg = <0xe0000
593 interrupts = <
594 clocks = <&gat
595 status = "disa
596 };
597
598 coredivclk: clock@e425
599 compatible = "
600 reg = <0xe4250
601 #clock-cells =
602 clocks = <&mai
603 clock-output-n
604 };
605
606 thermal: thermal@e8078
607 compatible = "
608 reg = <0xe4078
609 status = "okay
610 };
611
612 nand_controller: nand-
613 compatible = "
614 reg = <0xd0000
615 #address-cells
616 #size-cells =
617 interrupts = <
618 clocks = <&cor
619 status = "disa
620 };
621
622 sdhci: sdhci@d8000 {
623 compatible = "
624 reg-names = "s
625 reg = <0xd8000
626 <0xdc0
627 <0x184
628 interrupts = <
629 clocks = <&gat
630 mrvl,clk-delay
631 status = "disa
632 };
633
634 audio_controller: audi
635 #sound-dai-cel
636 compatible = "
637 reg = <0xe8000
638 <0x18204
639 reg-names = "i
640 interrupts = <
641 clocks = <&gat
642 clock-names =
643 status = "disa
644 };
645
646 usb3_0: usb3@f0000 {
647 compatible = "
648 reg = <0xf0000
649 interrupts = <
650 clocks = <&gat
651 status = "disa
652 };
653
654 usb3_1: usb3@f8000 {
655 compatible = "
656 reg = <0xf8000
657 interrupts = <
658 clocks = <&gat
659 status = "disa
660 };
661 };
662
663 crypto_sram0: sa-sram0 {
664 compatible = "mmio-sra
665 reg = <MBUS_ID(0x09, 0
666 clocks = <&gateclk 23>
667 #address-cells = <1>;
668 #size-cells = <1>;
669 ranges = <0 MBUS_ID(0x
670 };
671
672 crypto_sram1: sa-sram1 {
673 compatible = "mmio-sra
674 reg = <MBUS_ID(0x09, 0
675 clocks = <&gateclk 21>
676 #address-cells = <1>;
677 #size-cells = <1>;
678 ranges = <0 MBUS_ID(0x
679 };
680
681 bm_bppi: bm-bppi {
682 compatible = "mmio-sra
683 reg = <MBUS_ID(0x0c, 0
684 ranges = <0 MBUS_ID(0x
685 #address-cells = <1>;
686 #size-cells = <1>;
687 clocks = <&gateclk 13>
688 no-memory-wc;
689 status = "disabled";
690 };
691
692 spi0: spi@10600 {
693 compatible = "marvell,
694 "marve
695 reg = <MBUS_ID(0xf0, 0
696 #address-cells = <1>;
697 #size-cells = <0>;
698 cell-index = <0>;
699 interrupts = <GIC_SPI
700 clocks = <&coreclk 0>;
701 status = "disabled";
702 };
703
704 spi1: spi@10680 {
705 compatible = "marvell,
706 "marve
707 reg = <MBUS_ID(0xf0, 0
708 #address-cells = <1>;
709 #size-cells = <0>;
710 cell-index = <1>;
711 interrupts = <GIC_SPI
712 clocks = <&coreclk 0>;
713 status = "disabled";
714 };
715 };
716
717 clocks {
718 /* 1 GHz fixed main PLL */
719 mainpll: mainpll {
720 compatible = "fixed-cl
721 #clock-cells = <0>;
722 clock-frequency = <100
723 };
724
725 /* 25 MHz reference crystal */
726 refclk: oscillator {
727 compatible = "fixed-cl
728 #clock-cells = <0>;
729 clock-frequency = <250
730 };
731 };
732 };
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