1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell 98dx32
4 *
5 * Copyright (C) 2016 Allied Telesis Labs
6 *
7 * Contains definitions specific to the 98dx32
8 * common to all Armada XP SoCs.
9 */
10
11 #include "armada-370-xp.dtsi"
12
13 / {
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 model = "Marvell 98DX3236 SoC";
18 compatible = "marvell,armadaxp-98dx323
19
20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,98dx3
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "marvell,
34 reg = <0>;
35 clocks = <&cpuclk 0>;
36 clock-latency = <10000
37 };
38 };
39
40 soc {
41 compatible = "marvell,armadaxp
42
43 ranges = <MBUS_ID(0xf0, 0x01)
44 MBUS_ID(0x01, 0x1d)
45 MBUS_ID(0x01, 0x2f)
46 MBUS_ID(0x03, 0x00)
47 MBUS_ID(0x08, 0x00)
48
49 bootrom {
50 compatible = "marvell,
51 reg = <MBUS_ID(0x01, 0
52 };
53
54 /*
55 * 98DX3236 has 1 x1 PCIe unit
56 */
57 pciec: pcie@82000000 {
58 compatible = "marvell,
59 status = "disabled";
60 device_type = "pci";
61
62 #address-cells = <3>;
63 #size-cells = <2>;
64
65 msi-parent = <&mpic>;
66 bus-range = <0x00 0xff
67
68 ranges =
69 <0x82000000 0 0
70 0x82000000 0x1
71 0x81000000 0x1
72
73 pcie1: pcie@1,0 {
74 device_type =
75 assigned-addre
76 reg = <0x0800
77 #address-cells
78 #size-cells =
79 interrupt-name
80 interrupts-ext
81 #interrupt-cel
82 ranges = <0x82
83 0x81
84 bus-range = <0
85 interrupt-map-
86 interrupt-map
87
88
89
90 marvell,pcie-p
91 marvell,pcie-l
92 clocks = <&gat
93 status = "disa
94
95 pcie1_intc: in
96 interr
97 #inter
98 };
99 };
100 };
101
102 internal-regs {
103 sdramc: sdramc@1400 {
104 compatible = "
105 reg = <0x1400
106 };
107
108 L2: l2-cache@8000 {
109 compatible = "
110 reg = <0x08000
111 cache-id-part
112 cache-level =
113 cache-unified;
114 wt-override;
115 };
116
117 gpio0: gpio@18100 {
118 compatible = "
119 reg = <0x18100
120 ngpios = <32>;
121 gpio-controlle
122 #gpio-cells =
123 interrupt-cont
124 #interrupt-cel
125 interrupts = <
126 };
127
128 /* does not exist */
129 gpio1: gpio@18140 {
130 compatible = "
131 reg = <0x18140
132 status = "disa
133 };
134
135 gpio2: gpio@18180 { /*
136 compatible = "
137 reg = <0x18180
138 ngpios = <1>;
139 gpio-controlle
140 #gpio-cells =
141 interrupt-cont
142 #interrupt-cel
143 interrupts = <
144 };
145
146 systemc: system-contro
147 compatible = "
148 reg = <0x18200
149 };
150
151 gateclk: clock-gating-
152 compatible = "
153 reg = <0x18220
154 clocks = <&cor
155 #clock-cells =
156 };
157
158 cpuclk: clock-complex@
159 #clock-cells =
160 compatible = "
161 reg = <0x18700
162 clocks = <&cor
163 };
164
165 corediv-clock@18740 {
166 status = "disa
167 };
168
169 cpu-config@21000 {
170 compatible = "
171 reg = <0x21000
172 };
173
174 ethernet@70000 {
175 compatible = "
176 };
177
178 ethernet@74000 {
179 compatible = "
180 };
181
182 xor1: xor@f0800 {
183 compatible = "
184 reg = <0xf0800
185 0xf0a00
186 clocks = <&gat
187 status = "okay
188
189 xor10 {
190 interr
191 dmacap
192 dmacap
193 };
194 xor11 {
195 interr
196 dmacap
197 dmacap
198 dmacap
199 };
200 };
201
202 nand_controller: nand-
203 clocks = <&dfx
204 };
205
206 xor0: xor@f0900 {
207 compatible = "
208 reg = <0xF0900
209 0xF0B00
210 clocks = <&gat
211 status = "okay
212
213 xor00 {
214 interr
215 dmacap
216 dmacap
217 };
218 xor01 {
219 interr
220 dmacap
221 dmacap
222 dmacap
223 };
224 };
225 };
226
227 dfx: dfx-server@ac000000 {
228 compatible = "marvell,
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0 MBUS_ID(0x
232 reg = <MBUS_ID(0x08, 0
233
234 coreclk: mvebu-sar@f82
235 compatible = "
236 reg = <0xf8204
237 #clock-cells =
238 };
239
240 dfx_coredivclk: coredi
241 compatible = "
242 reg = <0xf8268
243 #clock-cells =
244 clocks = <&mai
245 clock-output-n
246 };
247 };
248
249 switch: switch@a8000000 {
250 compatible = "simple-b
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0 MBUS_ID(0x
254
255 pp0: packet-processor@
256 compatible = "
257 reg = <0 0x400
258 interrupts = <
259 dfx = <&dfx>;
260 };
261 };
262 };
263
264 clocks {
265 /* 25 MHz reference crystal */
266 refclk: oscillator {
267 compatible = "fixed-cl
268 #clock-cells = <0>;
269 clock-frequency = <250
270 };
271 };
272 };
273
274 &i2c0 {
275 compatible = "marvell,mv78230-i2c", "m
276 reg = <0x11000 0x100>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_pins>;
279 };
280
281 &mpic {
282 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
283 };
284
285 &rtc {
286 status = "disabled";
287 };
288
289 &timer {
290 compatible = "marvell,armada-xp-timer"
291 clocks = <&coreclk 2>, <&refclk>;
292 clock-names = "nbclk", "fixed";
293 };
294
295 &watchdog {
296 compatible = "marvell,armada-xp-wdt";
297 clocks = <&coreclk 2>, <&refclk>;
298 clock-names = "nbclk", "fixed";
299 interrupts = <93>, <38>;
300 };
301
302 &cpurst {
303 reg = <0x20800 0x20>;
304 };
305
306 &usb0 {
307 clocks = <&gateclk 18>;
308 };
309
310 &usb1 {
311 clocks = <&gateclk 19>;
312 };
313
314 &pinctrl {
315 compatible = "marvell,98dx3236-pinctrl
316
317 nand_pins: nand-pins {
318 marvell,pins = "mpp20", "mpp21
319 "mpp23", "mpp24
320 "mpp26", "mpp27
321 "mpp29", "mpp30
322 marvell,function = "dev";
323 };
324
325 nand_rb: nand-rb {
326 marvell,pins = "mpp19";
327 marvell,function = "nand";
328 };
329
330 spi0_pins: spi0-pins {
331 marvell,pins = "mpp0", "mpp1",
332 "mpp2", "mpp3";
333 marvell,function = "spi0";
334 };
335
336 i2c0_pins: i2c-pins-0 {
337 marvell,pins = "mpp14", "mpp15
338 marvell,function = "i2c0";
339 };
340 };
341
342 &spi0 {
343 compatible = "marvell,armada-xp-spi",
344 pinctrl-0 = <&spi0_pins>;
345 pinctrl-names = "default";
346 };
347
348 &sdio {
349 status = "disabled";
350 };
351
352 &uart0 {
353 compatible = "marvell,armada-38x-uart"
354 };
355
356 &uart1 {
357 compatible = "marvell,armada-38x-uart"
358 };
359
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