1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Marvell 98dx32 3 * Device Tree Include file for Marvell 98dx3236 family SoC
4 * 4 *
5 * Copyright (C) 2016 Allied Telesis Labs 5 * Copyright (C) 2016 Allied Telesis Labs
6 * 6 *
7 * Contains definitions specific to the 98dx32 7 * Contains definitions specific to the 98dx3236 SoC that are not
8 * common to all Armada XP SoCs. 8 * common to all Armada XP SoCs.
9 */ 9 */
10 10
11 #include "armada-370-xp.dtsi" 11 #include "armada-370-xp.dtsi"
12 12
13 / { 13 / {
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 model = "Marvell 98DX3236 SoC"; 17 model = "Marvell 98DX3236 SoC";
18 compatible = "marvell,armadaxp-98dx323 18 compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
19 19
20 aliases { 20 aliases {
21 gpio0 = &gpio0; 21 gpio0 = &gpio0;
22 gpio1 = &gpio1; 22 gpio1 = &gpio1;
23 gpio2 = &gpio2; 23 gpio2 = &gpio2;
24 }; 24 };
25 25
26 cpus { 26 cpus {
27 #address-cells = <1>; 27 #address-cells = <1>;
28 #size-cells = <0>; 28 #size-cells = <0>;
29 enable-method = "marvell,98dx3 29 enable-method = "marvell,98dx3236-smp";
30 30
31 cpu@0 { 31 cpu@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 compatible = "marvell, 33 compatible = "marvell,sheeva-v7";
34 reg = <0>; 34 reg = <0>;
35 clocks = <&cpuclk 0>; 35 clocks = <&cpuclk 0>;
36 clock-latency = <10000 36 clock-latency = <1000000>;
37 }; 37 };
38 }; 38 };
39 39
40 soc { 40 soc {
41 compatible = "marvell,armadaxp 41 compatible = "marvell,armadaxp-mbus", "simple-bus";
42 42
43 ranges = <MBUS_ID(0xf0, 0x01) 43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
48 48
49 bootrom { 49 bootrom {
50 compatible = "marvell, 50 compatible = "marvell,bootrom";
51 reg = <MBUS_ID(0x01, 0 51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
52 }; 52 };
53 53
54 /* 54 /*
55 * 98DX3236 has 1 x1 PCIe unit 55 * 98DX3236 has 1 x1 PCIe unit Gen2.0
56 */ 56 */
57 pciec: pcie@82000000 { 57 pciec: pcie@82000000 {
58 compatible = "marvell, 58 compatible = "marvell,armada-xp-pcie";
59 status = "disabled"; 59 status = "disabled";
60 device_type = "pci"; 60 device_type = "pci";
61 61
62 #address-cells = <3>; 62 #address-cells = <3>;
63 #size-cells = <2>; 63 #size-cells = <2>;
64 64
65 msi-parent = <&mpic>; 65 msi-parent = <&mpic>;
66 bus-range = <0x00 0xff 66 bus-range = <0x00 0xff>;
67 67
68 ranges = 68 ranges =
69 <0x82000000 0 0 69 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
70 0x82000000 0x1 70 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
71 0x81000000 0x1 71 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
72 72
73 pcie1: pcie@1,0 { 73 pcie1: pcie@1,0 {
74 device_type = 74 device_type = "pci";
75 assigned-addre 75 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
76 reg = <0x0800 76 reg = <0x0800 0 0 0 0>;
77 #address-cells 77 #address-cells = <3>;
78 #size-cells = 78 #size-cells = <2>;
79 interrupt-name 79 interrupt-names = "intx";
80 interrupts-ext 80 interrupts-extended = <&mpic 58>;
81 #interrupt-cel 81 #interrupt-cells = <1>;
82 ranges = <0x82 82 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
83 0x81 83 0x81000000 0 0 0x81000000 0x1 0 1 0>;
84 bus-range = <0 84 bus-range = <0x00 0xff>;
85 interrupt-map- 85 interrupt-map-mask = <0 0 0 7>;
86 interrupt-map 86 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
87 87 <0 0 0 2 &pcie1_intc 1>,
88 88 <0 0 0 3 &pcie1_intc 2>,
89 89 <0 0 0 4 &pcie1_intc 3>;
90 marvell,pcie-p 90 marvell,pcie-port = <0>;
91 marvell,pcie-l 91 marvell,pcie-lane = <0>;
92 clocks = <&gat 92 clocks = <&gateclk 5>;
93 status = "disa 93 status = "disabled";
94 94
95 pcie1_intc: in 95 pcie1_intc: interrupt-controller {
96 interr 96 interrupt-controller;
97 #inter 97 #interrupt-cells = <1>;
98 }; 98 };
99 }; 99 };
100 }; 100 };
101 101
102 internal-regs { 102 internal-regs {
103 sdramc: sdramc@1400 { 103 sdramc: sdramc@1400 {
104 compatible = " 104 compatible = "marvell,armada-xp-sdram-controller";
105 reg = <0x1400 105 reg = <0x1400 0x500>;
106 }; 106 };
107 107
108 L2: l2-cache@8000 { 108 L2: l2-cache@8000 {
109 compatible = " 109 compatible = "marvell,aurora-system-cache";
110 reg = <0x08000 110 reg = <0x08000 0x1000>;
111 cache-id-part 111 cache-id-part = <0x100>;
112 cache-level = 112 cache-level = <2>;
113 cache-unified; 113 cache-unified;
114 wt-override; 114 wt-override;
115 }; 115 };
116 116
117 gpio0: gpio@18100 { 117 gpio0: gpio@18100 {
118 compatible = " 118 compatible = "marvell,orion-gpio";
119 reg = <0x18100 119 reg = <0x18100 0x40>;
120 ngpios = <32>; 120 ngpios = <32>;
121 gpio-controlle 121 gpio-controller;
122 #gpio-cells = 122 #gpio-cells = <2>;
123 interrupt-cont 123 interrupt-controller;
124 #interrupt-cel 124 #interrupt-cells = <2>;
125 interrupts = < 125 interrupts = <82>, <83>, <84>, <85>;
126 }; 126 };
127 127
128 /* does not exist */ 128 /* does not exist */
129 gpio1: gpio@18140 { 129 gpio1: gpio@18140 {
130 compatible = " 130 compatible = "marvell,orion-gpio";
131 reg = <0x18140 131 reg = <0x18140 0x40>;
132 status = "disa 132 status = "disabled";
133 }; 133 };
134 134
135 gpio2: gpio@18180 { /* 135 gpio2: gpio@18180 { /* rework some properties */
136 compatible = " 136 compatible = "marvell,orion-gpio";
137 reg = <0x18180 137 reg = <0x18180 0x40>;
138 ngpios = <1>; 138 ngpios = <1>; /* only gpio #32 */
139 gpio-controlle 139 gpio-controller;
140 #gpio-cells = 140 #gpio-cells = <2>;
141 interrupt-cont 141 interrupt-controller;
142 #interrupt-cel 142 #interrupt-cells = <2>;
143 interrupts = < 143 interrupts = <87>;
144 }; 144 };
145 145
146 systemc: system-contro 146 systemc: system-controller@18200 {
147 compatible = " 147 compatible = "marvell,armada-370-xp-system-controller";
148 reg = <0x18200 148 reg = <0x18200 0x500>;
149 }; 149 };
150 150
151 gateclk: clock-gating- 151 gateclk: clock-gating-control@18220 {
152 compatible = " 152 compatible = "marvell,mv98dx3236-gating-clock";
153 reg = <0x18220 153 reg = <0x18220 0x4>;
154 clocks = <&cor 154 clocks = <&coreclk 0>;
155 #clock-cells = 155 #clock-cells = <1>;
156 }; 156 };
157 157
158 cpuclk: clock-complex@ 158 cpuclk: clock-complex@18700 {
159 #clock-cells = 159 #clock-cells = <1>;
160 compatible = " 160 compatible = "marvell,mv98dx3236-cpu-clock";
161 reg = <0x18700 161 reg = <0x18700 0x24>, <0x1c054 0x10>;
162 clocks = <&cor 162 clocks = <&coreclk 1>;
163 }; 163 };
164 164
165 corediv-clock@18740 { 165 corediv-clock@18740 {
166 status = "disa 166 status = "disabled";
167 }; 167 };
168 168
169 cpu-config@21000 { 169 cpu-config@21000 {
170 compatible = " 170 compatible = "marvell,armada-xp-cpu-config";
171 reg = <0x21000 171 reg = <0x21000 0x8>;
172 }; 172 };
173 173
174 ethernet@70000 { 174 ethernet@70000 {
175 compatible = " 175 compatible = "marvell,armada-xp-neta";
176 }; 176 };
177 177
178 ethernet@74000 { 178 ethernet@74000 {
179 compatible = " 179 compatible = "marvell,armada-xp-neta";
180 }; 180 };
181 181
182 xor1: xor@f0800 { 182 xor1: xor@f0800 {
183 compatible = " 183 compatible = "marvell,orion-xor";
184 reg = <0xf0800 184 reg = <0xf0800 0x100
185 0xf0a00 185 0xf0a00 0x100>;
186 clocks = <&gat 186 clocks = <&gateclk 22>;
187 status = "okay 187 status = "okay";
188 188
189 xor10 { 189 xor10 {
190 interr 190 interrupts = <51>;
191 dmacap 191 dmacap,memcpy;
192 dmacap 192 dmacap,xor;
193 }; 193 };
194 xor11 { 194 xor11 {
195 interr 195 interrupts = <52>;
196 dmacap 196 dmacap,memcpy;
197 dmacap 197 dmacap,xor;
198 dmacap 198 dmacap,memset;
199 }; 199 };
200 }; 200 };
201 201
202 nand_controller: nand- 202 nand_controller: nand-controller@d0000 {
203 clocks = <&dfx 203 clocks = <&dfx_coredivclk 0>;
204 }; 204 };
205 205
206 xor0: xor@f0900 { 206 xor0: xor@f0900 {
207 compatible = " 207 compatible = "marvell,orion-xor";
208 reg = <0xF0900 208 reg = <0xF0900 0x100
209 0xF0B00 209 0xF0B00 0x100>;
210 clocks = <&gat 210 clocks = <&gateclk 28>;
211 status = "okay 211 status = "okay";
212 212
213 xor00 { 213 xor00 {
214 interr 214 interrupts = <94>;
215 dmacap 215 dmacap,memcpy;
216 dmacap 216 dmacap,xor;
217 }; 217 };
218 xor01 { 218 xor01 {
219 interr 219 interrupts = <95>;
220 dmacap 220 dmacap,memcpy;
221 dmacap 221 dmacap,xor;
222 dmacap 222 dmacap,memset;
223 }; 223 };
224 }; 224 };
225 }; 225 };
226 226
227 dfx: dfx-server@ac000000 { 227 dfx: dfx-server@ac000000 {
228 compatible = "marvell, 228 compatible = "marvell,dfx-server", "simple-bus";
229 #address-cells = <1>; 229 #address-cells = <1>;
230 #size-cells = <1>; 230 #size-cells = <1>;
231 ranges = <0 MBUS_ID(0x 231 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
232 reg = <MBUS_ID(0x08, 0 232 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
233 233
234 coreclk: mvebu-sar@f82 234 coreclk: mvebu-sar@f8204 {
235 compatible = " 235 compatible = "marvell,mv98dx3236-core-clock";
236 reg = <0xf8204 236 reg = <0xf8204 0x4>;
237 #clock-cells = 237 #clock-cells = <1>;
238 }; 238 };
239 239
240 dfx_coredivclk: coredi 240 dfx_coredivclk: corediv-clock@f8268 {
241 compatible = " 241 compatible = "marvell,mv98dx3236-corediv-clock";
242 reg = <0xf8268 242 reg = <0xf8268 0xc>;
243 #clock-cells = 243 #clock-cells = <1>;
244 clocks = <&mai 244 clocks = <&mainpll>;
245 clock-output-n 245 clock-output-names = "nand";
246 }; 246 };
247 }; 247 };
248 248
249 switch: switch@a8000000 { 249 switch: switch@a8000000 {
250 compatible = "simple-b 250 compatible = "simple-bus";
251 #address-cells = <1>; 251 #address-cells = <1>;
252 #size-cells = <1>; 252 #size-cells = <1>;
253 ranges = <0 MBUS_ID(0x 253 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
254 254
255 pp0: packet-processor@ 255 pp0: packet-processor@0 {
256 compatible = " 256 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
257 reg = <0 0x400 257 reg = <0 0x4000000>;
258 interrupts = < 258 interrupts = <33>, <34>, <35>;
259 dfx = <&dfx>; 259 dfx = <&dfx>;
260 }; 260 };
261 }; 261 };
262 }; 262 };
263 263
264 clocks { 264 clocks {
265 /* 25 MHz reference crystal */ 265 /* 25 MHz reference crystal */
266 refclk: oscillator { 266 refclk: oscillator {
267 compatible = "fixed-cl 267 compatible = "fixed-clock";
268 #clock-cells = <0>; 268 #clock-cells = <0>;
269 clock-frequency = <250 269 clock-frequency = <25000000>;
270 }; 270 };
271 }; 271 };
272 }; 272 };
273 273
274 &i2c0 { 274 &i2c0 {
275 compatible = "marvell,mv78230-i2c", "m 275 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
276 reg = <0x11000 0x100>; 276 reg = <0x11000 0x100>;
277 pinctrl-names = "default"; 277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_pins>; 278 pinctrl-0 = <&i2c0_pins>;
279 }; 279 };
280 280
281 &mpic { 281 &mpic {
282 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 282 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
283 }; 283 };
284 284
285 &rtc { 285 &rtc {
286 status = "disabled"; 286 status = "disabled";
287 }; 287 };
288 288
289 &timer { 289 &timer {
290 compatible = "marvell,armada-xp-timer" 290 compatible = "marvell,armada-xp-timer";
291 clocks = <&coreclk 2>, <&refclk>; 291 clocks = <&coreclk 2>, <&refclk>;
292 clock-names = "nbclk", "fixed"; 292 clock-names = "nbclk", "fixed";
293 }; 293 };
294 294
295 &watchdog { 295 &watchdog {
296 compatible = "marvell,armada-xp-wdt"; 296 compatible = "marvell,armada-xp-wdt";
297 clocks = <&coreclk 2>, <&refclk>; 297 clocks = <&coreclk 2>, <&refclk>;
298 clock-names = "nbclk", "fixed"; 298 clock-names = "nbclk", "fixed";
299 interrupts = <93>, <38>; 299 interrupts = <93>, <38>;
300 }; 300 };
301 301
302 &cpurst { 302 &cpurst {
303 reg = <0x20800 0x20>; 303 reg = <0x20800 0x20>;
304 }; 304 };
305 305
306 &usb0 { 306 &usb0 {
307 clocks = <&gateclk 18>; 307 clocks = <&gateclk 18>;
308 }; 308 };
309 309
310 &usb1 { 310 &usb1 {
311 clocks = <&gateclk 19>; 311 clocks = <&gateclk 19>;
312 }; 312 };
313 313
314 &pinctrl { 314 &pinctrl {
315 compatible = "marvell,98dx3236-pinctrl 315 compatible = "marvell,98dx3236-pinctrl";
316 316
317 nand_pins: nand-pins { 317 nand_pins: nand-pins {
318 marvell,pins = "mpp20", "mpp21 318 marvell,pins = "mpp20", "mpp21", "mpp22",
319 "mpp23", "mpp24 319 "mpp23", "mpp24", "mpp25",
320 "mpp26", "mpp27 320 "mpp26", "mpp27", "mpp28",
321 "mpp29", "mpp30 321 "mpp29", "mpp30";
322 marvell,function = "dev"; 322 marvell,function = "dev";
323 }; 323 };
324 324
325 nand_rb: nand-rb { 325 nand_rb: nand-rb {
326 marvell,pins = "mpp19"; 326 marvell,pins = "mpp19";
327 marvell,function = "nand"; 327 marvell,function = "nand";
328 }; 328 };
329 329
330 spi0_pins: spi0-pins { 330 spi0_pins: spi0-pins {
331 marvell,pins = "mpp0", "mpp1", 331 marvell,pins = "mpp0", "mpp1",
332 "mpp2", "mpp3"; 332 "mpp2", "mpp3";
333 marvell,function = "spi0"; 333 marvell,function = "spi0";
334 }; 334 };
335 335
336 i2c0_pins: i2c-pins-0 { 336 i2c0_pins: i2c-pins-0 {
337 marvell,pins = "mpp14", "mpp15 337 marvell,pins = "mpp14", "mpp15";
338 marvell,function = "i2c0"; 338 marvell,function = "i2c0";
339 }; 339 };
340 }; 340 };
341 341
342 &spi0 { 342 &spi0 {
343 compatible = "marvell,armada-xp-spi", 343 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
344 pinctrl-0 = <&spi0_pins>; 344 pinctrl-0 = <&spi0_pins>;
345 pinctrl-names = "default"; 345 pinctrl-names = "default";
346 }; 346 };
347 347
348 &sdio { 348 &sdio {
349 status = "disabled"; 349 status = "disabled";
350 }; 350 };
351 351
352 &uart0 { 352 &uart0 {
353 compatible = "marvell,armada-38x-uart" 353 compatible = "marvell,armada-38x-uart";
354 }; 354 };
355 355
356 &uart1 { 356 &uart1 {
357 compatible = "marvell,armada-38x-uart" 357 compatible = "marvell,armada-38x-uart";
358 }; 358 };
359 359
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