1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for DB-XC3-24G4XG board 3 * Device Tree file for DB-XC3-24G4XG board
4 * 4 *
5 * Copyright (C) 2016 Allied Telesis Labs 5 * Copyright (C) 2016 Allied Telesis Labs
6 * 6 *
7 * Based on armada-xp-db.dts 7 * Based on armada-xp-db.dts
8 * 8 *
9 * Note: this Device Tree assumes that the boo 9 * Note: this Device Tree assumes that the bootloader has remapped the
10 * internal registers to 0xf1000000 (instead o 10 * internal registers to 0xf1000000 (instead of the default
11 * 0xd0000000). The 0xf1000000 is the default 11 * 0xd0000000). The 0xf1000000 is the default used by the recent,
12 * DT-capable, U-Boot bootloaders provided by 12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
13 * boards were delivered with an older version 13 * boards were delivered with an older version of the bootloader that
14 * left internal registers mapped at 0xd000000 14 * left internal registers mapped at 0xd0000000. If you are in this
15 * situation, you should either update your bo 15 * situation, you should either update your bootloader (preferred
16 * solution) or the below Device Tree should b 16 * solution) or the below Device Tree should be adjusted.
17 */ 17 */
18 18
19 /dts-v1/; 19 /dts-v1/;
20 #include "armada-xp-98dx3336.dtsi" 20 #include "armada-xp-98dx3336.dtsi"
21 21
22 / { 22 / {
23 model = "DB-XC3-24G4XG"; 23 model = "DB-XC3-24G4XG";
24 compatible = "marvell,db-xc3-24g4xg", 24 compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
25 25
26 chosen { 26 chosen {
27 bootargs = "console=ttyS0,1152 27 bootargs = "console=ttyS0,115200 earlyprintk";
28 }; 28 };
29 29
30 memory { 30 memory {
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0 0x00000000 0 0x400000 32 reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
33 }; 33 };
34 }; 34 };
35 35
36 &L2 { 36 &L2 {
37 arm,parity-enable; 37 arm,parity-enable;
38 marvell,ecc-enable; 38 marvell,ecc-enable;
39 }; 39 };
40 40
41 &devbus_bootcs { 41 &devbus_bootcs {
42 status = "okay"; 42 status = "okay";
43 43
44 /* Device Bus parameters are required 44 /* Device Bus parameters are required */
45 45
46 /* Read parameters */ 46 /* Read parameters */
47 devbus,bus-width = <16>; 47 devbus,bus-width = <16>;
48 devbus,turn-off-ps = <60000>; 48 devbus,turn-off-ps = <60000>;
49 devbus,badr-skew-ps = <0>; 49 devbus,badr-skew-ps = <0>;
50 devbus,acc-first-ps = <124000>; 50 devbus,acc-first-ps = <124000>;
51 devbus,acc-next-ps = <248000>; 51 devbus,acc-next-ps = <248000>;
52 devbus,rd-setup-ps = <0>; 52 devbus,rd-setup-ps = <0>;
53 devbus,rd-hold-ps = <0>; 53 devbus,rd-hold-ps = <0>;
54 54
55 /* Write parameters */ 55 /* Write parameters */
56 devbus,sync-enable = <0>; 56 devbus,sync-enable = <0>;
57 devbus,wr-high-ps = <60000>; 57 devbus,wr-high-ps = <60000>;
58 devbus,wr-low-ps = <60000>; 58 devbus,wr-low-ps = <60000>;
59 devbus,ale-wr-ps = <60000>; 59 devbus,ale-wr-ps = <60000>;
60 }; 60 };
61 61
62 &uart0 { 62 &uart0 {
63 status = "okay"; 63 status = "okay";
64 }; 64 };
65 65
66 &uart1 { 66 &uart1 {
67 status = "okay"; 67 status = "okay";
68 }; 68 };
69 69
70 &i2c0 { 70 &i2c0 {
71 clock-frequency = <100000>; 71 clock-frequency = <100000>;
72 status = "okay"; 72 status = "okay";
73 }; 73 };
74 74
75 &nand_controller { 75 &nand_controller {
76 status = "okay"; 76 status = "okay";
77 77
78 nand@0 { 78 nand@0 {
79 reg = <0>; 79 reg = <0>;
80 label = "pxa3xx_nand-0"; 80 label = "pxa3xx_nand-0";
81 nand-rb = <0>; 81 nand-rb = <0>;
82 marvell,nand-keep-config; 82 marvell,nand-keep-config;
83 nand-on-flash-bbt; 83 nand-on-flash-bbt;
84 nand-ecc-strength = <4>; 84 nand-ecc-strength = <4>;
85 nand-ecc-step-size = <512>; 85 nand-ecc-step-size = <512>;
86 }; 86 };
87 }; 87 };
88 88
89 &spi0 { 89 &spi0 {
90 status = "okay"; 90 status = "okay";
91 91
92 flash@0 { 92 flash@0 {
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <1>; 94 #size-cells = <1>;
95 compatible = "m25p64"; 95 compatible = "m25p64";
96 reg = <0>; /* Chip select 0 */ 96 reg = <0>; /* Chip select 0 */
97 spi-max-frequency = <20000000> 97 spi-max-frequency = <20000000>;
98 m25p,fast-read; 98 m25p,fast-read;
99 99
100 partition@u-boot { 100 partition@u-boot {
101 reg = <0x00000000 0x00 101 reg = <0x00000000 0x00100000>;
102 label = "u-boot"; 102 label = "u-boot";
103 }; 103 };
104 partition@u-boot-env { 104 partition@u-boot-env {
105 reg = <0x00100000 0x00 105 reg = <0x00100000 0x00040000>;
106 label = "u-boot-env"; 106 label = "u-boot-env";
107 }; 107 };
108 partition@unused { 108 partition@unused {
109 reg = <0x00140000 0x00 109 reg = <0x00140000 0x00ec0000>;
110 label = "unused"; 110 label = "unused";
111 }; 111 };
112 112
113 }; 113 };
114 }; 114 };
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