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Linux/scripts/dtc/include-prefixes/arm/marvell/armada-xp-gp.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm/marvell/armada-xp-gp.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm/marvell/armada-xp-gp.dts (Version linux-4.18.20)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)     
  2 /*                                                
  3  * Device Tree file for Marvell Armada XP deve    
  4  * (DB-MV784MP-GP)                                
  5  *                                                
  6  * Copyright (C) 2013-2014 Marvell                
  7  *                                                
  8  * Lior Amsalem <alior@marvell.com>                
  9  * Gregory CLEMENT <gregory.clement@free-electr    
 10  * Thomas Petazzoni <thomas.petazzoni@free-elec    
 11  *                                                
 12  * Note: this Device Tree assumes that the boo    
 13  * internal registers to 0xf1000000 (instead o    
 14  * 0xd0000000). The 0xf1000000 is the default     
 15  * DT-capable, U-Boot bootloaders provided by     
 16  * boards were delivered with an older version    
 17  * left internal registers mapped at 0xd000000    
 18  * situation, you should either update your bo    
 19  * solution) or the below Device Tree should b    
 20  */                                               
 21                                                   
 22 /dts-v1/;                                         
 23 #include <dt-bindings/gpio/gpio.h>                
 24 #include "armada-xp-mv78460.dtsi"                 
 25                                                   
 26 / {                                               
 27         model = "Marvell Armada XP Development    
 28         compatible = "marvell,axp-gp", "marvel    
 29                                                   
 30         chosen {                                  
 31                 stdout-path = "serial0:115200n    
 32         };                                        
 33                                                   
 34         memory@0 {                                
 35                 device_type = "memory";           
 36                 /*                                
 37                  * 8 GB of plug-in RAM modules    
 38                  * of memory available can be     
 39                  * bootloader according the si    
 40                  * actually plugged. However,     
 41                  * 0xF0000000 to 0xFFFFFFFF ca    
 42                  * the address range used for     
 43                  * MBus windows).                 
 44                  */                               
 45                 reg = <0x00000000 0x00000000 0    
 46                       <0x00000001 0x00000000 0    
 47         };                                        
 48                                                   
 49         cpus {                                    
 50                 pm_pic {                          
 51                         ctrl-gpios = <&gpio0 1    
 52                                      <&gpio0 1    
 53                                      <&gpio0 1    
 54                 };                                
 55         };                                        
 56                                                   
 57         soc {                                     
 58                 ranges = <MBUS_ID(0xf0, 0x01)     
 59                           MBUS_ID(0x01, 0x1d)     
 60                           MBUS_ID(0x01, 0x2f)     
 61                           MBUS_ID(0x09, 0x09)     
 62                           MBUS_ID(0x09, 0x05)     
 63                           MBUS_ID(0x0c, 0x04)     
 64                                                   
 65                 devbus-bootcs {                   
 66                         status = "okay";          
 67                                                   
 68                         /* Device Bus paramete    
 69                                                   
 70                         /* Read parameters */     
 71                         devbus,bus-width    =     
 72                         devbus,turn-off-ps  =     
 73                         devbus,badr-skew-ps =     
 74                         devbus,acc-first-ps =     
 75                         devbus,acc-next-ps  =     
 76                         devbus,rd-setup-ps  =     
 77                         devbus,rd-hold-ps   =     
 78                                                   
 79                         /* Write parameters */    
 80                         devbus,sync-enable = <    
 81                         devbus,wr-high-ps  = <    
 82                         devbus,wr-low-ps   = <    
 83                         devbus,ale-wr-ps   = <    
 84                                                   
 85                         /* NOR 16 MiB */          
 86                         nor@0 {                   
 87                                 compatible = "    
 88                                 reg = <0 0x100    
 89                                 bank-width = <    
 90                         };                        
 91                 };                                
 92                                                   
 93                 internal-regs {                   
 94                         serial@12000 {            
 95                                 status = "okay    
 96                         };                        
 97                         serial@12100 {            
 98                                 status = "okay    
 99                         };                        
100                         serial@12200 {            
101                                 status = "okay    
102                         };                        
103                         serial@12300 {            
104                                 status = "okay    
105                         };                        
106                         pinctrl {                 
107                                 pinctrl-0 = <&    
108                                 pinctrl-names     
109                                 pic_pins: pic-    
110                                         marvel    
111                                                   
112                                         marvel    
113                                 };                
114                         };                        
115                         sata@a0000 {              
116                                 nr-ports = <2>    
117                                 status = "okay    
118                         };                        
119                                                   
120                         ethernet@70000 {          
121                                 status = "okay    
122                                 phy = <&phy0>;    
123                                 phy-mode = "qs    
124                                 buffer-manager    
125                                 bm,pool-long =    
126                         };                        
127                         ethernet@74000 {          
128                                 status = "okay    
129                                 phy = <&phy1>;    
130                                 phy-mode = "qs    
131                                 buffer-manager    
132                                 bm,pool-long =    
133                         };                        
134                         ethernet@30000 {          
135                                 status = "okay    
136                                 phy = <&phy2>;    
137                                 phy-mode = "qs    
138                                 buffer-manager    
139                                 bm,pool-long =    
140                         };                        
141                         ethernet@34000 {          
142                                 status = "okay    
143                                 phy = <&phy3>;    
144                                 phy-mode = "qs    
145                                 buffer-manager    
146                                 bm,pool-long =    
147                         };                        
148                                                   
149                         /* Front-side USB slot    
150                         usb@50000 {               
151                                 status = "okay    
152                         };                        
153                                                   
154                         /* Back-side USB slot     
155                         usb@51000 {               
156                                 status = "okay    
157                         };                        
158                                                   
159                         bm@c0000 {                
160                                 status = "okay    
161                         };                        
162                                                   
163                         nand-controller@d0000     
164                                 status = "okay    
165                                                   
166                                 nand@0 {          
167                                         reg =     
168                                         label     
169                                         nand-r    
170                                         nand-o    
171                                 };                
172                         };                        
173                 };                                
174                                                   
175                 bm-bppi {                         
176                         status = "okay";          
177                 };                                
178         };                                        
179 };                                                
180                                                   
181 &pciec {                                          
182         status = "okay";                          
183                                                   
184         /*                                        
185          * The 3 slots are physically present     
186          * standard PCIe slots on the board.      
187          */                                       
188         pcie@1,0 {                                
189                 /* Port 0, Lane 0 */              
190                 status = "okay";                  
191         };                                        
192         pcie@9,0 {                                
193                 /* Port 2, Lane 0 */              
194                 status = "okay";                  
195         };                                        
196         pcie@a,0 {                                
197                 /* Port 3, Lane 0 */              
198                 status = "okay";                  
199         };                                        
200 };                                                
201                                                   
202 &mdio {                                           
203         phy0: ethernet-phy@0 {                    
204                 reg = <16>;                       
205         };                                        
206                                                   
207         phy1: ethernet-phy@1 {                    
208                 reg = <17>;                       
209         };                                        
210                                                   
211         phy2: ethernet-phy@2 {                    
212                 reg = <18>;                       
213         };                                        
214                                                   
215         phy3: ethernet-phy@3 {                    
216                 reg = <19>;                       
217         };                                        
218 };                                                
219                                                   
220 &spi0 {                                           
221         status = "okay";                          
222                                                   
223         flash@0 {                                 
224                 #address-cells = <1>;             
225                 #size-cells = <1>;                
226                 compatible = "n25q128a13", "je    
227                 reg = <0>; /* Chip select 0 */    
228                 spi-max-frequency = <108000000    
229         };                                        
230 };                                                
                                                      

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