1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Marvell Armada 3 * Device Tree Include file for Marvell Armada XP family SoC
4 * 4 *
5 * Copyright (C) 2012 Marvell 5 * Copyright (C) 2012 Marvell
6 * 6 *
7 * Lior Amsalem <alior@marvell.com> 7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electr 8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-elec 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * 11 *
12 * Contains definitions specific to the Armada 12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs. 13 * common to all Armada SoCs.
14 */ 14 */
15 15
16 #include "armada-370-xp.dtsi" 16 #include "armada-370-xp.dtsi"
17 17
18 / { 18 / {
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 model = "Marvell Armada XP family SoC" 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marv 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 aliases { 25 aliases {
26 serial2 = &uart2; 26 serial2 = &uart2;
27 serial3 = &uart3; 27 serial3 = &uart3;
28 }; 28 };
29 29
30 soc { 30 soc {
31 compatible = "marvell,armadaxp 31 compatible = "marvell,armadaxp-mbus", "simple-bus";
32 32
33 bootrom { 33 bootrom {
34 compatible = "marvell, 34 compatible = "marvell,bootrom";
35 reg = <MBUS_ID(0x01, 0 35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
36 }; 36 };
37 37
38 internal-regs { 38 internal-regs {
39 sdramc: sdramc@1400 { 39 sdramc: sdramc@1400 {
40 compatible = " 40 compatible = "marvell,armada-xp-sdram-controller";
41 reg = <0x1400 41 reg = <0x1400 0x500>;
42 }; 42 };
43 43
44 L2: l2-cache@8000 { 44 L2: l2-cache@8000 {
45 compatible = " 45 compatible = "marvell,aurora-system-cache";
46 reg = <0x08000 46 reg = <0x08000 0x1000>;
47 cache-id-part 47 cache-id-part = <0x100>;
48 cache-level = 48 cache-level = <2>;
49 cache-unified; 49 cache-unified;
50 wt-override; 50 wt-override;
51 }; 51 };
52 52
53 uart2: serial@12200 { 53 uart2: serial@12200 {
54 compatible = " 54 compatible = "snps,dw-apb-uart";
55 pinctrl-0 = <& 55 pinctrl-0 = <&uart2_pins>;
56 pinctrl-names 56 pinctrl-names = "default";
57 reg = <0x12200 57 reg = <0x12200 0x100>;
58 reg-shift = <2 58 reg-shift = <2>;
59 interrupts = < 59 interrupts = <43>;
60 reg-io-width = 60 reg-io-width = <1>;
61 clocks = <&cor 61 clocks = <&coreclk 0>;
62 status = "disa 62 status = "disabled";
63 }; 63 };
64 64
65 uart3: serial@12300 { 65 uart3: serial@12300 {
66 compatible = " 66 compatible = "snps,dw-apb-uart";
67 pinctrl-0 = <& 67 pinctrl-0 = <&uart3_pins>;
68 pinctrl-names 68 pinctrl-names = "default";
69 reg = <0x12300 69 reg = <0x12300 0x100>;
70 reg-shift = <2 70 reg-shift = <2>;
71 interrupts = < 71 interrupts = <44>;
72 reg-io-width = 72 reg-io-width = <1>;
73 clocks = <&cor 73 clocks = <&coreclk 0>;
74 status = "disa 74 status = "disabled";
75 }; 75 };
76 76
77 systemc: system-contro 77 systemc: system-controller@18200 {
78 compatible = " 78 compatible = "marvell,armada-370-xp-system-controller";
79 reg = <0x18200 79 reg = <0x18200 0x500>;
80 }; 80 };
81 81
82 gateclk: clock-gating- 82 gateclk: clock-gating-control@18220 {
83 compatible = " 83 compatible = "marvell,armada-xp-gating-clock";
84 reg = <0x18220 84 reg = <0x18220 0x4>;
85 clocks = <&cor 85 clocks = <&coreclk 0>;
86 #clock-cells = 86 #clock-cells = <1>;
87 }; 87 };
88 88
89 coreclk: mvebu-sar@182 89 coreclk: mvebu-sar@18230 {
90 compatible = " 90 compatible = "marvell,armada-xp-core-clock";
91 reg = <0x18230 91 reg = <0x18230 0x08>;
92 #clock-cells = 92 #clock-cells = <1>;
93 }; 93 };
94 94
95 thermal: thermal@182b0 95 thermal: thermal@182b0 {
96 compatible = " 96 compatible = "marvell,armadaxp-thermal";
97 reg = <0x182b0 97 reg = <0x182b0 0x4
98 0x184d 98 0x184d0 0x4>;
99 status = "okay 99 status = "okay";
100 }; 100 };
101 101
102 cpuclk: clock-complex@ 102 cpuclk: clock-complex@18700 {
103 #clock-cells = 103 #clock-cells = <1>;
104 compatible = " 104 compatible = "marvell,armada-xp-cpu-clock";
105 reg = <0x18700 105 reg = <0x18700 0x24>, <0x1c054 0x10>;
106 clocks = <&cor 106 clocks = <&coreclk 1>;
107 }; 107 };
108 108
109 cpu-config@21000 { 109 cpu-config@21000 {
110 compatible = " 110 compatible = "marvell,armada-xp-cpu-config";
111 reg = <0x21000 111 reg = <0x21000 0x8>;
112 }; 112 };
113 113
114 eth2: ethernet@30000 { 114 eth2: ethernet@30000 {
115 compatible = " 115 compatible = "marvell,armada-xp-neta";
116 reg = <0x30000 116 reg = <0x30000 0x4000>;
117 interrupts = < 117 interrupts = <12>;
118 clocks = <&gat 118 clocks = <&gateclk 2>;
119 status = "disa 119 status = "disabled";
120 }; 120 };
121 121
122 usb2: usb@52000 { 122 usb2: usb@52000 {
123 compatible = " 123 compatible = "marvell,orion-ehci";
124 reg = <0x52000 124 reg = <0x52000 0x500>;
125 interrupts = < 125 interrupts = <47>;
126 clocks = <&gat 126 clocks = <&gateclk 20>;
127 status = "disa 127 status = "disabled";
128 }; 128 };
129 129
130 xor1: xor@60900 { 130 xor1: xor@60900 {
131 compatible = " 131 compatible = "marvell,orion-xor";
132 reg = <0x60900 132 reg = <0x60900 0x100
133 0x60b00 133 0x60b00 0x100>;
134 clocks = <&gat 134 clocks = <&gateclk 22>;
135 status = "okay 135 status = "okay";
136 136
137 xor10 { 137 xor10 {
138 interr 138 interrupts = <51>;
139 dmacap 139 dmacap,memcpy;
140 dmacap 140 dmacap,xor;
141 }; 141 };
142 xor11 { 142 xor11 {
143 interr 143 interrupts = <52>;
144 dmacap 144 dmacap,memcpy;
145 dmacap 145 dmacap,xor;
146 dmacap 146 dmacap,memset;
147 }; 147 };
148 }; 148 };
149 149
150 ethernet@70000 { 150 ethernet@70000 {
151 compatible = " 151 compatible = "marvell,armada-xp-neta";
152 }; 152 };
153 153
154 ethernet@74000 { 154 ethernet@74000 {
155 compatible = " 155 compatible = "marvell,armada-xp-neta";
156 }; 156 };
157 157
158 cesa: crypto@90000 { 158 cesa: crypto@90000 {
159 compatible = " 159 compatible = "marvell,armada-xp-crypto";
160 reg = <0x90000 160 reg = <0x90000 0x10000>;
161 reg-names = "r 161 reg-names = "regs";
162 interrupts = < 162 interrupts = <48>, <49>;
163 clocks = <&gat 163 clocks = <&gateclk 23>, <&gateclk 23>;
164 clock-names = 164 clock-names = "cesa0", "cesa1";
165 marvell,crypto 165 marvell,crypto-srams = <&crypto_sram0>,
166 166 <&crypto_sram1>;
167 marvell,crypto 167 marvell,crypto-sram-size = <0x800>;
168 }; 168 };
169 169
170 bm: bm@c0000 { 170 bm: bm@c0000 {
171 compatible = " 171 compatible = "marvell,armada-380-neta-bm";
172 reg = <0xc0000 172 reg = <0xc0000 0xac>;
173 clocks = <&gat 173 clocks = <&gateclk 13>;
174 internal-mem = 174 internal-mem = <&bm_bppi>;
175 status = "disa 175 status = "disabled";
176 }; 176 };
177 177
178 xor0: xor@f0900 { 178 xor0: xor@f0900 {
179 compatible = " 179 compatible = "marvell,orion-xor";
180 reg = <0xF0900 180 reg = <0xF0900 0x100
181 0xF0B00 181 0xF0B00 0x100>;
182 clocks = <&gat 182 clocks = <&gateclk 28>;
183 status = "okay 183 status = "okay";
184 184
185 xor00 { 185 xor00 {
186 interr 186 interrupts = <94>;
187 dmacap 187 dmacap,memcpy;
188 dmacap 188 dmacap,xor;
189 }; 189 };
190 xor01 { 190 xor01 {
191 interr 191 interrupts = <95>;
192 dmacap 192 dmacap,memcpy;
193 dmacap 193 dmacap,xor;
194 dmacap 194 dmacap,memset;
195 }; 195 };
196 }; 196 };
197 }; 197 };
198 198
199 crypto_sram0: sa-sram0 { 199 crypto_sram0: sa-sram0 {
200 compatible = "mmio-sra 200 compatible = "mmio-sram";
201 reg = <MBUS_ID(0x09, 0 201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
202 clocks = <&gateclk 23> 202 clocks = <&gateclk 23>;
203 #address-cells = <1>; 203 #address-cells = <1>;
204 #size-cells = <1>; 204 #size-cells = <1>;
205 ranges = <0 MBUS_ID(0x 205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
206 }; 206 };
207 207
208 crypto_sram1: sa-sram1 { 208 crypto_sram1: sa-sram1 {
209 compatible = "mmio-sra 209 compatible = "mmio-sram";
210 reg = <MBUS_ID(0x09, 0 210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
211 clocks = <&gateclk 23> 211 clocks = <&gateclk 23>;
212 #address-cells = <1>; 212 #address-cells = <1>;
213 #size-cells = <1>; 213 #size-cells = <1>;
214 ranges = <0 MBUS_ID(0x 214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
215 }; 215 };
216 216
217 bm_bppi: bm-bppi { 217 bm_bppi: bm-bppi {
218 compatible = "mmio-sra 218 compatible = "mmio-sram";
219 reg = <MBUS_ID(0x0c, 0 219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x 220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 #address-cells = <1>; 221 #address-cells = <1>;
222 #size-cells = <1>; 222 #size-cells = <1>;
223 clocks = <&gateclk 13> 223 clocks = <&gateclk 13>;
224 no-memory-wc; 224 no-memory-wc;
225 status = "disabled"; 225 status = "disabled";
226 }; 226 };
227 }; 227 };
228 228
229 clocks { 229 clocks {
230 /* 25 MHz reference crystal */ 230 /* 25 MHz reference crystal */
231 refclk: oscillator { 231 refclk: oscillator {
232 compatible = "fixed-cl 232 compatible = "fixed-clock";
233 #clock-cells = <0>; 233 #clock-cells = <0>;
234 clock-frequency = <250 234 clock-frequency = <25000000>;
235 }; 235 };
236 }; 236 };
237 }; 237 };
238 238
239 &i2c0 { 239 &i2c0 {
240 compatible = "marvell,mv78230-i2c", "m 240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
241 reg = <0x11000 0x100>; 241 reg = <0x11000 0x100>;
242 }; 242 };
243 243
244 &i2c1 { 244 &i2c1 {
245 compatible = "marvell,mv78230-i2c", "m 245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x100>; 246 reg = <0x11100 0x100>;
247 }; 247 };
248 248
249 &mpic { 249 &mpic {
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
251 }; 251 };
252 252
253 &timer { 253 &timer {
254 compatible = "marvell,armada-xp-timer" 254 compatible = "marvell,armada-xp-timer";
255 clocks = <&coreclk 2>, <&refclk>; 255 clocks = <&coreclk 2>, <&refclk>;
256 clock-names = "nbclk", "fixed"; 256 clock-names = "nbclk", "fixed";
257 }; 257 };
258 258
259 &watchdog { 259 &watchdog {
260 compatible = "marvell,armada-xp-wdt"; 260 compatible = "marvell,armada-xp-wdt";
261 clocks = <&coreclk 2>, <&refclk>; 261 clocks = <&coreclk 2>, <&refclk>;
262 clock-names = "nbclk", "fixed"; 262 clock-names = "nbclk", "fixed";
263 interrupts = <93>, <38>; 263 interrupts = <93>, <38>;
264 }; 264 };
265 265
266 &cpurst { 266 &cpurst {
267 reg = <0x20800 0x20>; 267 reg = <0x20800 0x20>;
268 }; 268 };
269 269
270 &usb0 { 270 &usb0 {
271 clocks = <&gateclk 18>; 271 clocks = <&gateclk 18>;
272 }; 272 };
273 273
274 &usb1 { 274 &usb1 {
275 clocks = <&gateclk 19>; 275 clocks = <&gateclk 19>;
276 }; 276 };
277 277
278 &pinctrl { 278 &pinctrl {
279 ge0_gmii_pins: ge0-gmii-pins { 279 ge0_gmii_pins: ge0-gmii-pins {
280 marvell,pins = 280 marvell,pins =
281 "mpp0", "mpp1", "mpp2", 281 "mpp0", "mpp1", "mpp2", "mpp3",
282 "mpp4", "mpp5", "mpp6", 282 "mpp4", "mpp5", "mpp6", "mpp7",
283 "mpp8", "mpp9", "mpp10" 283 "mpp8", "mpp9", "mpp10", "mpp11",
284 "mpp12", "mpp13", "mpp14" 284 "mpp12", "mpp13", "mpp14", "mpp15",
285 "mpp16", "mpp17", "mpp18" 285 "mpp16", "mpp17", "mpp18", "mpp19",
286 "mpp20", "mpp21", "mpp22" 286 "mpp20", "mpp21", "mpp22", "mpp23";
287 marvell,function = "ge0"; 287 marvell,function = "ge0";
288 }; 288 };
289 289
290 ge0_rgmii_pins: ge0-rgmii-pins { 290 ge0_rgmii_pins: ge0-rgmii-pins {
291 marvell,pins = 291 marvell,pins =
292 "mpp0", "mpp1", "mpp2", " 292 "mpp0", "mpp1", "mpp2", "mpp3",
293 "mpp4", "mpp5", "mpp6", " 293 "mpp4", "mpp5", "mpp6", "mpp7",
294 "mpp8", "mpp9", "mpp10", 294 "mpp8", "mpp9", "mpp10", "mpp11";
295 marvell,function = "ge0"; 295 marvell,function = "ge0";
296 }; 296 };
297 297
298 ge1_rgmii_pins: ge1-rgmii-pins { 298 ge1_rgmii_pins: ge1-rgmii-pins {
299 marvell,pins = 299 marvell,pins =
300 "mpp12", "mpp13", "mpp14" 300 "mpp12", "mpp13", "mpp14", "mpp15",
301 "mpp16", "mpp17", "mpp18" 301 "mpp16", "mpp17", "mpp18", "mpp19",
302 "mpp20", "mpp21", "mpp22" 302 "mpp20", "mpp21", "mpp22", "mpp23";
303 marvell,function = "ge1"; 303 marvell,function = "ge1";
304 }; 304 };
305 305
306 sdio_pins: sdio-pins { 306 sdio_pins: sdio-pins {
307 marvell,pins = "mpp30", "mpp31 307 marvell,pins = "mpp30", "mpp31", "mpp32",
308 "mpp33", "mpp34 308 "mpp33", "mpp34", "mpp35";
309 marvell,function = "sd0"; 309 marvell,function = "sd0";
310 }; 310 };
311 311
312 spi0_pins: spi0-pins { 312 spi0_pins: spi0-pins {
313 marvell,pins = "mpp36", "mpp37 313 marvell,pins = "mpp36", "mpp37",
314 "mpp38", "mpp39 314 "mpp38", "mpp39";
315 marvell,function = "spi0"; 315 marvell,function = "spi0";
316 }; 316 };
317 317
318 spi1_pins: spi1-pins { 318 spi1_pins: spi1-pins {
319 marvell,pins = "mpp13", "mpp14 319 marvell,pins = "mpp13", "mpp14",
320 "mpp16", "mpp17 320 "mpp16", "mpp17";
321 marvell,function = "spi1"; 321 marvell,function = "spi1";
322 }; 322 };
323 323
324 uart2_pins: uart2-pins { 324 uart2_pins: uart2-pins {
325 marvell,pins = "mpp42", "mpp43 325 marvell,pins = "mpp42", "mpp43";
326 marvell,function = "uart2"; 326 marvell,function = "uart2";
327 }; 327 };
328 328
329 uart3_pins: uart3-pins { 329 uart3_pins: uart3-pins {
330 marvell,pins = "mpp44", "mpp45 330 marvell,pins = "mpp44", "mpp45";
331 marvell,function = "uart3"; 331 marvell,function = "uart3";
332 }; 332 };
333 }; 333 };
334 334
335 &spi0 { 335 &spi0 {
336 compatible = "marvell,armada-xp-spi", 336 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
337 pinctrl-0 = <&spi0_pins>; 337 pinctrl-0 = <&spi0_pins>;
338 pinctrl-names = "default"; 338 pinctrl-names = "default";
339 }; 339 };
340 340
341 &spi1 { 341 &spi1 {
342 compatible = "marvell,armada-xp-spi", 342 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343 pinctrl-0 = <&spi1_pins>; 343 pinctrl-0 = <&spi1_pins>;
344 pinctrl-names = "default"; 344 pinctrl-names = "default";
345 }; 345 };
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