1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4
5 #define MBUS_ID(target,attributes) (((target)
6
7 / {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "marvell,kirkwood";
11 interrupt-parent = <&intc>;
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 device_type = "cpu";
19 compatible = "marvell,
20 reg = <0>;
21 clocks = <&core_clk 1>
22 clock-names = "cpu_clk
23 };
24 };
25
26 aliases {
27 gpio0 = &gpio0;
28 gpio1 = &gpio1;
29 i2c0 = &i2c0;
30 };
31
32 mbus@f1000000 {
33 compatible = "marvell,kirkwood
34 #address-cells = <2>;
35 #size-cells = <1>;
36 /* If a board file needs to ch
37 ranges = <MBUS_ID(0xf0, 0x01)
38 MBUS_ID(0x01, 0x2f)
39 MBUS_ID(0x03, 0x01)
40 >;
41 controller = <&mbusc>;
42 pcie-mem-aperture = <0xe000000
43 pcie-io-aperture = <0xf200000
44
45 nand: nand@12f {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 cle = <0>;
49 ale = <1>;
50 bank-width = <1>;
51 compatible = "marvell,
52 reg = <MBUS_ID(0x01, 0
53 chip-delay = <25>;
54 /* set partition map a
55 clocks = <&gate_clk 7>
56 pinctrl-0 = <&pmx_nand
57 pinctrl-names = "defau
58 status = "disabled";
59 };
60
61 crypto_sram: sa-sram@301 {
62 compatible = "mmio-sra
63 reg = <MBUS_ID(0x03, 0
64 clocks = <&gate_clk 17
65 #address-cells = <1>;
66 #size-cells = <1>;
67 };
68 };
69
70 ocp@f1000000 {
71 compatible = "simple-bus";
72 ranges = <0x00000000 0xf100000
73 #address-cells = <1>;
74 #size-cells = <1>;
75
76 pinctrl: pin-controller@10000
77 /* set compatible prop
78 reg = <0x10000 0x20>;
79
80 pmx_ge1: pmx-ge1 {
81 marvell,pins =
82
83
84 marvell,functi
85 };
86
87 pmx_nand: pmx-nand {
88 marvell,pins =
89
90 marvell,functi
91 };
92
93 /*
94 * Default SPI0 pinctr
95 * overwrite marvell,p
96 */
97 pmx_spi: pmx-spi {
98 marvell,pins =
99 marvell,functi
100 };
101
102 pmx_twsi0: pmx-twsi0 {
103 marvell,pins =
104 marvell,functi
105 };
106
107 /*
108 * Default UART pinctr
109 * overwrite marvell,p
110 */
111 pmx_uart0: pmx-uart0 {
112 marvell,pins =
113 marvell,functi
114 };
115
116 pmx_uart1: pmx-uart1 {
117 marvell,pins =
118 marvell,functi
119 };
120 };
121
122 core_clk: core-clocks@10030 {
123 compatible = "marvell,
124 reg = <0x10030 0x4>;
125 #clock-cells = <1>;
126 };
127
128 spi0: spi@10600 {
129 compatible = "marvell,
130 #address-cells = <1>;
131 #size-cells = <0>;
132 cell-index = <0>;
133 interrupts = <23>;
134 reg = <0x10600 0x28>;
135 clocks = <&gate_clk 7>
136 pinctrl-0 = <&pmx_spi>
137 pinctrl-names = "defau
138 status = "disabled";
139 };
140
141 gpio0: gpio@10100 {
142 compatible = "marvell,
143 #gpio-cells = <2>;
144 gpio-controller;
145 reg = <0x10100 0x40>;
146 ngpios = <32>;
147 interrupt-controller;
148 #interrupt-cells = <2>
149 interrupts = <35>, <36
150 clocks = <&gate_clk 7>
151 };
152
153 gpio1: gpio@10140 {
154 compatible = "marvell,
155 #gpio-cells = <2>;
156 gpio-controller;
157 reg = <0x10140 0x40>;
158 ngpios = <18>;
159 interrupt-controller;
160 #interrupt-cells = <2>
161 interrupts = <39>, <40
162 clocks = <&gate_clk 7>
163 };
164
165 i2c0: i2c@11000 {
166 compatible = "marvell,
167 reg = <0x11000 0x20>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170 interrupts = <29>;
171 clock-frequency = <100
172 clocks = <&gate_clk 7>
173 pinctrl-0 = <&pmx_twsi
174 pinctrl-names = "defau
175 status = "disabled";
176 };
177
178 uart0: serial@12000 {
179 compatible = "ns16550a
180 reg = <0x12000 0x100>;
181 reg-shift = <2>;
182 interrupts = <33>;
183 clocks = <&gate_clk 7>
184 pinctrl-0 = <&pmx_uart
185 pinctrl-names = "defau
186 status = "disabled";
187 };
188
189 uart1: serial@12100 {
190 compatible = "ns16550a
191 reg = <0x12100 0x100>;
192 reg-shift = <2>;
193 interrupts = <34>;
194 clocks = <&gate_clk 7>
195 pinctrl-0 = <&pmx_uart
196 pinctrl-names = "defau
197 status = "disabled";
198 };
199
200 mbusc: mbus-controller@20000 {
201 compatible = "marvell,
202 reg = <0x20000 0x80>,
203 };
204
205 sysc: system-controller@20000
206 compatible = "marvell,
207 reg = <0x20000 0x120>;
208 };
209
210 bridge_intc: bridge-interrupt-
211 compatible = "marvell,
212 interrupt-controller;
213 #interrupt-cells = <1>
214 reg = <0x20110 0x8>;
215 interrupts = <1>;
216 marvell,#interrupts =
217 };
218
219 gate_clk: clock-gating-control
220 compatible = "marvell,
221 reg = <0x2011c 0x4>;
222 clocks = <&core_clk 0>
223 #clock-cells = <1>;
224 };
225
226 l2: l2-cache@20128 {
227 compatible = "marvell,
228 reg = <0x20128 0x4>;
229 };
230
231 intc: interrupt-controller@202
232 compatible = "marvell,
233 interrupt-controller;
234 #interrupt-cells = <1>
235 reg = <0x20200 0x10>,
236 };
237
238 timer: timer@20300 {
239 compatible = "marvell,
240 reg = <0x20300 0x20>;
241 interrupt-parent = <&b
242 interrupts = <1>, <2>;
243 clocks = <&core_clk 0>
244 };
245
246 wdt: watchdog-timer@20300 {
247 compatible = "marvell,
248 reg = <0x20300 0x28>,
249 interrupt-parent = <&b
250 interrupts = <3>;
251 clocks = <&gate_clk 7>
252 status = "okay";
253 };
254
255 cesa: crypto@30000 {
256 compatible = "marvell,
257 reg = <0x30000 0x10000
258 reg-names = "regs";
259 interrupts = <22>;
260 clocks = <&gate_clk 17
261 marvell,crypto-srams =
262 marvell,crypto-sram-si
263 status = "okay";
264 };
265
266 usb0: ehci@50000 {
267 compatible = "marvell,
268 reg = <0x50000 0x1000>
269 interrupts = <19>;
270 clocks = <&gate_clk 3>
271 status = "okay";
272 };
273
274 dma0: xor@60800 {
275 compatible = "marvell,
276 reg = <0x60800 0x100
277 0x60A00 0x100>;
278 status = "okay";
279 clocks = <&gate_clk 8>
280
281 xor00 {
282 interrupts = <
283 dmacap,memcpy;
284 dmacap,xor;
285 };
286 xor01 {
287 interrupts = <
288 dmacap,memcpy;
289 dmacap,xor;
290 dmacap,memset;
291 };
292 };
293
294 dma1: xor@60900 {
295 compatible = "marvell,
296 reg = <0x60900 0x100
297 0x60B00 0x100>;
298 status = "okay";
299 clocks = <&gate_clk 16
300
301 xor00 {
302 interrupts = <
303 dmacap,memcpy;
304 dmacap,xor;
305 };
306 xor01 {
307 interrupts = <
308 dmacap,memcpy;
309 dmacap,xor;
310 dmacap,memset;
311 };
312 };
313
314 eth0: ethernet-controller@7200
315 compatible = "marvell,
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x72000 0x4000>
319 clocks = <&gate_clk 0>
320 marvell,tx-checksum-li
321 status = "disabled";
322
323 eth0port: ethernet0-po
324 compatible = "
325 reg = <0>;
326 interrupts = <
327 /* overwrite M
328 local-mac-addr
329 /* set phy-han
330 };
331 };
332
333 mdio: mdio-bus@72004 {
334 compatible = "marvell,
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <0x72004 0x84>;
338 interrupts = <46>;
339 clocks = <&gate_clk 0>
340 status = "disabled";
341
342 /* add phy nodes in bo
343 };
344
345 eth1: ethernet-controller@7600
346 compatible = "marvell,
347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <0x76000 0x4000>
350 clocks = <&gate_clk 19
351 marvell,tx-checksum-li
352 pinctrl-0 = <&pmx_ge1>
353 pinctrl-names = "defau
354 status = "disabled";
355
356 eth1port: ethernet1-po
357 compatible = "
358 reg = <0>;
359 interrupts = <
360 /* overwrite M
361 local-mac-addr
362 /* set phy-han
363 };
364 };
365
366 sata_phy0: sata-phy@82000 {
367 compatible = "marvell,
368 reg = <0x82000 0x0334>
369 clocks = <&gate_clk 14
370 clock-names = "sata";
371 #phy-cells = <0>;
372 status = "okay";
373 };
374
375 sata_phy1: sata-phy@84000 {
376 compatible = "marvell,
377 reg = <0x84000 0x0334>
378 clocks = <&gate_clk 15
379 clock-names = "sata";
380 #phy-cells = <0>;
381 status = "okay";
382 };
383
384 audio0: audio-controller@a0000
385 compatible = "marvell,
386 #sound-dai-cells = <0>
387 reg = <0xa0000 0x2210>
388 interrupts = <24>;
389 clocks = <&gate_clk 9>
390 clock-names = "interna
391 status = "disabled";
392 };
393 };
394 };
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