1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Marvell Technology Grou
4 * Author: Haojian Zhuang <haojian.zhuang@marv
5 */
6
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
9 #include <dt-bindings/clock/marvell,mmp2-audio
10
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 i2c0 = &twsi1;
21 i2c1 = &twsi2;
22 };
23
24 soc {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 interrupt-parent = <&intc>;
29 ranges;
30
31 L2: l2-cache {
32 compatible = "marvell,
33 marvell,tauros2-cache-
34 };
35
36 axi@d4200000 { /* AXI */
37 compatible = "mrvl,axi
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0xd4200000 0x00
41 ranges;
42
43 gpu: gpu@d420d000 {
44 compatible = "
45 reg = <0xd420d
46 interrupts = <
47 status = "disa
48 clocks = <&soc
49 <&soc
50 clock-names =
51 power-domains
52 };
53
54 intc: interrupt-contro
55 compatible = "
56 interrupt-cont
57 #interrupt-cel
58 reg = <0xd4282
59 mrvl,intc-nr-i
60 };
61
62 intcmux4: interrupt-co
63 compatible = "
64 interrupts = <
65 interrupt-cont
66 #interrupt-cel
67 reg = <0x150 0
68 reg-names = "m
69 mrvl,intc-nr-i
70 };
71
72 intcmux5: interrupt-co
73 compatible = "
74 interrupts = <
75 interrupt-cont
76 #interrupt-cel
77 reg = <0x154 0
78 reg-names = "m
79 mrvl,intc-nr-i
80 mrvl,clr-mfp-i
81 };
82
83 intcmux9: interrupt-co
84 compatible = "
85 interrupts = <
86 interrupt-cont
87 #interrupt-cel
88 reg = <0x180 0
89 reg-names = "m
90 mrvl,intc-nr-i
91 };
92
93 intcmux17: interrupt-c
94 compatible = "
95 interrupts = <
96 interrupt-cont
97 #interrupt-cel
98 reg = <0x158 0
99 reg-names = "m
100 mrvl,intc-nr-i
101 };
102
103 intcmux35: interrupt-c
104 compatible = "
105 interrupts = <
106 interrupt-cont
107 #interrupt-cel
108 reg = <0x15c 0
109 reg-names = "m
110 mrvl,intc-nr-i
111 };
112
113 intcmux51: interrupt-c
114 compatible = "
115 interrupts = <
116 interrupt-cont
117 #interrupt-cel
118 reg = <0x160 0
119 reg-names = "m
120 mrvl,intc-nr-i
121 };
122
123 intcmux55: interrupt-c
124 compatible = "
125 interrupts = <
126 interrupt-cont
127 #interrupt-cel
128 reg = <0x188 0
129 reg-names = "m
130 mrvl,intc-nr-i
131 };
132
133 usb_phy0: usb-phy@d420
134 compatible = "
135 reg = <0xd4207
136 #phy-cells = <
137 status = "disa
138 };
139
140 usb_otg0: usb-otg@d420
141 compatible = "
142 reg = <0xd4208
143 interrupts = <
144 clocks = <&soc
145 clock-names =
146 phys = <&usb_p
147 phy-names = "u
148 status = "disa
149 };
150
151 mmc1: mmc@d4280000 {
152 compatible = "
153 reg = <0xd4280
154 clocks = <&soc
155 clock-names =
156 interrupts = <
157 status = "disa
158 };
159
160 mmc2: mmc@d4280800 {
161 compatible = "
162 reg = <0xd4280
163 clocks = <&soc
164 clock-names =
165 interrupts = <
166 status = "disa
167 };
168
169 mmc3: mmc@d4281000 {
170 compatible = "
171 reg = <0xd4281
172 clocks = <&soc
173 clock-names =
174 interrupts = <
175 status = "disa
176 };
177
178 mmc4: mmc@d4281800 {
179 compatible = "
180 reg = <0xd4281
181 clocks = <&soc
182 clock-names =
183 interrupts = <
184 status = "disa
185 };
186
187 camera0: camera@d420a0
188 compatible = "
189 reg = <0xd420a
190 interrupts = <
191 clocks = <&soc
192 clock-names =
193 #clock-cells =
194 clock-output-n
195 status = "disa
196 };
197
198 camera1: camera@d420a8
199 compatible = "
200 reg = <0xd420a
201 interrupts = <
202 clocks = <&soc
203 clock-names =
204 #clock-cells =
205 clock-output-n
206 status = "disa
207 };
208
209 adma0: dma-controller@
210 compatible = "
211 reg = <0xd42a0
212 interrupts = <
213 #dma-cells = <
214 asram = <&asra
215 iram = <&asram
216 status = "disa
217 };
218
219 adma1: dma-controller@
220 compatible = "
221 reg = <0xd42a0
222 interrupts = <
223 #dma-cells = <
224 status = "disa
225 };
226
227 audio_clk: clocks@d42a
228 compatible = "
229 reg = <0xd42a0
230 clock-names =
231 clocks = <&soc
232 <&soc
233 <&soc
234 <&soc
235 power-domains
236 #clock-cells =
237 status = "disa
238 };
239
240 sspa0: audio-controlle
241 compatible = "
242 reg = <0xd42a0
243 <0xd42a0
244 interrupts = <
245 clock-names =
246 clocks = <&soc
247 <&aud
248 power-domains
249 #sound-dai-cel
250 status = "disa
251 };
252
253 sspa1: audio-controlle
254 compatible = "
255 reg = <0xd42a0
256 <0xd42a0
257 interrupts = <
258 clock-names =
259 clocks = <&soc
260 <&aud
261 power-domains
262 #sound-dai-cel
263 status = "disa
264 };
265 };
266
267 apb@d4000000 { /* APB */
268 compatible = "mrvl,apb
269 #address-cells = <1>;
270 #size-cells = <1>;
271 reg = <0xd4000000 0x00
272 ranges;
273
274 dma-controller@d400000
275 compatible = "
276 reg = <0xd4000
277 interrupts = <
278 /* For backwar
279 #dma-channels
280 dma-channels =
281 status = "disa
282 };
283
284 timer0: timer@d4014000
285 compatible = "
286 reg = <0xd4014
287 interrupts = <
288 clocks = <&soc
289 };
290
291 uart1: serial@d4030000
292 compatible = "
293 reg = <0xd4030
294 interrupts = <
295 clocks = <&soc
296 resets = <&soc
297 reg-shift = <2
298 status = "disa
299 };
300
301 uart2: serial@d4017000
302 compatible = "
303 reg = <0xd4017
304 interrupts = <
305 clocks = <&soc
306 resets = <&soc
307 reg-shift = <2
308 status = "disa
309 };
310
311 uart3: serial@d4018000
312 compatible = "
313 reg = <0xd4018
314 interrupts = <
315 clocks = <&soc
316 resets = <&soc
317 reg-shift = <2
318 status = "disa
319 };
320
321 uart4: serial@d4016000
322 compatible = "
323 reg = <0xd4016
324 interrupts = <
325 clocks = <&soc
326 resets = <&soc
327 reg-shift = <2
328 status = "disa
329 };
330
331 gpio: gpio@d4019000 {
332 compatible = "
333 #address-cells
334 #size-cells =
335 reg = <0xd4019
336 gpio-controlle
337 #gpio-cells =
338 interrupts = <
339 interrupt-name
340 clocks = <&soc
341 resets = <&soc
342 interrupt-cont
343 #interrupt-cel
344 ranges;
345
346 gcb0: gpio@d40
347 reg =
348 };
349
350 gcb1: gpio@d40
351 reg =
352 };
353
354 gcb2: gpio@d40
355 reg =
356 };
357
358 gcb3: gpio@d40
359 reg =
360 };
361
362 gcb4: gpio@d40
363 reg =
364 };
365
366 gcb5: gpio@d40
367 reg =
368 };
369 };
370
371 twsi1: i2c@d4011000 {
372 compatible = "
373 reg = <0xd4011
374 interrupts = <
375 clocks = <&soc
376 resets = <&soc
377 #address-cells
378 #size-cells =
379 mrvl,i2c-fast-
380 status = "disa
381 };
382
383 twsi2: i2c@d4031000 {
384 compatible = "
385 reg = <0xd4031
386 interrupt-pare
387 interrupts = <
388 clocks = <&soc
389 resets = <&soc
390 #address-cells
391 #size-cells =
392 status = "disa
393 };
394
395 twsi3: i2c@d4032000 {
396 compatible = "
397 reg = <0xd4032
398 interrupt-pare
399 interrupts = <
400 clocks = <&soc
401 resets = <&soc
402 #address-cells
403 #size-cells =
404 status = "disa
405 };
406
407 twsi4: i2c@d4033000 {
408 compatible = "
409 reg = <0xd4033
410 interrupt-pare
411 interrupts = <
412 clocks = <&soc
413 resets = <&soc
414 #address-cells
415 #size-cells =
416 status = "disa
417 };
418
419
420 twsi5: i2c@d4033800 {
421 compatible = "
422 reg = <0xd4033
423 interrupt-pare
424 interrupts = <
425 clocks = <&soc
426 resets = <&soc
427 #address-cells
428 #size-cells =
429 status = "disa
430 };
431
432 twsi6: i2c@d4034000 {
433 compatible = "
434 reg = <0xd4034
435 interrupt-pare
436 interrupts = <
437 clocks = <&soc
438 resets = <&soc
439 #address-cells
440 #size-cells =
441 status = "disa
442 };
443
444 rtc: rtc@d4010000 {
445 compatible = "
446 reg = <0xd4010
447 interrupts = <
448 interrupt-name
449 interrupt-pare
450 clocks = <&soc
451 resets = <&soc
452 status = "disa
453 };
454
455 ssp1: spi@d4035000 {
456 compatible = "
457 reg = <0xd4035
458 clocks = <&soc
459 interrupts = <
460 #address-cells
461 #size-cells =
462 status = "disa
463 };
464
465 ssp2: spi@d4036000 {
466 compatible = "
467 reg = <0xd4036
468 clocks = <&soc
469 interrupts = <
470 #address-cells
471 #size-cells =
472 status = "disa
473 };
474
475 ssp3: spi@d4037000 {
476 compatible = "
477 reg = <0xd4037
478 clocks = <&soc
479 interrupts = <
480 #address-cells
481 #size-cells =
482 status = "disa
483 };
484
485 ssp4: spi@d4039000 {
486 compatible = "
487 reg = <0xd4039
488 clocks = <&soc
489 interrupts = <
490 #address-cells
491 #size-cells =
492 status = "disa
493 };
494 };
495
496 asram: sram@e0000000 {
497 compatible = "mmio-sra
498 reg = <0xe0000000 0x10
499 ranges = <0 0xe0000000
500 #address-cells = <1>;
501 #size-cells = <1>;
502 status = "disabled";
503 };
504
505 soc_clocks: clocks {
506 compatible = "marvell,
507 reg = <0xd4050000 0x20
508 <0xd4282800 0x40
509 <0xd4015000 0x10
510 reg-names = "mpmu", "a
511 #clock-cells = <1>;
512 #reset-cells = <1>;
513 #power-domain-cells =
514 };
515 };
516 };
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