1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 *
6 */
7
8 /dts-v1/;
9 #include <dt-bindings/power/mt7623a-power.h>
10 #include "mt7623.dtsi"
11
12 &afe {
13 power-domains = <&scpsys MT7623A_POWER
14 };
15
16 &crypto {
17 power-domains = <&scpsys MT7623A_POWER
18 };
19
20 &gmac0 {
21 status = "okay";
22 phy-mode = "trgmii";
23
24 fixed-link {
25 speed = <1000>;
26 full-duplex;
27 pause;
28 };
29 };
30
31 &gmac1 {
32 status = "okay";
33 phy-mode = "rgmii";
34
35 fixed-link {
36 speed = <1000>;
37 full-duplex;
38 pause;
39 };
40 };
41
42 ð {
43 status = "okay";
44 power-domains = <&scpsys MT7623A_POWER
45
46 mdio: mdio-bus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 switch0: switch@1f {
51 compatible = "mediatek
52 reg = <0x1f>;
53 mediatek,mcm;
54 resets = <ðsys MT27
55 reset-names = "mcm";
56 core-supply = <&mt6323
57 io-supply = <&mt6323_v
58
59 ports {
60 #address-cells
61 #size-cells =
62
63 port@0 {
64 status
65 reg =
66 label
67 };
68
69 port@1 {
70 status
71 reg =
72 label
73 };
74
75 port@2 {
76 status
77 reg =
78 label
79 };
80
81 port@3 {
82 status
83 reg =
84 label
85 };
86
87 port@4 {
88 status
89 reg =
90 label
91 };
92
93 port@5 {
94 reg =
95 label
96 ethern
97 phy-mo
98
99 fixed-
100
101
102
103 };
104 };
105
106 port@6 {
107 reg =
108 label
109 ethern
110 phy-mo
111
112 fixed-
113
114
115
116 };
117 };
118 };
119 };
120 };
121 };
122
123 &nandc {
124 power-domains = <&scpsys MT7623A_POWER
125 };
126
127 &pcie {
128 power-domains = <&scpsys MT7623A_POWER
129 };
130
131 &scpsys {
132 compatible = "mediatek,mt7623a-scpsys"
133 clocks = <&topckgen CLK_TOP_ETHIF_SEL>
134 clock-names = "ethif";
135 };
136
137 &usb0 {
138 power-domains = <&scpsys MT7623A_POWER
139 };
140
141 &usb1 {
142 power-domains = <&scpsys MT7623A_POWER
143 };
144
145 &usb2 {
146 power-domains = <&scpsys MT7623A_POWER
147 };
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