1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright © 2017-2020 MediaTek Inc.
4 * Author: Sean Wang <sean.wang@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 *
7 */
8
9 #include "mt7623.dtsi"
10 #include <dt-bindings/memory/mt2701-larb-port.
11
12 / {
13 aliases {
14 rdma0 = &rdma0;
15 rdma1 = &rdma1;
16 };
17
18 g3dsys: syscon@13000000 {
19 compatible = "mediatek,mt7623-
20 "mediatek,mt2701-
21 "syscon";
22 reg = <0 0x13000000 0 0x200>;
23 #clock-cells = <1>;
24 #reset-cells = <1>;
25 };
26
27 mali: gpu@13040000 {
28 compatible = "mediatek,mt7623-
29 reg = <0 0x13040000 0 0x30000>
30 interrupts = <GIC_SPI 170 IRQ_
31 <GIC_SPI 171 IRQ_
32 <GIC_SPI 172 IRQ_
33 <GIC_SPI 173 IRQ_
34 <GIC_SPI 174 IRQ_
35 <GIC_SPI 175 IRQ_
36 <GIC_SPI 176 IRQ_
37 <GIC_SPI 177 IRQ_
38 <GIC_SPI 178 IRQ_
39 <GIC_SPI 179 IRQ_
40 <GIC_SPI 180 IRQ_
41 interrupt-names = "gp", "gpmmu
42 "ppmmu1", "p
43 "pp";
44 clocks = <&topckgen CLK_TOP_MM
45 <&g3dsys CLK_G3DSYS_C
46 clock-names = "bus", "core";
47 power-domains = <&scpsys MT270
48 resets = <&g3dsys MT2701_G3DSY
49 };
50
51 mmsys: syscon@14000000 {
52 compatible = "mediatek,mt7623-
53 "mediatek,mt2701-
54 "syscon";
55 reg = <0 0x14000000 0 0x1000>;
56 #clock-cells = <1>;
57 };
58
59 larb0: larb@14010000 {
60 compatible = "mediatek,mt7623-
61 "mediatek,mt2701-
62 reg = <0 0x14010000 0 0x1000>;
63 mediatek,smi = <&smi_common>;
64 mediatek,larb-id = <0>;
65 clocks = <&mmsys CLK_MM_SMI_LA
66 <&mmsys CLK_MM_SMI_LA
67 clock-names = "apb", "smi";
68 power-domains = <&scpsys MT270
69 };
70
71 larb1: larb@16010000 {
72 compatible = "mediatek,mt7623-
73 "mediatek,mt2701-
74 reg = <0 0x16010000 0 0x1000>;
75 mediatek,smi = <&smi_common>;
76 mediatek,larb-id = <1>;
77 clocks = <&vdecsys CLK_VDEC_CK
78 <&vdecsys CLK_VDEC_LA
79 clock-names = "apb", "smi";
80 power-domains = <&scpsys MT270
81 };
82
83 larb2: larb@15001000 {
84 compatible = "mediatek,mt7623-
85 "mediatek,mt2701-
86 reg = <0 0x15001000 0 0x1000>;
87 mediatek,smi = <&smi_common>;
88 mediatek,larb-id = <2>;
89 clocks = <&imgsys CLK_IMG_SMI_
90 <&imgsys CLK_IMG_SMI_
91 clock-names = "apb", "smi";
92 power-domains = <&scpsys MT270
93 };
94
95 imgsys: syscon@15000000 {
96 compatible = "mediatek,mt7623-
97 "mediatek,mt2701-
98 "syscon";
99 reg = <0 0x15000000 0 0x1000>;
100 #clock-cells = <1>;
101 };
102
103 iommu: mmsys_iommu@10205000 {
104 compatible = "mediatek,mt7623-
105 "mediatek,mt2701-
106 reg = <0 0x10205000 0 0x1000>;
107 interrupts = <GIC_SPI 106 IRQ_
108 clocks = <&infracfg CLK_INFRA_
109 clock-names = "bclk";
110 mediatek,larbs = <&larb0 &larb
111 #iommu-cells = <1>;
112 };
113
114 jpegdec: jpegdec@15004000 {
115 compatible = "mediatek,mt7623-
116 "mediatek,mt2701-
117 reg = <0 0x15004000 0 0x1000>;
118 interrupts = <GIC_SPI 143 IRQ_
119 clocks = <&imgsys CLK_IMG_JPGD
120 <&imgsys CLK_IMG_JPGD
121 clock-names = "jpgdec-smi",
122 "jpgdec";
123 power-domains = <&scpsys MT270
124 iommus = <&iommu MT2701_M4U_PO
125 <&iommu MT2701_M4U_PO
126 };
127
128 smi_common: smi@1000c000 {
129 compatible = "mediatek,mt7623-
130 "mediatek,mt2701-
131 reg = <0 0x1000c000 0 0x1000>;
132 clocks = <&infracfg CLK_INFRA_
133 <&mmsys CLK_MM_SMI_CO
134 <&infracfg CLK_INFRA_
135 clock-names = "apb", "smi", "a
136 power-domains = <&scpsys MT270
137 };
138
139 ovl: ovl@14007000 {
140 compatible = "mediatek,mt7623-
141 "mediatek,mt2701-
142 reg = <0 0x14007000 0 0x1000>;
143 interrupts = <GIC_SPI 153 IRQ_
144 clocks = <&mmsys CLK_MM_DISP_O
145 iommus = <&iommu MT2701_M4U_PO
146 };
147
148 rdma0: rdma@14008000 {
149 compatible = "mediatek,mt7623-
150 "mediatek,mt2701-
151 reg = <0 0x14008000 0 0x1000>;
152 interrupts = <GIC_SPI 152 IRQ_
153 clocks = <&mmsys CLK_MM_DISP_R
154 iommus = <&iommu MT2701_M4U_PO
155 };
156
157 wdma@14009000 {
158 compatible = "mediatek,mt7623-
159 "mediatek,mt2701-
160 reg = <0 0x14009000 0 0x1000>;
161 interrupts = <GIC_SPI 154 IRQ_
162 clocks = <&mmsys CLK_MM_DISP_W
163 iommus = <&iommu MT2701_M4U_PO
164 };
165
166 bls: pwm@1400a000 {
167 compatible = "mediatek,mt7623-
168 "mediatek,mt2701-
169 reg = <0 0x1400a000 0 0x1000>;
170 #pwm-cells = <2>;
171 clocks = <&mmsys CLK_MM_MDP_BL
172 <&mmsys CLK_MM_DISP_B
173 clock-names = "main", "mm";
174 status = "disabled";
175 };
176
177 color: color@1400b000 {
178 compatible = "mediatek,mt7623-
179 "mediatek,mt2701-
180 reg = <0 0x1400b000 0 0x1000>;
181 interrupts = <GIC_SPI 156 IRQ_
182 clocks = <&mmsys CLK_MM_DISP_C
183 };
184
185 dsi: dsi@1400c000 {
186 compatible = "mediatek,mt7623-
187 "mediatek,mt2701-
188 reg = <0 0x1400c000 0 0x1000>;
189 interrupts = <GIC_SPI 157 IRQ_
190 clocks = <&mmsys CLK_MM_DSI_EN
191 <&mmsys CLK_MM_DSI_DI
192 <&mipi_tx0>;
193 clock-names = "engine", "digit
194 phys = <&mipi_tx0>;
195 phy-names = "dphy";
196 status = "disabled";
197 };
198
199 mutex: mutex@1400e000 {
200 compatible = "mediatek,mt7623-
201 "mediatek,mt2701-
202 reg = <0 0x1400e000 0 0x1000>;
203 interrupts = <GIC_SPI 161 IRQ_
204 clocks = <&mmsys CLK_MM_MUTEX_
205 };
206
207 rdma1: rdma@14012000 {
208 compatible = "mediatek,mt7623-
209 "mediatek,mt2701-
210 reg = <0 0x14012000 0 0x1000>;
211 interrupts = <GIC_SPI 164 IRQ_
212 clocks = <&mmsys CLK_MM_DISP_R
213 iommus = <&iommu MT2701_M4U_PO
214 };
215
216 dpi0: dpi@14014000 {
217 compatible = "mediatek,mt7623-
218 "mediatek,mt2701-
219 reg = <0 0x14014000 0 0x1000>;
220 interrupts = <GIC_SPI 194 IRQ_
221 clocks = <&mmsys CLK_MM_DPI1_D
222 <&mmsys CLK_MM_DPI1_E
223 <&apmixedsys CLK_APMI
224 clock-names = "pixel", "engine
225 status = "disabled";
226 };
227
228 hdmi0: hdmi@14015000 {
229 compatible = "mediatek,mt7623-
230 "mediatek,mt2701-
231 reg = <0 0x14015000 0 0x400>;
232 clocks = <&mmsys CLK_MM_HDMI_P
233 <&mmsys CLK_MM_HDMI_P
234 <&mmsys CLK_MM_HDMI_A
235 <&mmsys CLK_MM_HDMI_S
236 clock-names = "pixel", "pll",
237 phys = <&hdmi_phy>;
238 phy-names = "hdmi";
239 mediatek,syscon-hdmi = <&mmsys
240 cec = <&cec>;
241 status = "disabled";
242 };
243
244 mipi_tx0: dsi-phy@10010000 {
245 compatible = "mediatek,mt7623-
246 "mediatek,mt2701-
247 reg = <0 0x10010000 0 0x90>;
248 clocks = <&clk26m>;
249 clock-output-names = "mipi_tx0
250 #clock-cells = <0>;
251 #phy-cells = <0>;
252 };
253
254 cec: cec@10012000 {
255 compatible = "mediatek,mt7623-
256 "mediatek,mt8173-
257 reg = <0 0x10012000 0 0xbc>;
258 interrupts = <GIC_SPI 182 IRQ_
259 clocks = <&infracfg CLK_INFRA_
260 status = "disabled";
261 };
262
263 hdmi_phy: hdmi-phy@10209100 {
264 compatible = "mediatek,mt7623-
265 "mediatek,mt2701-
266 reg = <0 0x10209100 0 0x24>;
267 clocks = <&apmixedsys CLK_APMI
268 clock-names = "pll_ref";
269 clock-output-names = "hdmitx_d
270 #clock-cells = <0>;
271 #phy-cells = <0>;
272 status = "disabled";
273 };
274
275 hdmiddc0: i2c@11013000 {
276 compatible = "mediatek,mt7623-
277 "mediatek,mt8173-
278 interrupts = <GIC_SPI 81 IRQ_T
279 reg = <0 0x11013000 0 0x1C>;
280 clocks = <&pericfg CLK_PERI_I2
281 clock-names = "ddc-i2c";
282 status = "disabled";
283 };
284 };
285
286 &pio {
287 hdmi_pins_a: hdmi-default {
288 pins-hdmi {
289 pinmux = <MT7623_PIN_1
290 input-enable;
291 bias-pull-down;
292 };
293 };
294
295 hdmi_ddc_pins_a: hdmi_ddc-default {
296 pins-hdmi-ddc {
297 pinmux = <MT7623_PIN_1
298 <MT7623_PIN_1
299 };
300 };
301 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.