1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019 MediaTek Inc.
4 *
5 * Author: Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
15
16 / {
17 compatible = "mediatek,mt7629";
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "mediatek,mt65
26
27 cpu0: cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cort
30 reg = <0x0>;
31 clock-frequency = <125
32 cci-control-port = <&c
33 };
34
35 cpu1: cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cort
38 reg = <0x1>;
39 clock-frequency = <125
40 cci-control-port = <&c
41 };
42 };
43
44 pmu {
45 compatible = "arm,cortex-a7-pm
46 interrupts = <GIC_SPI 8 IRQ_TY
47 <GIC_SPI 9 IRQ_TY
48 interrupt-affinity = <&cpu0>,
49 };
50
51 clk20m: oscillator-0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <20000000>;
55 clock-output-names = "clk20m";
56 };
57
58 clk40m: oscillator-1 {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <40000000>;
62 clock-output-names = "clkxtal"
63 };
64
65 timer {
66 compatible = "arm,armv7-timer"
67 interrupt-parent = <&gic>;
68 interrupts = <GIC_PPI 13 (GIC_
69 <GIC_PPI 14 (GIC_
70 <GIC_PPI 11 (GIC_
71 <GIC_PPI 10 (GIC_
72 clock-frequency = <20000000>;
73 };
74
75 soc {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80
81 infracfg: syscon@10000000 {
82 compatible = "mediatek
83 reg = <0x10000000 0x10
84 #clock-cells = <1>;
85 };
86
87 pericfg: syscon@10002000 {
88 compatible = "mediatek
89 reg = <0x10002000 0x10
90 #clock-cells = <1>;
91 };
92
93 scpsys: power-controller@10006
94 compatible = "mediatek
95 "mediatek
96 #power-domain-cells =
97 reg = <0x10006000 0x10
98 clocks = <&topckgen CL
99 clock-names = "hif_sel
100 assigned-clocks = <&to
101 assigned-clock-parents
102 infracfg = <&infracfg>
103 };
104
105 timer: timer@10009000 {
106 compatible = "mediatek
107 "mediatek
108 reg = <0x10009000 0x60
109 interrupts = <GIC_SPI
110 clocks = <&clk20m>;
111 clock-names = "clk20m"
112 };
113
114 sysirq: interrupt-controller@1
115 compatible = "mediatek
116 "mediatek
117 reg = <0x10200a80 0x20
118 interrupt-controller;
119 #interrupt-cells = <3>
120 interrupt-parent = <&g
121 };
122
123 apmixedsys: syscon@10209000 {
124 compatible = "mediatek
125 reg = <0x10209000 0x10
126 #clock-cells = <1>;
127 };
128
129 rng: rng@1020f000 {
130 compatible = "mediatek
131 "mediatek
132 reg = <0x1020f000 0x10
133 clocks = <&infracfg CL
134 clock-names = "rng";
135 };
136
137 topckgen: syscon@10210000 {
138 compatible = "mediatek
139 reg = <0x10210000 0x10
140 #clock-cells = <1>;
141 };
142
143 watchdog: watchdog@10212000 {
144 compatible = "mediatek
145 "mediatek
146 reg = <0x10212000 0x10
147 };
148
149 pio: pinctrl@10217000 {
150 compatible = "mediatek
151 reg = <0x10217000 0x80
152 <0x10005000 0x10
153 reg-names = "base", "e
154 gpio-controller;
155 gpio-ranges = <&pio 0
156 #gpio-cells = <2>;
157 #interrupt-cells = <2>
158 interrupt-controller;
159 interrupts = <GIC_SPI
160 interrupt-parent = <&g
161 };
162
163 gic: interrupt-controller@1030
164 compatible = "arm,gic-
165 interrupt-controller;
166 #interrupt-cells = <3>
167 interrupt-parent = <&g
168 reg = <0x10310000 0x10
169 <0x10320000 0x10
170 <0x10340000 0x20
171 <0x10360000 0x20
172 };
173
174 cci: cci@10390000 {
175 compatible = "arm,cci-
176 #address-cells = <1>;
177 #size-cells = <1>;
178 reg = <0x10390000 0x10
179 ranges = <0 0x10390000
180
181 cci_control0: slave-if
182 compatible = "
183 interface-type
184 reg = <0x1000
185 };
186
187 cci_control1: slave-if
188 compatible = "
189 interface-type
190 reg = <0x4000
191 };
192
193 cci_control2: slave-if
194 compatible = "
195 interface-type
196 reg = <0x5000
197 };
198
199 pmu@9000 {
200 compatible = "
201 reg = <0x9000
202 interrupts = <
203 <
204 <
205 <
206 <
207 };
208 };
209
210 uart0: serial@11002000 {
211 compatible = "mediatek
212 "mediatek
213 reg = <0x11002000 0x40
214 interrupts = <GIC_SPI
215 clocks = <&topckgen CL
216 <&pericfg CLK
217 clock-names = "baud",
218 status = "disabled";
219 };
220
221 uart1: serial@11003000 {
222 compatible = "mediatek
223 "mediatek
224 reg = <0x11003000 0x40
225 interrupts = <GIC_SPI
226 clocks = <&topckgen CL
227 <&pericfg CLK
228 clock-names = "baud",
229 status = "disabled";
230 };
231
232 uart2: serial@11004000 {
233 compatible = "mediatek
234 "mediatek
235 reg = <0x11004000 0x40
236 interrupts = <GIC_SPI
237 clocks = <&topckgen CL
238 <&pericfg CLK
239 clock-names = "baud",
240 status = "disabled";
241 };
242
243 pwm: pwm@11006000 {
244 compatible = "mediatek
245 reg = <0x11006000 0x10
246 #pwm-cells = <2>;
247 clocks = <&topckgen CL
248 <&pericfg CLK
249 <&pericfg CLK
250 clock-names = "top", "
251 assigned-clocks = <&to
252 assigned-clock-parents
253 <&topc
254 status = "disabled";
255 };
256
257 i2c: i2c@11007000 {
258 compatible = "mediatek
259 "mediatek
260 reg = <0x11007000 0x90
261 <0x11000100 0x80
262 interrupts = <GIC_SPI
263 clock-div = <4>;
264 clocks = <&pericfg CLK
265 <&pericfg CLK
266 clock-names = "main",
267 assigned-clocks = <&to
268 assigned-clock-parents
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
273
274 spi: spi@1100a000 {
275 compatible = "mediatek
276 "mediatek
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <0x1100a000 0x10
280 interrupts = <GIC_SPI
281 clocks = <&topckgen CL
282 <&topckgen CL
283 <&pericfg CLK
284 clock-names = "parent-
285 status = "disabled";
286 };
287
288 qspi: spi@11014000 {
289 compatible = "mediatek
290 "mediatek
291 reg = <0x11014000 0xe0
292 clocks = <&pericfg CLK
293 <&topckgen CL
294 clock-names = "spi", "
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 ssusbsys: syscon@1a000000 {
301 compatible = "mediatek
302 reg = <0x1a000000 0x10
303 #clock-cells = <1>;
304 #reset-cells = <1>;
305 };
306
307 ssusb: usb@1a0c0000 {
308 compatible = "mediatek
309 "mediatek
310 reg = <0x1a0c0000 0x01
311 <0x1a0c3e00 0x01
312 reg-names = "mac", "ip
313 interrupts = <GIC_SPI
314 clocks = <&ssusbsys CL
315 <&ssusbsys CL
316 <&ssusbsys CL
317 <&ssusbsys CL
318 clock-names = "sys_ck"
319 assigned-clocks = <&to
320 <&to
321 <&to
322 assigned-clock-parents
323
324
325 power-domains = <&scps
326 phys = <&u2port0 PHY_T
327 <&u3port0 PHY_T
328 status = "disabled";
329 };
330
331 u3phy0: t-phy@1a0c4000 {
332 compatible = "mediatek
333 "mediatek
334 #address-cells = <1>;
335 #size-cells = <1>;
336 ranges = <0 0x1a0c4000
337 status = "disabled";
338
339 u2port0: usb-phy@0 {
340 reg = <0 0x700
341 clocks = <&ssu
342 clock-names =
343 #phy-cells = <
344 status = "okay
345 };
346
347 u3port0: usb-phy@700 {
348 reg = <0x700 0
349 clocks = <&clk
350 clock-names =
351 #phy-cells = <
352 status = "okay
353 };
354 };
355
356 pciesys: syscon@1a100800 {
357 compatible = "mediatek
358 reg = <0x1a100800 0x10
359 #clock-cells = <1>;
360 #reset-cells = <1>;
361 };
362
363 pciecfg: pciecfg@1a140000 {
364 compatible = "mediatek
365 reg = <0x1a140000 0x10
366 };
367
368 pcie1: pcie@1a145000 {
369 compatible = "mediatek
370 device_type = "pci";
371 reg = <0x1a145000 0x10
372 reg-names = "port1";
373 linux,pci-domain = <1>
374 #address-cells = <3>;
375 #size-cells = <2>;
376 interrupts = <GIC_SPI
377 interrupt-names = "pci
378 clocks = <&pciesys CLK
379 <&pciesys CLK
380 <&pciesys CLK
381 <&pciesys CLK
382 <&pciesys CLK
383 <&pciesys CLK
384 clock-names = "sys_ck1
385 "aux_ck1
386 "obff_ck
387 assigned-clocks = <&to
388 <&to
389 <&to
390 assigned-clock-parents
391
392
393 phys = <&pcieport1 PHY
394 phy-names = "pcie-phy1
395 power-domains = <&scps
396 bus-range = <0x00 0xff
397 ranges = <0x82000000 0
398 status = "disabled";
399
400 #interrupt-cells = <1>
401 interrupt-map-mask = <
402 interrupt-map = <0 0 0
403 <0 0 0
404 <0 0 0
405 <0 0 0
406 pcie_intc1: interrupt-
407 interrupt-cont
408 #address-cells
409 #interrupt-cel
410 };
411 };
412
413 pciephy1: t-phy@1a14a000 {
414 compatible = "mediatek
415 "mediatek
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0 0x1a14a000
419 status = "disabled";
420
421 pcieport1: pcie-phy@0
422 reg = <0 0x100
423 clocks = <&clk
424 clock-names =
425 #phy-cells = <
426 status = "okay
427 };
428 };
429
430 ethsys: syscon@1b000000 {
431 compatible = "mediatek
432 reg = <0x1b000000 0x10
433 #clock-cells = <1>;
434 #reset-cells = <1>;
435 };
436
437 eth: ethernet@1b100000 {
438 compatible = "mediatek
439 reg = <0x1b100000 0x20
440 interrupts = <GIC_SPI
441 <GIC_SPI
442 <GIC_SPI
443 clocks = <&topckgen CL
444 <&topckgen CL
445 <ðsys CLK_
446 <ðsys CLK_
447 <ðsys CLK_
448 <ðsys CLK_
449 <ðsys CLK_
450 <&sgmiisys0 C
451 <&sgmiisys0 C
452 <&sgmiisys0 C
453 <&sgmiisys0 C
454 <&sgmiisys1 C
455 <&sgmiisys1 C
456 <&sgmiisys1 C
457 <&sgmiisys1 C
458 <&apmixedsys
459 <&apmixedsys
460 clock-names = "ethif",
461 "gp2", "
462 "sgmii_c
463 "sgmii2_
464 "sgmii2_
465 "sgmii_c
466 assigned-clocks = <&to
467 <&to
468 assigned-clock-parents
469
470 power-domains = <&scps
471 mediatek,ethsys = <&et
472 mediatek,sgmiisys = <&
473 mediatek,infracfg = <&
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "disabled";
477 };
478
479 sgmiisys0: syscon@1b128000 {
480 compatible = "mediatek
481 reg = <0x1b128000 0x30
482 #clock-cells = <1>;
483 };
484
485 sgmiisys1: syscon@1b130000 {
486 compatible = "mediatek
487 reg = <0x1b130000 0x30
488 #clock-cells = <1>;
489 };
490 };
491 };
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