1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (c) 2019 MediaTek Inc. 3 * Copyright (c) 2019 MediaTek Inc.
4 * 4 *
5 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 * Author: Ryder Lee <ryder.lee@mediatek.com>
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h> 10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h> 11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h> 14 #include <dt-bindings/reset/mt7629-resets.h>
15 15
16 / { 16 / {
17 compatible = "mediatek,mt7629"; 17 compatible = "mediatek,mt7629";
18 interrupt-parent = <&sysirq>; 18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <1>; 20 #size-cells = <1>;
21 21
22 cpus { 22 cpus {
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 enable-method = "mediatek,mt65 25 enable-method = "mediatek,mt6589-smp";
26 26
27 cpu0: cpu@0 { 27 cpu0: cpu@0 {
28 device_type = "cpu"; 28 device_type = "cpu";
29 compatible = "arm,cort 29 compatible = "arm,cortex-a7";
30 reg = <0x0>; 30 reg = <0x0>;
31 clock-frequency = <125 31 clock-frequency = <1250000000>;
32 cci-control-port = <&c 32 cci-control-port = <&cci_control2>;
33 }; 33 };
34 34
35 cpu1: cpu@1 { 35 cpu1: cpu@1 {
36 device_type = "cpu"; 36 device_type = "cpu";
37 compatible = "arm,cort 37 compatible = "arm,cortex-a7";
38 reg = <0x1>; 38 reg = <0x1>;
39 clock-frequency = <125 39 clock-frequency = <1250000000>;
40 cci-control-port = <&c 40 cci-control-port = <&cci_control2>;
41 }; 41 };
42 }; 42 };
43 43
44 pmu { 44 pmu {
45 compatible = "arm,cortex-a7-pm 45 compatible = "arm,cortex-a7-pmu";
46 interrupts = <GIC_SPI 8 IRQ_TY 46 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
47 <GIC_SPI 9 IRQ_TY 47 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
48 interrupt-affinity = <&cpu0>, 48 interrupt-affinity = <&cpu0>, <&cpu1>;
49 }; 49 };
50 50
51 clk20m: oscillator-0 { 51 clk20m: oscillator-0 {
52 compatible = "fixed-clock"; 52 compatible = "fixed-clock";
53 #clock-cells = <0>; 53 #clock-cells = <0>;
54 clock-frequency = <20000000>; 54 clock-frequency = <20000000>;
55 clock-output-names = "clk20m"; 55 clock-output-names = "clk20m";
56 }; 56 };
57 57
58 clk40m: oscillator-1 { 58 clk40m: oscillator-1 {
59 compatible = "fixed-clock"; 59 compatible = "fixed-clock";
60 #clock-cells = <0>; 60 #clock-cells = <0>;
61 clock-frequency = <40000000>; 61 clock-frequency = <40000000>;
62 clock-output-names = "clkxtal" 62 clock-output-names = "clkxtal";
63 }; 63 };
64 64
65 timer { 65 timer {
66 compatible = "arm,armv7-timer" 66 compatible = "arm,armv7-timer";
67 interrupt-parent = <&gic>; 67 interrupt-parent = <&gic>;
68 interrupts = <GIC_PPI 13 (GIC_ 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
69 <GIC_PPI 14 (GIC_ 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
70 <GIC_PPI 11 (GIC_ 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
71 <GIC_PPI 10 (GIC_ 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
72 clock-frequency = <20000000>; 72 clock-frequency = <20000000>;
73 }; 73 };
74 74
75 soc { 75 soc {
76 compatible = "simple-bus"; 76 compatible = "simple-bus";
77 #address-cells = <1>; 77 #address-cells = <1>;
78 #size-cells = <1>; 78 #size-cells = <1>;
79 ranges; 79 ranges;
80 80
81 infracfg: syscon@10000000 { 81 infracfg: syscon@10000000 {
82 compatible = "mediatek 82 compatible = "mediatek,mt7629-infracfg", "syscon";
83 reg = <0x10000000 0x10 83 reg = <0x10000000 0x1000>;
84 #clock-cells = <1>; 84 #clock-cells = <1>;
85 }; 85 };
86 86
87 pericfg: syscon@10002000 { 87 pericfg: syscon@10002000 {
88 compatible = "mediatek 88 compatible = "mediatek,mt7629-pericfg", "syscon";
89 reg = <0x10002000 0x10 89 reg = <0x10002000 0x1000>;
90 #clock-cells = <1>; 90 #clock-cells = <1>;
91 }; 91 };
92 92
93 scpsys: power-controller@10006 93 scpsys: power-controller@10006000 {
94 compatible = "mediatek 94 compatible = "mediatek,mt7629-scpsys",
95 "mediatek 95 "mediatek,mt7622-scpsys";
96 #power-domain-cells = 96 #power-domain-cells = <1>;
97 reg = <0x10006000 0x10 97 reg = <0x10006000 0x1000>;
98 clocks = <&topckgen CL 98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
99 clock-names = "hif_sel 99 clock-names = "hif_sel";
100 assigned-clocks = <&to 100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents 101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
102 infracfg = <&infracfg> 102 infracfg = <&infracfg>;
103 }; 103 };
104 104
105 timer: timer@10009000 { 105 timer: timer@10009000 {
106 compatible = "mediatek 106 compatible = "mediatek,mt7629-timer",
107 "mediatek 107 "mediatek,mt6765-timer";
108 reg = <0x10009000 0x60 108 reg = <0x10009000 0x60>;
109 interrupts = <GIC_SPI 109 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&clk20m>; 110 clocks = <&clk20m>;
111 clock-names = "clk20m" 111 clock-names = "clk20m";
112 }; 112 };
113 113
114 sysirq: interrupt-controller@1 114 sysirq: interrupt-controller@10200a80 {
115 compatible = "mediatek 115 compatible = "mediatek,mt7629-sysirq",
116 "mediatek 116 "mediatek,mt6577-sysirq";
117 reg = <0x10200a80 0x20 117 reg = <0x10200a80 0x20>;
118 interrupt-controller; 118 interrupt-controller;
119 #interrupt-cells = <3> 119 #interrupt-cells = <3>;
120 interrupt-parent = <&g 120 interrupt-parent = <&gic>;
121 }; 121 };
122 122
123 apmixedsys: syscon@10209000 { 123 apmixedsys: syscon@10209000 {
124 compatible = "mediatek 124 compatible = "mediatek,mt7629-apmixedsys", "syscon";
125 reg = <0x10209000 0x10 125 reg = <0x10209000 0x1000>;
126 #clock-cells = <1>; 126 #clock-cells = <1>;
127 }; 127 };
128 128
129 rng: rng@1020f000 { 129 rng: rng@1020f000 {
130 compatible = "mediatek 130 compatible = "mediatek,mt7629-rng",
131 "mediatek 131 "mediatek,mt7623-rng";
132 reg = <0x1020f000 0x10 132 reg = <0x1020f000 0x100>;
133 clocks = <&infracfg CL 133 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
134 clock-names = "rng"; 134 clock-names = "rng";
135 }; 135 };
136 136
137 topckgen: syscon@10210000 { 137 topckgen: syscon@10210000 {
138 compatible = "mediatek 138 compatible = "mediatek,mt7629-topckgen", "syscon";
139 reg = <0x10210000 0x10 139 reg = <0x10210000 0x1000>;
140 #clock-cells = <1>; 140 #clock-cells = <1>;
141 }; 141 };
142 142
143 watchdog: watchdog@10212000 { 143 watchdog: watchdog@10212000 {
144 compatible = "mediatek 144 compatible = "mediatek,mt7629-wdt",
145 "mediatek 145 "mediatek,mt6589-wdt";
146 reg = <0x10212000 0x10 146 reg = <0x10212000 0x100>;
147 }; 147 };
148 148
149 pio: pinctrl@10217000 { 149 pio: pinctrl@10217000 {
150 compatible = "mediatek 150 compatible = "mediatek,mt7629-pinctrl";
151 reg = <0x10217000 0x80 151 reg = <0x10217000 0x8000>,
152 <0x10005000 0x10 152 <0x10005000 0x1000>;
153 reg-names = "base", "e 153 reg-names = "base", "eint";
154 gpio-controller; 154 gpio-controller;
155 gpio-ranges = <&pio 0 155 gpio-ranges = <&pio 0 0 79>;
156 #gpio-cells = <2>; 156 #gpio-cells = <2>;
157 #interrupt-cells = <2> 157 #interrupt-cells = <2>;
158 interrupt-controller; 158 interrupt-controller;
159 interrupts = <GIC_SPI 159 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-parent = <&g 160 interrupt-parent = <&gic>;
161 }; 161 };
162 162
163 gic: interrupt-controller@1030 163 gic: interrupt-controller@10300000 {
164 compatible = "arm,gic- 164 compatible = "arm,gic-400";
165 interrupt-controller; 165 interrupt-controller;
166 #interrupt-cells = <3> 166 #interrupt-cells = <3>;
167 interrupt-parent = <&g 167 interrupt-parent = <&gic>;
168 reg = <0x10310000 0x10 168 reg = <0x10310000 0x1000>,
169 <0x10320000 0x10 169 <0x10320000 0x1000>,
170 <0x10340000 0x20 170 <0x10340000 0x2000>,
171 <0x10360000 0x20 171 <0x10360000 0x2000>;
172 }; 172 };
173 173
174 cci: cci@10390000 { 174 cci: cci@10390000 {
175 compatible = "arm,cci- 175 compatible = "arm,cci-400";
176 #address-cells = <1>; 176 #address-cells = <1>;
177 #size-cells = <1>; 177 #size-cells = <1>;
178 reg = <0x10390000 0x10 178 reg = <0x10390000 0x1000>;
179 ranges = <0 0x10390000 179 ranges = <0 0x10390000 0x10000>;
180 180
181 cci_control0: slave-if 181 cci_control0: slave-if@1000 {
182 compatible = " 182 compatible = "arm,cci-400-ctrl-if";
183 interface-type 183 interface-type = "ace-lite";
184 reg = <0x1000 184 reg = <0x1000 0x1000>;
185 }; 185 };
186 186
187 cci_control1: slave-if 187 cci_control1: slave-if@4000 {
188 compatible = " 188 compatible = "arm,cci-400-ctrl-if";
189 interface-type 189 interface-type = "ace";
190 reg = <0x4000 190 reg = <0x4000 0x1000>;
191 }; 191 };
192 192
193 cci_control2: slave-if 193 cci_control2: slave-if@5000 {
194 compatible = " 194 compatible = "arm,cci-400-ctrl-if";
195 interface-type 195 interface-type = "ace";
196 reg = <0x5000 196 reg = <0x5000 0x1000>;
197 }; 197 };
198 198
199 pmu@9000 { 199 pmu@9000 {
200 compatible = " 200 compatible = "arm,cci-400-pmu,r1";
201 reg = <0x9000 201 reg = <0x9000 0x5000>;
202 interrupts = < 202 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
203 < 203 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
204 < 204 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
205 < 205 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
206 < 206 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
207 }; 207 };
208 }; 208 };
209 209
210 uart0: serial@11002000 { 210 uart0: serial@11002000 {
211 compatible = "mediatek 211 compatible = "mediatek,mt7629-uart",
212 "mediatek 212 "mediatek,mt6577-uart";
213 reg = <0x11002000 0x40 213 reg = <0x11002000 0x400>;
214 interrupts = <GIC_SPI 214 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
215 clocks = <&topckgen CL 215 clocks = <&topckgen CLK_TOP_UART_SEL>,
216 <&pericfg CLK 216 <&pericfg CLK_PERI_UART0_PD>;
217 clock-names = "baud", 217 clock-names = "baud", "bus";
218 status = "disabled"; 218 status = "disabled";
219 }; 219 };
220 220
221 uart1: serial@11003000 { 221 uart1: serial@11003000 {
222 compatible = "mediatek 222 compatible = "mediatek,mt7629-uart",
223 "mediatek 223 "mediatek,mt6577-uart";
224 reg = <0x11003000 0x40 224 reg = <0x11003000 0x400>;
225 interrupts = <GIC_SPI 225 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
226 clocks = <&topckgen CL 226 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 <&pericfg CLK 227 <&pericfg CLK_PERI_UART1_PD>;
228 clock-names = "baud", 228 clock-names = "baud", "bus";
229 status = "disabled"; 229 status = "disabled";
230 }; 230 };
231 231
232 uart2: serial@11004000 { 232 uart2: serial@11004000 {
233 compatible = "mediatek 233 compatible = "mediatek,mt7629-uart",
234 "mediatek 234 "mediatek,mt6577-uart";
235 reg = <0x11004000 0x40 235 reg = <0x11004000 0x400>;
236 interrupts = <GIC_SPI 236 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
237 clocks = <&topckgen CL 237 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 <&pericfg CLK 238 <&pericfg CLK_PERI_UART2_PD>;
239 clock-names = "baud", 239 clock-names = "baud", "bus";
240 status = "disabled"; 240 status = "disabled";
241 }; 241 };
242 242
243 pwm: pwm@11006000 { 243 pwm: pwm@11006000 {
244 compatible = "mediatek 244 compatible = "mediatek,mt7629-pwm";
245 reg = <0x11006000 0x10 245 reg = <0x11006000 0x1000>;
246 #pwm-cells = <2>; 246 #pwm-cells = <2>;
247 clocks = <&topckgen CL 247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
248 <&pericfg CLK 248 <&pericfg CLK_PERI_PWM_PD>,
249 <&pericfg CLK 249 <&pericfg CLK_PERI_PWM1_PD>;
250 clock-names = "top", " 250 clock-names = "top", "main", "pwm1";
251 assigned-clocks = <&to 251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
252 assigned-clock-parents 252 assigned-clock-parents =
253 <&topc 253 <&topckgen CLK_TOP_UNIVPLL2_D4>;
254 status = "disabled"; 254 status = "disabled";
255 }; 255 };
256 256
257 i2c: i2c@11007000 { 257 i2c: i2c@11007000 {
258 compatible = "mediatek 258 compatible = "mediatek,mt7629-i2c",
259 "mediatek 259 "mediatek,mt2712-i2c";
260 reg = <0x11007000 0x90 260 reg = <0x11007000 0x90>,
261 <0x11000100 0x80 261 <0x11000100 0x80>;
262 interrupts = <GIC_SPI 262 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
263 clock-div = <4>; 263 clock-div = <4>;
264 clocks = <&pericfg CLK 264 clocks = <&pericfg CLK_PERI_I2C0_PD>,
265 <&pericfg CLK 265 <&pericfg CLK_PERI_AP_DMA_PD>;
266 clock-names = "main", 266 clock-names = "main", "dma";
267 assigned-clocks = <&to 267 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
268 assigned-clock-parents 268 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
269 #address-cells = <1>; 269 #address-cells = <1>;
270 #size-cells = <0>; 270 #size-cells = <0>;
271 status = "disabled"; 271 status = "disabled";
272 }; 272 };
273 273
274 spi: spi@1100a000 { 274 spi: spi@1100a000 {
275 compatible = "mediatek 275 compatible = "mediatek,mt7629-spi",
276 "mediatek 276 "mediatek,mt7622-spi";
277 #address-cells = <1>; 277 #address-cells = <1>;
278 #size-cells = <0>; 278 #size-cells = <0>;
279 reg = <0x1100a000 0x10 279 reg = <0x1100a000 0x100>;
280 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
281 clocks = <&topckgen CL 281 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
282 <&topckgen CL 282 <&topckgen CLK_TOP_SPI0_SEL>,
283 <&pericfg CLK 283 <&pericfg CLK_PERI_SPI0_PD>;
284 clock-names = "parent- 284 clock-names = "parent-clk", "sel-clk", "spi-clk";
285 status = "disabled"; 285 status = "disabled";
286 }; 286 };
287 287
288 qspi: spi@11014000 { 288 qspi: spi@11014000 {
289 compatible = "mediatek 289 compatible = "mediatek,mt7629-nor",
290 "mediatek 290 "mediatek,mt8173-nor";
291 reg = <0x11014000 0xe0 291 reg = <0x11014000 0xe0>;
292 clocks = <&pericfg CLK 292 clocks = <&pericfg CLK_PERI_FLASH_PD>,
293 <&topckgen CL 293 <&topckgen CLK_TOP_FLASH_SEL>;
294 clock-names = "spi", " 294 clock-names = "spi", "sf";
295 #address-cells = <1>; 295 #address-cells = <1>;
296 #size-cells = <0>; 296 #size-cells = <0>;
297 status = "disabled"; 297 status = "disabled";
298 }; 298 };
299 299
300 ssusbsys: syscon@1a000000 { 300 ssusbsys: syscon@1a000000 {
301 compatible = "mediatek 301 compatible = "mediatek,mt7629-ssusbsys", "syscon";
302 reg = <0x1a000000 0x10 302 reg = <0x1a000000 0x1000>;
303 #clock-cells = <1>; 303 #clock-cells = <1>;
304 #reset-cells = <1>; 304 #reset-cells = <1>;
305 }; 305 };
306 306
307 ssusb: usb@1a0c0000 { 307 ssusb: usb@1a0c0000 {
308 compatible = "mediatek 308 compatible = "mediatek,mt7629-xhci",
309 "mediatek 309 "mediatek,mtk-xhci";
310 reg = <0x1a0c0000 0x01 310 reg = <0x1a0c0000 0x01000>,
311 <0x1a0c3e00 0x01 311 <0x1a0c3e00 0x0100>;
312 reg-names = "mac", "ip 312 reg-names = "mac", "ippc";
313 interrupts = <GIC_SPI 313 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
314 clocks = <&ssusbsys CL 314 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
315 <&ssusbsys CL 315 <&ssusbsys CLK_SSUSB_REF_EN>,
316 <&ssusbsys CL 316 <&ssusbsys CLK_SSUSB_MCU_EN>,
317 <&ssusbsys CL 317 <&ssusbsys CLK_SSUSB_DMA_EN>;
318 clock-names = "sys_ck" 318 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
319 assigned-clocks = <&to 319 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
320 <&to 320 <&topckgen CLK_TOP_SATA_SEL>,
321 <&to 321 <&topckgen CLK_TOP_HIF_SEL>;
322 assigned-clock-parents 322 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
323 323 <&topckgen CLK_TOP_UNIVPLL2_D4>,
324 324 <&topckgen CLK_TOP_UNIVPLL1_D2>;
325 power-domains = <&scps 325 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
326 phys = <&u2port0 PHY_T 326 phys = <&u2port0 PHY_TYPE_USB2>,
327 <&u3port0 PHY_T 327 <&u3port0 PHY_TYPE_USB3>;
328 status = "disabled"; 328 status = "disabled";
329 }; 329 };
330 330
331 u3phy0: t-phy@1a0c4000 { 331 u3phy0: t-phy@1a0c4000 {
332 compatible = "mediatek 332 compatible = "mediatek,mt7629-tphy",
333 "mediatek 333 "mediatek,generic-tphy-v2";
334 #address-cells = <1>; 334 #address-cells = <1>;
335 #size-cells = <1>; 335 #size-cells = <1>;
336 ranges = <0 0x1a0c4000 336 ranges = <0 0x1a0c4000 0xe00>;
337 status = "disabled"; 337 status = "disabled";
338 338
339 u2port0: usb-phy@0 { 339 u2port0: usb-phy@0 {
340 reg = <0 0x700 340 reg = <0 0x700>;
341 clocks = <&ssu 341 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
342 clock-names = 342 clock-names = "ref";
343 #phy-cells = < 343 #phy-cells = <1>;
344 status = "okay 344 status = "okay";
345 }; 345 };
346 346
347 u3port0: usb-phy@700 { 347 u3port0: usb-phy@700 {
348 reg = <0x700 0 348 reg = <0x700 0x700>;
349 clocks = <&clk 349 clocks = <&clk20m>;
350 clock-names = 350 clock-names = "ref";
351 #phy-cells = < 351 #phy-cells = <1>;
352 status = "okay 352 status = "okay";
353 }; 353 };
354 }; 354 };
355 355
356 pciesys: syscon@1a100800 { 356 pciesys: syscon@1a100800 {
357 compatible = "mediatek 357 compatible = "mediatek,mt7629-pciesys", "syscon";
358 reg = <0x1a100800 0x10 358 reg = <0x1a100800 0x1000>;
359 #clock-cells = <1>; 359 #clock-cells = <1>;
360 #reset-cells = <1>; 360 #reset-cells = <1>;
361 }; 361 };
362 362
363 pciecfg: pciecfg@1a140000 { 363 pciecfg: pciecfg@1a140000 {
364 compatible = "mediatek 364 compatible = "mediatek,generic-pciecfg", "syscon";
365 reg = <0x1a140000 0x10 365 reg = <0x1a140000 0x1000>;
366 }; 366 };
367 367
368 pcie1: pcie@1a145000 { 368 pcie1: pcie@1a145000 {
369 compatible = "mediatek 369 compatible = "mediatek,mt7629-pcie";
370 device_type = "pci"; 370 device_type = "pci";
371 reg = <0x1a145000 0x10 371 reg = <0x1a145000 0x1000>;
372 reg-names = "port1"; 372 reg-names = "port1";
373 linux,pci-domain = <1> 373 linux,pci-domain = <1>;
374 #address-cells = <3>; 374 #address-cells = <3>;
375 #size-cells = <2>; 375 #size-cells = <2>;
376 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
377 interrupt-names = "pci 377 interrupt-names = "pcie_irq";
378 clocks = <&pciesys CLK 378 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
379 <&pciesys CLK 379 <&pciesys CLK_PCIE_P0_AHB_EN>,
380 <&pciesys CLK 380 <&pciesys CLK_PCIE_P1_AUX_EN>,
381 <&pciesys CLK 381 <&pciesys CLK_PCIE_P1_AXI_EN>,
382 <&pciesys CLK 382 <&pciesys CLK_PCIE_P1_OBFF_EN>,
383 <&pciesys CLK 383 <&pciesys CLK_PCIE_P1_PIPE_EN>;
384 clock-names = "sys_ck1 384 clock-names = "sys_ck1", "ahb_ck1",
385 "aux_ck1 385 "aux_ck1", "axi_ck1",
386 "obff_ck 386 "obff_ck1", "pipe_ck1";
387 assigned-clocks = <&to 387 assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
388 <&to 388 <&topckgen CLK_TOP_AXI_SEL>,
389 <&to 389 <&topckgen CLK_TOP_HIF_SEL>;
390 assigned-clock-parents 390 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
391 391 <&topckgen CLK_TOP_SYSPLL1_D2>,
392 392 <&topckgen CLK_TOP_UNIVPLL1_D2>;
393 phys = <&pcieport1 PHY 393 phys = <&pcieport1 PHY_TYPE_PCIE>;
394 phy-names = "pcie-phy1 394 phy-names = "pcie-phy1";
395 power-domains = <&scps 395 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
396 bus-range = <0x00 0xff 396 bus-range = <0x00 0xff>;
397 ranges = <0x82000000 0 397 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
398 status = "disabled"; 398 status = "disabled";
399 399
400 #interrupt-cells = <1> 400 #interrupt-cells = <1>;
401 interrupt-map-mask = < 401 interrupt-map-mask = <0 0 0 7>;
402 interrupt-map = <0 0 0 402 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
403 <0 0 0 403 <0 0 0 2 &pcie_intc1 1>,
404 <0 0 0 404 <0 0 0 3 &pcie_intc1 2>,
405 <0 0 0 405 <0 0 0 4 &pcie_intc1 3>;
406 pcie_intc1: interrupt- 406 pcie_intc1: interrupt-controller {
407 interrupt-cont 407 interrupt-controller;
408 #address-cells 408 #address-cells = <0>;
409 #interrupt-cel 409 #interrupt-cells = <1>;
410 }; 410 };
411 }; 411 };
412 412
413 pciephy1: t-phy@1a14a000 { 413 pciephy1: t-phy@1a14a000 {
414 compatible = "mediatek 414 compatible = "mediatek,mt7629-tphy",
415 "mediatek 415 "mediatek,generic-tphy-v2";
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <1>; 417 #size-cells = <1>;
418 ranges = <0 0x1a14a000 418 ranges = <0 0x1a14a000 0x1000>;
419 status = "disabled"; 419 status = "disabled";
420 420
421 pcieport1: pcie-phy@0 421 pcieport1: pcie-phy@0 {
422 reg = <0 0x100 422 reg = <0 0x1000>;
423 clocks = <&clk 423 clocks = <&clk20m>;
424 clock-names = 424 clock-names = "ref";
425 #phy-cells = < 425 #phy-cells = <1>;
426 status = "okay 426 status = "okay";
427 }; 427 };
428 }; 428 };
429 429
430 ethsys: syscon@1b000000 { 430 ethsys: syscon@1b000000 {
431 compatible = "mediatek 431 compatible = "mediatek,mt7629-ethsys", "syscon";
432 reg = <0x1b000000 0x10 432 reg = <0x1b000000 0x1000>;
433 #clock-cells = <1>; 433 #clock-cells = <1>;
434 #reset-cells = <1>; 434 #reset-cells = <1>;
435 }; 435 };
436 436
437 eth: ethernet@1b100000 { 437 eth: ethernet@1b100000 {
438 compatible = "mediatek 438 compatible = "mediatek,mt7629-eth","syscon";
439 reg = <0x1b100000 0x20 439 reg = <0x1b100000 0x20000>;
440 interrupts = <GIC_SPI 440 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
441 <GIC_SPI 441 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
442 <GIC_SPI 442 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&topckgen CL 443 clocks = <&topckgen CLK_TOP_ETH_SEL>,
444 <&topckgen CL 444 <&topckgen CLK_TOP_F10M_REF_SEL>,
445 <ðsys CLK_ 445 <ðsys CLK_ETH_ESW_EN>,
446 <ðsys CLK_ 446 <ðsys CLK_ETH_GP0_EN>,
447 <ðsys CLK_ 447 <ðsys CLK_ETH_GP1_EN>,
448 <ðsys CLK_ 448 <ðsys CLK_ETH_GP2_EN>,
449 <ðsys CLK_ 449 <ðsys CLK_ETH_FE_EN>,
450 <&sgmiisys0 C 450 <&sgmiisys0 CLK_SGMII_TX_EN>,
451 <&sgmiisys0 C 451 <&sgmiisys0 CLK_SGMII_RX_EN>,
452 <&sgmiisys0 C 452 <&sgmiisys0 CLK_SGMII_CDR_REF>,
453 <&sgmiisys0 C 453 <&sgmiisys0 CLK_SGMII_CDR_FB>,
454 <&sgmiisys1 C 454 <&sgmiisys1 CLK_SGMII_TX_EN>,
455 <&sgmiisys1 C 455 <&sgmiisys1 CLK_SGMII_RX_EN>,
456 <&sgmiisys1 C 456 <&sgmiisys1 CLK_SGMII_CDR_REF>,
457 <&sgmiisys1 C 457 <&sgmiisys1 CLK_SGMII_CDR_FB>,
458 <&apmixedsys 458 <&apmixedsys CLK_APMIXED_SGMIPLL>,
459 <&apmixedsys 459 <&apmixedsys CLK_APMIXED_ETH2PLL>;
460 clock-names = "ethif", 460 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
461 "gp2", " 461 "gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
462 "sgmii_c 462 "sgmii_cdr_ref", "sgmii_cdr_fb",
463 "sgmii2_ 463 "sgmii2_tx250m", "sgmii2_rx250m",
464 "sgmii2_ 464 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
465 "sgmii_c 465 "sgmii_ck", "eth2pll";
466 assigned-clocks = <&to 466 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
467 <&to 467 <&topckgen CLK_TOP_F10M_REF_SEL>;
468 assigned-clock-parents 468 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
469 469 <&topckgen CLK_TOP_SGMIIPLL_D2>;
470 power-domains = <&scps 470 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
471 mediatek,ethsys = <&et 471 mediatek,ethsys = <ðsys>;
472 mediatek,sgmiisys = <& 472 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
473 mediatek,infracfg = <& 473 mediatek,infracfg = <&infracfg>;
474 #address-cells = <1>; 474 #address-cells = <1>;
475 #size-cells = <0>; 475 #size-cells = <0>;
476 status = "disabled"; 476 status = "disabled";
477 }; 477 };
478 478
479 sgmiisys0: syscon@1b128000 { 479 sgmiisys0: syscon@1b128000 {
480 compatible = "mediatek 480 compatible = "mediatek,mt7629-sgmiisys", "syscon";
481 reg = <0x1b128000 0x30 481 reg = <0x1b128000 0x3000>;
482 #clock-cells = <1>; 482 #clock-cells = <1>;
483 }; 483 };
484 484
485 sgmiisys1: syscon@1b130000 { 485 sgmiisys1: syscon@1b130000 {
486 compatible = "mediatek 486 compatible = "mediatek,mt7629-sgmiisys", "syscon";
487 reg = <0x1b130000 0x30 487 reg = <0x1b130000 0x3000>;
488 #clock-cells = <1>; 488 #clock-cells = <1>;
489 }; 489 };
490 }; 490 };
491 }; 491 };
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