1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * at91sam9g45.dtsi - Device Tree Include file 3 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
4 * applies to AT91SAM9G45, 4 * applies to AT91SAM9G45, AT91SAM9M10,
5 * AT91SAM9G46, AT91SAM9M11 5 * AT91SAM9G46, AT91SAM9M11 SoC
6 * 6 *
7 * Copyright (C) 2011 Atmel, 7 * Copyright (C) 2011 Atmel,
8 * 2011 Nicolas Ferre <nicolas.f 8 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
9 */ 9 */
10 10
11 #include <dt-bindings/dma/at91.h> 11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h> 12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq 13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h> 15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h> 16 #include <dt-bindings/mfd/at91-usart.h>
17 17
18 / { 18 / {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <1>; 20 #size-cells = <1>;
21 model = "Atmel AT91SAM9G45 family SoC" 21 model = "Atmel AT91SAM9G45 family SoC";
22 compatible = "atmel,at91sam9g45"; 22 compatible = "atmel,at91sam9g45";
23 interrupt-parent = <&aic>; 23 interrupt-parent = <&aic>;
24 24
25 aliases { 25 aliases {
26 serial0 = &dbgu; 26 serial0 = &dbgu;
27 serial1 = &usart0; 27 serial1 = &usart0;
28 serial2 = &usart1; 28 serial2 = &usart1;
29 serial3 = &usart2; 29 serial3 = &usart2;
30 serial4 = &usart3; 30 serial4 = &usart3;
31 gpio0 = &pioA; 31 gpio0 = &pioA;
32 gpio1 = &pioB; 32 gpio1 = &pioB;
33 gpio2 = &pioC; 33 gpio2 = &pioC;
34 gpio3 = &pioD; 34 gpio3 = &pioD;
35 gpio4 = &pioE; 35 gpio4 = &pioE;
36 tcb0 = &tcb0; 36 tcb0 = &tcb0;
37 tcb1 = &tcb1; 37 tcb1 = &tcb1;
38 i2c0 = &i2c0; 38 i2c0 = &i2c0;
39 i2c1 = &i2c1; 39 i2c1 = &i2c1;
40 ssc0 = &ssc0; 40 ssc0 = &ssc0;
41 ssc1 = &ssc1; 41 ssc1 = &ssc1;
42 pwm0 = &pwm0; 42 pwm0 = &pwm0;
43 }; 43 };
44 cpus { 44 cpus {
45 #address-cells = <1>; 45 #address-cells = <1>;
46 #size-cells = <0>; 46 #size-cells = <0>;
47 47
48 cpu@0 { 48 cpu@0 {
49 compatible = "arm,arm9 49 compatible = "arm,arm926ej-s";
50 device_type = "cpu"; 50 device_type = "cpu";
51 reg = <0>; 51 reg = <0>;
52 }; 52 };
53 }; 53 };
54 54
55 memory@70000000 { 55 memory@70000000 {
56 device_type = "memory"; 56 device_type = "memory";
57 reg = <0x70000000 0x10000000>; 57 reg = <0x70000000 0x10000000>;
58 }; 58 };
59 59
60 clocks { 60 clocks {
61 slow_xtal: slow_xtal { 61 slow_xtal: slow_xtal {
62 compatible = "fixed-cl 62 compatible = "fixed-clock";
63 #clock-cells = <0>; 63 #clock-cells = <0>;
64 clock-frequency = <0>; 64 clock-frequency = <0>;
65 }; 65 };
66 66
67 main_xtal: main_xtal { 67 main_xtal: main_xtal {
68 compatible = "fixed-cl 68 compatible = "fixed-clock";
69 #clock-cells = <0>; 69 #clock-cells = <0>;
70 clock-frequency = <0>; 70 clock-frequency = <0>;
71 }; 71 };
72 72
73 adc_op_clk: adc_op_clk { 73 adc_op_clk: adc_op_clk {
74 compatible = "fixed-cl 74 compatible = "fixed-clock";
75 #clock-cells = <0>; 75 #clock-cells = <0>;
76 clock-frequency = <300 76 clock-frequency = <300000>;
77 }; 77 };
78 }; 78 };
79 79
80 sram: sram@300000 { 80 sram: sram@300000 {
81 compatible = "mmio-sram"; 81 compatible = "mmio-sram";
82 reg = <0x00300000 0x10000>; 82 reg = <0x00300000 0x10000>;
83 #address-cells = <1>; 83 #address-cells = <1>;
84 #size-cells = <1>; 84 #size-cells = <1>;
85 ranges = <0 0x00300000 0x10000 85 ranges = <0 0x00300000 0x10000>;
86 }; 86 };
87 87
88 ahb { 88 ahb {
89 compatible = "simple-bus"; 89 compatible = "simple-bus";
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <1>; 91 #size-cells = <1>;
92 ranges; 92 ranges;
93 93
94 apb { 94 apb {
95 compatible = "simple-b 95 compatible = "simple-bus";
96 #address-cells = <1>; 96 #address-cells = <1>;
97 #size-cells = <1>; 97 #size-cells = <1>;
98 ranges; 98 ranges;
99 99
100 aic: interrupt-control 100 aic: interrupt-controller@fffff000 {
101 #interrupt-cel 101 #interrupt-cells = <3>;
102 compatible = " 102 compatible = "atmel,at91rm9200-aic";
103 interrupt-cont 103 interrupt-controller;
104 reg = <0xfffff 104 reg = <0xfffff000 0x200>;
105 atmel,external 105 atmel,external-irqs = <31>;
106 }; 106 };
107 107
108 ramc0: ramc@ffffe400 { 108 ramc0: ramc@ffffe400 {
109 compatible = " 109 compatible = "atmel,at91sam9g45-ddramc";
110 reg = <0xffffe 110 reg = <0xffffe400 0x200>;
111 clocks = <&pmc 111 clocks = <&pmc PMC_TYPE_SYSTEM 2>;
112 clock-names = 112 clock-names = "ddrck";
113 }; 113 };
114 114
115 ramc1: ramc@ffffe600 { 115 ramc1: ramc@ffffe600 {
116 compatible = " 116 compatible = "atmel,at91sam9g45-ddramc";
117 reg = <0xffffe 117 reg = <0xffffe600 0x200>;
118 clocks = <&pmc 118 clocks = <&pmc PMC_TYPE_SYSTEM 2>;
119 clock-names = 119 clock-names = "ddrck";
120 }; 120 };
121 121
122 smc: smc@ffffe800 { 122 smc: smc@ffffe800 {
123 compatible = " 123 compatible = "atmel,at91sam9260-smc", "syscon";
124 reg = <0xffffe 124 reg = <0xffffe800 0x200>;
125 }; 125 };
126 126
127 matrix: matrix@ffffea0 127 matrix: matrix@ffffea00 {
128 compatible = " 128 compatible = "atmel,at91sam9g45-matrix", "syscon";
129 reg = <0xffffe 129 reg = <0xffffea00 0x200>;
130 }; 130 };
131 131
132 pmc: clock-controller@ 132 pmc: clock-controller@fffffc00 {
133 compatible = " 133 compatible = "atmel,at91sam9g45-pmc", "syscon";
134 reg = <0xfffff 134 reg = <0xfffffc00 0x100>;
135 interrupts = < 135 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
136 #clock-cells = 136 #clock-cells = <2>;
137 clocks = <&clk 137 clocks = <&clk32k>, <&main_xtal>;
138 clock-names = 138 clock-names = "slow_clk", "main_xtal";
139 }; 139 };
140 140
141 reset-controller@fffff 141 reset-controller@fffffd00 {
142 compatible = " 142 compatible = "atmel,at91sam9g45-rstc";
143 reg = <0xfffff 143 reg = <0xfffffd00 0x10>;
144 clocks = <&clk 144 clocks = <&clk32k>;
145 }; 145 };
146 146
147 pit: timer@fffffd30 { 147 pit: timer@fffffd30 {
148 compatible = " 148 compatible = "atmel,at91sam9260-pit";
149 reg = <0xfffff 149 reg = <0xfffffd30 0xf>;
150 interrupts = < 150 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
151 clocks = <&pmc 151 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
152 }; 152 };
153 153
154 154
155 poweroff@fffffd10 { 155 poweroff@fffffd10 {
156 compatible = " 156 compatible = "atmel,at91sam9rl-shdwc";
157 reg = <0xfffff 157 reg = <0xfffffd10 0x10>;
158 clocks = <&clk 158 clocks = <&clk32k>;
159 }; 159 };
160 160
161 tcb0: timer@fff7c000 { 161 tcb0: timer@fff7c000 {
162 compatible = " 162 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
163 #address-cells 163 #address-cells = <1>;
164 #size-cells = 164 #size-cells = <0>;
165 reg = <0xfff7c 165 reg = <0xfff7c000 0x100>;
166 interrupts = < 166 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
167 clocks = <&pmc 167 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
168 clock-names = 168 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
169 }; 169 };
170 170
171 tcb1: timer@fffd4000 { 171 tcb1: timer@fffd4000 {
172 compatible = " 172 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
173 #address-cells 173 #address-cells = <1>;
174 #size-cells = 174 #size-cells = <0>;
175 reg = <0xfffd4 175 reg = <0xfffd4000 0x100>;
176 interrupts = < 176 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
177 clocks = <&pmc 177 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>;
178 clock-names = 178 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
179 }; 179 };
180 180
181 dma: dma-controller@ff 181 dma: dma-controller@ffffec00 {
182 compatible = " 182 compatible = "atmel,at91sam9g45-dma";
183 reg = <0xffffe 183 reg = <0xffffec00 0x200>;
184 interrupts = < 184 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
185 #dma-cells = < 185 #dma-cells = <2>;
186 clocks = <&pmc 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
187 clock-names = 187 clock-names = "dma_clk";
188 }; 188 };
189 189
190 pinctrl@fffff200 { 190 pinctrl@fffff200 {
191 #address-cells 191 #address-cells = <1>;
192 #size-cells = 192 #size-cells = <1>;
193 compatible = " 193 compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
194 ranges = <0xff 194 ranges = <0xfffff200 0xfffff200 0xa00>;
195 195
196 atmel,mux-mask 196 atmel,mux-mask = <
197 /* A 197 /* A B */
198 0xfffff 198 0xffffffff 0xffc003ff /* pioA */
199 0xfffff 199 0xffffffff 0x800f8f00 /* pioB */
200 0xfffff 200 0xffffffff 0x00000e00 /* pioC */
201 0xfffff 201 0xffffffff 0xff0c1381 /* pioD */
202 0xfffff 202 0xffffffff 0x81ffff81 /* pioE */
203 >; 203 >;
204 204
205 /* shared pinc 205 /* shared pinctrl settings */
206 ac97 { 206 ac97 {
207 pinctr 207 pinctrl_ac97: ac97-0 {
208 208 atmel,pins =
209 209 <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97RX */
210 210 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97TX */
211 211 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* AC97FS */
212 212 AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* AC97CK */
213 }; 213 };
214 }; 214 };
215 215
216 adc0 { 216 adc0 {
217 pinctr 217 pinctrl_adc0_adtrg: adc0_adtrg {
218 218 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
219 }; 219 };
220 pinctr 220 pinctrl_adc0_ad0: adc0_ad0 {
221 221 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
222 }; 222 };
223 pinctr 223 pinctrl_adc0_ad1: adc0_ad1 {
224 224 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
225 }; 225 };
226 pinctr 226 pinctrl_adc0_ad2: adc0_ad2 {
227 227 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
228 }; 228 };
229 pinctr 229 pinctrl_adc0_ad3: adc0_ad3 {
230 230 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
231 }; 231 };
232 pinctr 232 pinctrl_adc0_ad4: adc0_ad4 {
233 233 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
234 }; 234 };
235 pinctr 235 pinctrl_adc0_ad5: adc0_ad5 {
236 236 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
237 }; 237 };
238 pinctr 238 pinctrl_adc0_ad6: adc0_ad6 {
239 239 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
240 }; 240 };
241 pinctr 241 pinctrl_adc0_ad7: adc0_ad7 {
242 242 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
243 }; 243 };
244 }; 244 };
245 245
246 dbgu { 246 dbgu {
247 pinctr 247 pinctrl_dbgu: dbgu-0 {
248 248 atmel,pins =
249 249 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
250 250 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
251 }; 251 };
252 }; 252 };
253 253
254 i2c0 { 254 i2c0 {
255 pinctr 255 pinctrl_i2c0: i2c0-0 {
256 256 atmel,pins =
257 257 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
258 258 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
259 }; 259 };
260 }; 260 };
261 261
262 i2c1 { 262 i2c1 {
263 pinctr 263 pinctrl_i2c1: i2c1-0 {
264 264 atmel,pins =
265 265 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
266 266 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
267 }; 267 };
268 }; 268 };
269 269
270 isi { 270 isi {
271 pinctr 271 pinctrl_isi_data_0_7: isi-0-data-0-7 {
272 272 atmel,pins =
273 273 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
274 274 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
275 275 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
276 276 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
277 277 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
278 278 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
279 279 AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
280 280 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
281 281 AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
282 282 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
283 283 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
284 }; 284 };
285 285
286 pinctr 286 pinctrl_isi_data_8_9: isi-0-data-8-9 {
287 287 atmel,pins =
288 288 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
289 289 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
290 }; 290 };
291 291
292 pinctr 292 pinctrl_isi_data_10_11: isi-0-data-10-11 {
293 293 atmel,pins =
294 294 <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
295 295 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
296 }; 296 };
297 }; 297 };
298 298
299 usart0 { 299 usart0 {
300 pinctr 300 pinctrl_usart0: usart0-0 {
301 301 atmel,pins =
302 302 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
303 303 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
304 }; 304 };
305 305
306 pinctr 306 pinctrl_usart0_rts: usart0_rts-0 {
307 307 atmel,pins =
308 308 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
309 }; 309 };
310 310
311 pinctr 311 pinctrl_usart0_cts: usart0_cts-0 {
312 312 atmel,pins =
313 313 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
314 }; 314 };
315 }; 315 };
316 316
317 usart1 { 317 usart1 {
318 pinctr 318 pinctrl_usart1: usart1-0 {
319 319 atmel,pins =
320 320 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
321 321 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
322 }; 322 };
323 323
324 pinctr 324 pinctrl_usart1_rts: usart1_rts-0 {
325 325 atmel,pins =
326 326 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
327 }; 327 };
328 328
329 pinctr 329 pinctrl_usart1_cts: usart1_cts-0 {
330 330 atmel,pins =
331 331 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
332 }; 332 };
333 }; 333 };
334 334
335 usart2 { 335 usart2 {
336 pinctr 336 pinctrl_usart2: usart2-0 {
337 337 atmel,pins =
338 338 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
339 339 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
340 }; 340 };
341 341
342 pinctr 342 pinctrl_usart2_rts: usart2_rts-0 {
343 343 atmel,pins =
344 344 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
345 }; 345 };
346 346
347 pinctr 347 pinctrl_usart2_cts: usart2_cts-0 {
348 348 atmel,pins =
349 349 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
350 }; 350 };
351 }; 351 };
352 352
353 usart3 { 353 usart3 {
354 pinctr 354 pinctrl_usart3: usart3-0 {
355 355 atmel,pins =
356 356 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
357 357 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
358 }; 358 };
359 359
360 pinctr 360 pinctrl_usart3_rts: usart3_rts-0 {
361 361 atmel,pins =
362 362 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
363 }; 363 };
364 364
365 pinctr 365 pinctrl_usart3_cts: usart3_cts-0 {
366 366 atmel,pins =
367 367 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
368 }; 368 };
369 }; 369 };
370 370
371 nand { 371 nand {
372 pinctr 372 pinctrl_nand_rb: nand-rb-0 {
373 373 atmel,pins =
374 374 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
375 }; 375 };
376 376
377 pinctr 377 pinctrl_nand_cs: nand-cs-0 {
378 378 atmel,pins =
379 379 <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
380 }; 380 };
381 }; 381 };
382 382
383 macb { 383 macb {
384 pinctr 384 pinctrl_macb_rmii: macb_rmii-0 {
385 385 atmel,pins =
386 386 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
387 387 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
388 388 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
389 389 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
390 390 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
391 391 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
392 392 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
393 393 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
394 394 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
395 395 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
396 }; 396 };
397 397
398 pinctr 398 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
399 399 atmel,pins =
400 400 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
401 401 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
402 402 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
403 403 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
404 404 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
405 405 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
406 406 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
407 407 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
408 }; 408 };
409 }; 409 };
410 410
411 mmc0 { 411 mmc0 {
412 pinctr 412 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
413 413 atmel,pins =
414 414 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
415 415 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
416 416 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
417 }; 417 };
418 418
419 pinctr 419 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
420 420 atmel,pins =
421 421 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
422 422 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
423 423 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
424 }; 424 };
425 425
426 pinctr 426 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
427 427 atmel,pins =
428 428 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
429 429 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
430 430 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
431 431 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
432 }; 432 };
433 }; 433 };
434 434
435 mmc1 { 435 mmc1 {
436 pinctr 436 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
437 437 atmel,pins =
438 438 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
439 439 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
440 440 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
441 }; 441 };
442 442
443 pinctr 443 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
444 444 atmel,pins =
445 445 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
446 446 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
447 447 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
448 }; 448 };
449 449
450 pinctr 450 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
451 451 atmel,pins =
452 452 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
453 453 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
454 454 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
455 455 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
456 }; 456 };
457 }; 457 };
458 458
459 ssc0 { 459 ssc0 {
460 pinctr 460 pinctrl_ssc0_tx: ssc0_tx-0 {
461 461 atmel,pins =
462 462 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
463 463 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
464 464 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
465 }; 465 };
466 466
467 pinctr 467 pinctrl_ssc0_rx: ssc0_rx-0 {
468 468 atmel,pins =
469 469 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
470 470 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
471 471 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
472 }; 472 };
473 }; 473 };
474 474
475 ssc1 { 475 ssc1 {
476 pinctr 476 pinctrl_ssc1_tx: ssc1_tx-0 {
477 477 atmel,pins =
478 478 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
479 479 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
480 480 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
481 }; 481 };
482 482
483 pinctr 483 pinctrl_ssc1_rx: ssc1_rx-0 {
484 484 atmel,pins =
485 485 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
486 486 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
487 487 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
488 }; 488 };
489 }; 489 };
490 490
491 spi0 { 491 spi0 {
492 pinctr 492 pinctrl_spi0: spi0-0 {
493 493 atmel,pins =
494 494 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
495 495 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
496 496 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
497 }; 497 };
498 }; 498 };
499 499
500 spi1 { 500 spi1 {
501 pinctr 501 pinctrl_spi1: spi1-0 {
502 502 atmel,pins =
503 503 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
504 504 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
505 505 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
506 }; 506 };
507 }; 507 };
508 508
509 tcb0 { 509 tcb0 {
510 pinctr 510 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
511 511 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
512 }; 512 };
513 513
514 pinctr 514 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
515 515 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
516 }; 516 };
517 517
518 pinctr 518 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
519 519 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
520 }; 520 };
521 521
522 pinctr 522 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
523 523 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
524 }; 524 };
525 525
526 pinctr 526 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
527 527 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
528 }; 528 };
529 529
530 pinctr 530 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
531 531 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
532 }; 532 };
533 533
534 pinctr 534 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
535 535 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
536 }; 536 };
537 537
538 pinctr 538 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
539 539 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
540 }; 540 };
541 541
542 pinctr 542 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
543 543 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
544 }; 544 };
545 }; 545 };
546 546
547 tcb1 { 547 tcb1 {
548 pinctr 548 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
549 549 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
550 }; 550 };
551 551
552 pinctr 552 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
553 553 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
554 }; 554 };
555 555
556 pinctr 556 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
557 557 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
558 }; 558 };
559 559
560 pinctr 560 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
561 561 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
562 }; 562 };
563 563
564 pinctr 564 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
565 565 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
566 }; 566 };
567 567
568 pinctr 568 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
569 569 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
570 }; 570 };
571 571
572 pinctr 572 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
573 573 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
574 }; 574 };
575 575
576 pinctr 576 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
577 577 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
578 }; 578 };
579 579
580 pinctr 580 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
581 581 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
582 }; 582 };
583 }; 583 };
584 584
585 fb { 585 fb {
586 pinctr 586 pinctrl_fb: fb-0 {
587 587 atmel,pins =
588 588 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
589 589 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
590 590 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
591 591 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
592 592 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
593 593 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
594 594 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
595 595 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
596 596 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
597 597 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
598 598 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
599 599 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
600 600 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
601 601 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
602 602 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
603 603 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
604 604 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
605 605 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
606 606 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
607 607 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
608 608 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
609 609 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
610 610 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
611 611 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
612 612 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
613 613 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
614 614 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
615 615 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
616 616 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
617 617 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
618 }; 618 };
619 }; 619 };
620 620
621 pioA: gpio@fff 621 pioA: gpio@fffff200 {
622 compat 622 compatible = "atmel,at91rm9200-gpio";
623 reg = 623 reg = <0xfffff200 0x200>;
624 interr 624 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
625 #gpio- 625 #gpio-cells = <2>;
626 gpio-c 626 gpio-controller;
627 interr 627 interrupt-controller;
628 #inter 628 #interrupt-cells = <2>;
629 clocks 629 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
630 }; 630 };
631 631
632 pioB: gpio@fff 632 pioB: gpio@fffff400 {
633 compat 633 compatible = "atmel,at91rm9200-gpio";
634 reg = 634 reg = <0xfffff400 0x200>;
635 interr 635 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
636 #gpio- 636 #gpio-cells = <2>;
637 gpio-c 637 gpio-controller;
638 interr 638 interrupt-controller;
639 #inter 639 #interrupt-cells = <2>;
640 clocks 640 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
641 }; 641 };
642 642
643 pioC: gpio@fff 643 pioC: gpio@fffff600 {
644 compat 644 compatible = "atmel,at91rm9200-gpio";
645 reg = 645 reg = <0xfffff600 0x200>;
646 interr 646 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
647 #gpio- 647 #gpio-cells = <2>;
648 gpio-c 648 gpio-controller;
649 interr 649 interrupt-controller;
650 #inter 650 #interrupt-cells = <2>;
651 clocks 651 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
652 }; 652 };
653 653
654 pioD: gpio@fff 654 pioD: gpio@fffff800 {
655 compat 655 compatible = "atmel,at91rm9200-gpio";
656 reg = 656 reg = <0xfffff800 0x200>;
657 interr 657 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
658 #gpio- 658 #gpio-cells = <2>;
659 gpio-c 659 gpio-controller;
660 interr 660 interrupt-controller;
661 #inter 661 #interrupt-cells = <2>;
662 clocks 662 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
663 }; 663 };
664 664
665 pioE: gpio@fff 665 pioE: gpio@fffffa00 {
666 compat 666 compatible = "atmel,at91rm9200-gpio";
667 reg = 667 reg = <0xfffffa00 0x200>;
668 interr 668 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
669 #gpio- 669 #gpio-cells = <2>;
670 gpio-c 670 gpio-controller;
671 interr 671 interrupt-controller;
672 #inter 672 #interrupt-cells = <2>;
673 clocks 673 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
674 }; 674 };
675 }; 675 };
676 676
677 dbgu: serial@ffffee00 677 dbgu: serial@ffffee00 {
678 compatible = " 678 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
679 atmel,usart-mo 679 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
680 reg = <0xffffe 680 reg = <0xffffee00 0x200>;
681 interrupts = < 681 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
682 pinctrl-names 682 pinctrl-names = "default";
683 pinctrl-0 = <& 683 pinctrl-0 = <&pinctrl_dbgu>;
684 clocks = <&pmc 684 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
685 clock-names = 685 clock-names = "usart";
686 status = "disa 686 status = "disabled";
687 }; 687 };
688 688
689 usart0: serial@fff8c00 689 usart0: serial@fff8c000 {
690 compatible = " 690 compatible = "atmel,at91sam9260-usart";
691 reg = <0xfff8c 691 reg = <0xfff8c000 0x200>;
692 atmel,usart-mo 692 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
693 interrupts = < 693 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
694 atmel,use-dma- 694 atmel,use-dma-rx;
695 atmel,use-dma- 695 atmel,use-dma-tx;
696 pinctrl-names 696 pinctrl-names = "default";
697 pinctrl-0 = <& 697 pinctrl-0 = <&pinctrl_usart0>;
698 clocks = <&pmc 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
699 clock-names = 699 clock-names = "usart";
700 status = "disa 700 status = "disabled";
701 }; 701 };
702 702
703 usart1: serial@fff9000 703 usart1: serial@fff90000 {
704 compatible = " 704 compatible = "atmel,at91sam9260-usart";
705 reg = <0xfff90 705 reg = <0xfff90000 0x200>;
706 atmel,usart-mo 706 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
707 interrupts = < 707 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
708 atmel,use-dma- 708 atmel,use-dma-rx;
709 atmel,use-dma- 709 atmel,use-dma-tx;
710 pinctrl-names 710 pinctrl-names = "default";
711 pinctrl-0 = <& 711 pinctrl-0 = <&pinctrl_usart1>;
712 clocks = <&pmc 712 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
713 clock-names = 713 clock-names = "usart";
714 status = "disa 714 status = "disabled";
715 }; 715 };
716 716
717 usart2: serial@fff9400 717 usart2: serial@fff94000 {
718 compatible = " 718 compatible = "atmel,at91sam9260-usart";
719 reg = <0xfff94 719 reg = <0xfff94000 0x200>;
720 atmel,usart-mo 720 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
721 interrupts = < 721 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
722 atmel,use-dma- 722 atmel,use-dma-rx;
723 atmel,use-dma- 723 atmel,use-dma-tx;
724 pinctrl-names 724 pinctrl-names = "default";
725 pinctrl-0 = <& 725 pinctrl-0 = <&pinctrl_usart2>;
726 clocks = <&pmc 726 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
727 clock-names = 727 clock-names = "usart";
728 status = "disa 728 status = "disabled";
729 }; 729 };
730 730
731 usart3: serial@fff9800 731 usart3: serial@fff98000 {
732 compatible = " 732 compatible = "atmel,at91sam9260-usart";
733 reg = <0xfff98 733 reg = <0xfff98000 0x200>;
734 atmel,usart-mo 734 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
735 interrupts = < 735 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
736 atmel,use-dma- 736 atmel,use-dma-rx;
737 atmel,use-dma- 737 atmel,use-dma-tx;
738 pinctrl-names 738 pinctrl-names = "default";
739 pinctrl-0 = <& 739 pinctrl-0 = <&pinctrl_usart3>;
740 clocks = <&pmc 740 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
741 clock-names = 741 clock-names = "usart";
742 status = "disa 742 status = "disabled";
743 }; 743 };
744 744
745 macb0: ethernet@fffbc0 745 macb0: ethernet@fffbc000 {
746 compatible = " 746 compatible = "cdns,at91sam9260-macb", "cdns,macb";
747 reg = <0xfffbc 747 reg = <0xfffbc000 0x100>;
748 interrupts = < 748 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
749 pinctrl-names 749 pinctrl-names = "default";
750 pinctrl-0 = <& 750 pinctrl-0 = <&pinctrl_macb_rmii>;
751 clocks = <&pmc 751 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>;
752 clock-names = 752 clock-names = "hclk", "pclk";
753 status = "disa 753 status = "disabled";
754 }; 754 };
755 755
756 trng@fffcc000 { 756 trng@fffcc000 {
757 compatible = " 757 compatible = "atmel,at91sam9g45-trng";
758 reg = <0xfffcc 758 reg = <0xfffcc000 0x100>;
759 interrupts = < 759 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
760 clocks = <&pmc 760 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
761 }; 761 };
762 762
763 i2c0: i2c@fff84000 { 763 i2c0: i2c@fff84000 {
764 compatible = " 764 compatible = "atmel,at91sam9g10-i2c";
765 reg = <0xfff84 765 reg = <0xfff84000 0x100>;
766 interrupts = < 766 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
767 pinctrl-names 767 pinctrl-names = "default";
768 pinctrl-0 = <& 768 pinctrl-0 = <&pinctrl_i2c0>;
769 #address-cells 769 #address-cells = <1>;
770 #size-cells = 770 #size-cells = <0>;
771 clocks = <&pmc 771 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
772 status = "disa 772 status = "disabled";
773 }; 773 };
774 774
775 i2c1: i2c@fff88000 { 775 i2c1: i2c@fff88000 {
776 compatible = " 776 compatible = "atmel,at91sam9g10-i2c";
777 reg = <0xfff88 777 reg = <0xfff88000 0x100>;
778 interrupts = < 778 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
779 pinctrl-names 779 pinctrl-names = "default";
780 pinctrl-0 = <& 780 pinctrl-0 = <&pinctrl_i2c1>;
781 #address-cells 781 #address-cells = <1>;
782 #size-cells = 782 #size-cells = <0>;
783 clocks = <&pmc 783 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
784 status = "disa 784 status = "disabled";
785 }; 785 };
786 786
787 ssc0: ssc@fff9c000 { 787 ssc0: ssc@fff9c000 {
788 compatible = " 788 compatible = "atmel,at91sam9g45-ssc";
789 reg = <0xfff9c 789 reg = <0xfff9c000 0x4000>;
790 interrupts = < 790 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
791 pinctrl-names 791 pinctrl-names = "default";
792 pinctrl-0 = <& 792 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
793 clocks = <&pmc 793 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
794 clock-names = 794 clock-names = "pclk";
795 status = "disa 795 status = "disabled";
796 }; 796 };
797 797
798 ssc1: ssc@fffa0000 { 798 ssc1: ssc@fffa0000 {
799 compatible = " 799 compatible = "atmel,at91sam9g45-ssc";
800 reg = <0xfffa0 800 reg = <0xfffa0000 0x4000>;
801 interrupts = < 801 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
802 pinctrl-names 802 pinctrl-names = "default";
803 pinctrl-0 = <& 803 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
804 clocks = <&pmc 804 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
805 clock-names = 805 clock-names = "pclk";
806 status = "disa 806 status = "disabled";
807 }; 807 };
808 808
809 ac97: sound@fffac000 { 809 ac97: sound@fffac000 {
810 compatible = " 810 compatible = "atmel,at91sam9263-ac97c";
811 reg = <0xfffac 811 reg = <0xfffac000 0x4000>;
812 interrupts = < 812 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>;
813 pinctrl-names 813 pinctrl-names = "default";
814 pinctrl-0 = <& 814 pinctrl-0 = <&pinctrl_ac97>;
815 clocks = <&pmc 815 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
816 clock-names = 816 clock-names = "ac97_clk";
817 status = "disa 817 status = "disabled";
818 }; 818 };
819 819
820 adc0: adc@fffb0000 { 820 adc0: adc@fffb0000 {
821 compatible = " 821 compatible = "atmel,at91sam9g45-adc";
822 reg = <0xfffb0 822 reg = <0xfffb0000 0x100>;
823 interrupts = < 823 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
824 clocks = <&pmc 824 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>;
825 clock-names = 825 clock-names = "adc_clk", "adc_op_clk";
826 atmel,adc-chan 826 atmel,adc-channels-used = <0xff>;
827 atmel,adc-vref 827 atmel,adc-vref = <3300>;
828 atmel,adc-star 828 atmel,adc-startup-time = <40>;
829 }; 829 };
830 830
831 isi@fffb4000 { 831 isi@fffb4000 {
832 compatible = " 832 compatible = "atmel,at91sam9g45-isi";
833 reg = <0xfffb4 833 reg = <0xfffb4000 0x4000>;
834 interrupts = < 834 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
835 clocks = <&pmc 835 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
836 clock-names = 836 clock-names = "isi_clk";
837 status = "disa 837 status = "disabled";
838 port { 838 port {
839 #addre 839 #address-cells = <1>;
840 #size- 840 #size-cells = <0>;
841 }; 841 };
842 }; 842 };
843 843
844 pwm0: pwm@fffb8000 { 844 pwm0: pwm@fffb8000 {
845 compatible = " 845 compatible = "atmel,at91sam9rl-pwm";
846 reg = <0xfffb8 846 reg = <0xfffb8000 0x300>;
847 interrupts = < 847 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
848 #pwm-cells = < 848 #pwm-cells = <3>;
849 clocks = <&pmc 849 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
850 status = "disa 850 status = "disabled";
851 }; 851 };
852 852
853 mmc0: mmc@fff80000 { 853 mmc0: mmc@fff80000 {
854 compatible = " 854 compatible = "atmel,hsmci";
855 reg = <0xfff80 855 reg = <0xfff80000 0x600>;
856 interrupts = < 856 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
857 dmas = <&dma 1 857 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
858 dma-names = "r 858 dma-names = "rxtx";
859 #address-cells 859 #address-cells = <1>;
860 #size-cells = 860 #size-cells = <0>;
861 clocks = <&pmc 861 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
862 clock-names = 862 clock-names = "mci_clk";
863 status = "disa 863 status = "disabled";
864 }; 864 };
865 865
866 mmc1: mmc@fffd0000 { 866 mmc1: mmc@fffd0000 {
867 compatible = " 867 compatible = "atmel,hsmci";
868 reg = <0xfffd0 868 reg = <0xfffd0000 0x600>;
869 interrupts = < 869 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
870 dmas = <&dma 1 870 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
871 dma-names = "r 871 dma-names = "rxtx";
872 #address-cells 872 #address-cells = <1>;
873 #size-cells = 873 #size-cells = <0>;
874 clocks = <&pmc 874 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
875 clock-names = 875 clock-names = "mci_clk";
876 status = "disa 876 status = "disabled";
877 }; 877 };
878 878
879 watchdog@fffffd40 { 879 watchdog@fffffd40 {
880 compatible = " 880 compatible = "atmel,at91sam9260-wdt";
881 reg = <0xfffff 881 reg = <0xfffffd40 0x10>;
882 interrupts = < 882 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
883 clocks = <&clk 883 clocks = <&clk32k>;
884 atmel,watchdog 884 atmel,watchdog-type = "hardware";
885 atmel,reset-ty 885 atmel,reset-type = "all";
886 atmel,dbg-halt 886 atmel,dbg-halt;
887 status = "disa 887 status = "disabled";
888 }; 888 };
889 889
890 spi0: spi@fffa4000 { 890 spi0: spi@fffa4000 {
891 #address-cells 891 #address-cells = <1>;
892 #size-cells = 892 #size-cells = <0>;
893 compatible = " 893 compatible = "atmel,at91rm9200-spi";
894 reg = <0xfffa4 894 reg = <0xfffa4000 0x200>;
895 interrupts = < 895 interrupts = <14 4 3>;
896 pinctrl-names 896 pinctrl-names = "default";
897 pinctrl-0 = <& 897 pinctrl-0 = <&pinctrl_spi0>;
898 clocks = <&pmc 898 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
899 clock-names = 899 clock-names = "spi_clk";
900 status = "disa 900 status = "disabled";
901 }; 901 };
902 902
903 spi1: spi@fffa8000 { 903 spi1: spi@fffa8000 {
904 #address-cells 904 #address-cells = <1>;
905 #size-cells = 905 #size-cells = <0>;
906 compatible = " 906 compatible = "atmel,at91rm9200-spi";
907 reg = <0xfffa8 907 reg = <0xfffa8000 0x200>;
908 interrupts = < 908 interrupts = <15 4 3>;
909 pinctrl-names 909 pinctrl-names = "default";
910 pinctrl-0 = <& 910 pinctrl-0 = <&pinctrl_spi1>;
911 clocks = <&pmc 911 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
912 clock-names = 912 clock-names = "spi_clk";
913 status = "disa 913 status = "disabled";
914 }; 914 };
915 915
916 usb2: gadget@fff78000 916 usb2: gadget@fff78000 {
917 compatible = " 917 compatible = "atmel,at91sam9g45-udc";
918 reg = <0x00600 918 reg = <0x00600000 0x80000
919 0xfff78 919 0xfff78000 0x400>;
920 interrupts = < 920 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
921 clocks = <&pmc 921 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
922 clock-names = 922 clock-names = "pclk", "hclk";
923 status = "disa 923 status = "disabled";
924 }; 924 };
925 925
926 clk32k: clock-controll 926 clk32k: clock-controller@fffffd50 {
927 compatible = " 927 compatible = "atmel,at91sam9x5-sckc";
928 reg = <0xfffff 928 reg = <0xfffffd50 0x4>;
929 clocks = <&slo 929 clocks = <&slow_xtal>;
930 #clock-cells = 930 #clock-cells = <0>;
931 }; 931 };
932 932
933 rtc@fffffd20 { 933 rtc@fffffd20 {
934 compatible = " 934 compatible = "atmel,at91sam9260-rtt";
935 reg = <0xfffff 935 reg = <0xfffffd20 0x10>;
936 interrupts = < 936 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
937 clocks = <&clk 937 clocks = <&clk32k>;
938 status = "disa 938 status = "disabled";
939 }; 939 };
940 940
941 rtc@fffffdb0 { 941 rtc@fffffdb0 {
942 compatible = " 942 compatible = "atmel,at91rm9200-rtc";
943 reg = <0xfffff 943 reg = <0xfffffdb0 0x30>;
944 interrupts = < 944 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
945 clocks = <&clk 945 clocks = <&clk32k>;
946 status = "disa 946 status = "disabled";
947 }; 947 };
948 948
949 gpbr: syscon@fffffd60 949 gpbr: syscon@fffffd60 {
950 compatible = " 950 compatible = "atmel,at91sam9260-gpbr", "syscon";
951 reg = <0xfffff 951 reg = <0xfffffd60 0x10>;
952 status = "disa 952 status = "disabled";
953 }; 953 };
954 }; 954 };
955 955
956 fb0: fb@500000 { 956 fb0: fb@500000 {
957 compatible = "atmel,at 957 compatible = "atmel,at91sam9g45-lcdc";
958 reg = <0x00500000 0x10 958 reg = <0x00500000 0x1000>;
959 interrupts = <23 IRQ_T 959 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
960 pinctrl-names = "defau 960 pinctrl-names = "default";
961 pinctrl-0 = <&pinctrl_ 961 pinctrl-0 = <&pinctrl_fb>;
962 clocks = <&pmc PMC_TYP 962 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>;
963 clock-names = "hclk", 963 clock-names = "hclk", "lcdc_clk";
964 status = "disabled"; 964 status = "disabled";
965 }; 965 };
966 966
967 usb0: ohci@700000 { 967 usb0: ohci@700000 {
968 compatible = "atmel,at 968 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
969 reg = <0x00700000 0x10 969 reg = <0x00700000 0x100000>;
970 interrupts = <22 IRQ_T 970 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
971 clocks = <&pmc PMC_TYP 971 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
972 clock-names = "ohci_cl 972 clock-names = "ohci_clk", "hclk", "uhpck";
973 status = "disabled"; 973 status = "disabled";
974 }; 974 };
975 975
976 usb1: ehci@800000 { 976 usb1: ehci@800000 {
977 compatible = "atmel,at 977 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
978 reg = <0x00800000 0x10 978 reg = <0x00800000 0x100000>;
979 interrupts = <22 IRQ_T 979 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
980 clocks = <&pmc PMC_TYP 980 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
981 clock-names = "usb_clk 981 clock-names = "usb_clk", "ehci_clk";
982 status = "disabled"; 982 status = "disabled";
983 }; 983 };
984 984
985 ebi: ebi@10000000 { 985 ebi: ebi@10000000 {
986 compatible = "atmel,at 986 compatible = "atmel,at91sam9g45-ebi";
987 #address-cells = <2>; 987 #address-cells = <2>;
988 #size-cells = <1>; 988 #size-cells = <1>;
989 atmel,smc = <&smc>; 989 atmel,smc = <&smc>;
990 atmel,matrix = <&matri 990 atmel,matrix = <&matrix>;
991 reg = <0x10000000 0x80 991 reg = <0x10000000 0x80000000>;
992 ranges = <0x0 0x0 0x10 992 ranges = <0x0 0x0 0x10000000 0x10000000
993 0x1 0x0 0x20 993 0x1 0x0 0x20000000 0x10000000
994 0x2 0x0 0x30 994 0x2 0x0 0x30000000 0x10000000
995 0x3 0x0 0x40 995 0x3 0x0 0x40000000 0x10000000
996 0x4 0x0 0x50 996 0x4 0x0 0x50000000 0x10000000
997 0x5 0x0 0x60 997 0x5 0x0 0x60000000 0x10000000>;
998 clocks = <&pmc PMC_TYP 998 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
999 status = "disabled"; 999 status = "disabled";
1000 1000
1001 nand_controller: nand 1001 nand_controller: nand-controller {
1002 compatible = 1002 compatible = "atmel,at91sam9g45-nand-controller";
1003 #address-cell 1003 #address-cells = <2>;
1004 #size-cells = 1004 #size-cells = <1>;
1005 ranges; 1005 ranges;
1006 status = "dis 1006 status = "disabled";
1007 }; 1007 };
1008 }; 1008 };
1009 }; 1009 };
1010 1010
1011 i2c-gpio-0 { 1011 i2c-gpio-0 {
1012 compatible = "i2c-gpio"; 1012 compatible = "i2c-gpio";
1013 gpios = <&pioA 20 GPIO_ACTIVE 1013 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1014 &pioA 21 GPIO_ACTIVE 1014 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1015 >; 1015 >;
1016 i2c-gpio,sda-open-drain; 1016 i2c-gpio,sda-open-drain;
1017 i2c-gpio,scl-open-drain; 1017 i2c-gpio,scl-open-drain;
1018 i2c-gpio,delay-us = <5>; 1018 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1019 #address-cells = <1>; 1019 #address-cells = <1>;
1020 #size-cells = <0>; 1020 #size-cells = <0>;
1021 status = "disabled"; 1021 status = "disabled";
1022 }; 1022 };
1023 }; 1023 };
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