1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * lan966x-pcb8290.dts - Device Tree file for 3 * lan966x-pcb8290.dts - Device Tree file for LAN966X-PCB8290 board
4 * 4 *
5 * Copyright (C) 2022 Microchip Technology Inc 5 * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
6 * 6 *
7 * Author: Horatiu Vultur <horatiu.vultur@micro 7 * Author: Horatiu Vultur <horatiu.vultur@microchip.com>
8 */ 8 */
9 /dts-v1/; 9 /dts-v1/;
10 #include "lan966x.dtsi" 10 #include "lan966x.dtsi"
11 #include "dt-bindings/phy/phy-lan966x-serdes.h 11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
12 12
13 / { 13 / {
14 model = "Microchip EVB LAN9668"; 14 model = "Microchip EVB LAN9668";
15 compatible = "microchip,lan9668-pcb829 15 compatible = "microchip,lan9668-pcb8290", "microchip,lan9668", "microchip,lan966";
16 16
17 gpio-restart { 17 gpio-restart {
18 compatible = "gpio-restart"; 18 compatible = "gpio-restart";
19 gpios = <&gpio 56 GPIO_ACTIVE_ 19 gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
20 priority = <200>; 20 priority = <200>;
21 }; 21 };
22 }; 22 };
23 23
24 &aes { 24 &aes {
25 status = "disabled"; /* Reserved by se 25 status = "disabled"; /* Reserved by secure OS */
26 }; 26 };
27 27
28 &gpio { 28 &gpio {
29 miim_a_pins: mdio-pins { 29 miim_a_pins: mdio-pins {
30 /* MDC, MDIO */ 30 /* MDC, MDIO */
31 pins = "GPIO_28", "GPIO_29"; !! 31 pins = "GPIO_28", "GPIO_29";
32 function = "miim_a"; 32 function = "miim_a";
33 }; 33 };
34 34
35 pps_out_pins: pps-out-pins { 35 pps_out_pins: pps-out-pins {
36 /* 1pps output */ 36 /* 1pps output */
37 pins = "GPIO_38"; 37 pins = "GPIO_38";
38 function = "ptpsync_3"; 38 function = "ptpsync_3";
39 }; 39 };
40 40
41 ptp_ext_pins: ptp-ext-pins { 41 ptp_ext_pins: ptp-ext-pins {
42 /* 1pps input */ 42 /* 1pps input */
43 pins = "GPIO_35"; 43 pins = "GPIO_35";
44 function = "ptpsync_0"; 44 function = "ptpsync_0";
45 }; 45 };
46 46
47 udc_pins: ucd-pins { 47 udc_pins: ucd-pins {
48 /* VBUS_DET B */ 48 /* VBUS_DET B */
49 pins = "GPIO_8"; 49 pins = "GPIO_8";
50 function = "usb_slave_b"; 50 function = "usb_slave_b";
51 }; 51 };
52 }; 52 };
53 53
54 &mdio0 { 54 &mdio0 {
55 pinctrl-0 = <&miim_a_pins>; 55 pinctrl-0 = <&miim_a_pins>;
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
57 status = "okay"; 57 status = "okay";
58 58
59 ext_phy0: ethernet-phy@7 { 59 ext_phy0: ethernet-phy@7 {
60 reg = <7>; 60 reg = <7>;
61 interrupts = <24 IRQ_TYPE_LEVE 61 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
62 interrupt-parent = <&gpio>; 62 interrupt-parent = <&gpio>;
63 coma-mode-gpios = <&gpio 60 GP 63 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
64 }; 64 };
65 65
66 ext_phy1: ethernet-phy@8 { 66 ext_phy1: ethernet-phy@8 {
67 reg = <8>; 67 reg = <8>;
68 interrupts = <24 IRQ_TYPE_LEVE 68 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
69 interrupt-parent = <&gpio>; 69 interrupt-parent = <&gpio>;
70 coma-mode-gpios = <&gpio 60 GP 70 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
71 }; 71 };
72 72
73 ext_phy2: ethernet-phy@9 { 73 ext_phy2: ethernet-phy@9 {
74 reg = <9>; 74 reg = <9>;
75 interrupts = <24 IRQ_TYPE_LEVE 75 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
76 interrupt-parent = <&gpio>; 76 interrupt-parent = <&gpio>;
77 coma-mode-gpios = <&gpio 60 GP 77 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
78 }; 78 };
79 79
80 ext_phy3: ethernet-phy@10 { 80 ext_phy3: ethernet-phy@10 {
81 reg = <10>; 81 reg = <10>;
82 interrupts = <24 IRQ_TYPE_LEVE 82 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
83 interrupt-parent = <&gpio>; 83 interrupt-parent = <&gpio>;
84 coma-mode-gpios = <&gpio 60 GP 84 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
85 }; 85 };
86 86
87 ext_phy4: ethernet-phy@15 { 87 ext_phy4: ethernet-phy@15 {
88 reg = <15>; 88 reg = <15>;
89 interrupts = <24 IRQ_TYPE_LEVE 89 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
90 interrupt-parent = <&gpio>; 90 interrupt-parent = <&gpio>;
91 coma-mode-gpios = <&gpio 60 GP 91 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
92 }; 92 };
93 93
94 ext_phy5: ethernet-phy@16 { 94 ext_phy5: ethernet-phy@16 {
95 reg = <16>; 95 reg = <16>;
96 interrupts = <24 IRQ_TYPE_LEVE 96 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
97 interrupt-parent = <&gpio>; 97 interrupt-parent = <&gpio>;
98 coma-mode-gpios = <&gpio 60 GP 98 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
99 }; 99 };
100 100
101 ext_phy6: ethernet-phy@17 { 101 ext_phy6: ethernet-phy@17 {
102 reg = <17>; 102 reg = <17>;
103 interrupts = <24 IRQ_TYPE_LEVE 103 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
104 interrupt-parent = <&gpio>; 104 interrupt-parent = <&gpio>;
105 coma-mode-gpios = <&gpio 60 GP 105 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
106 }; 106 };
107 107
108 ext_phy7: ethernet-phy@18 { 108 ext_phy7: ethernet-phy@18 {
109 reg = <18>; 109 reg = <18>;
110 interrupts = <24 IRQ_TYPE_LEVE 110 interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
111 interrupt-parent = <&gpio>; 111 interrupt-parent = <&gpio>;
112 coma-mode-gpios = <&gpio 60 GP 112 coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>;
113 }; 113 };
114 }; 114 };
115 115
116 &port0 { 116 &port0 {
117 reg = <2>; 117 reg = <2>;
118 phy-handle = <&ext_phy2>; 118 phy-handle = <&ext_phy2>;
119 phy-mode = "qsgmii"; 119 phy-mode = "qsgmii";
120 phys = <&serdes 0 SERDES6G(1)>; 120 phys = <&serdes 0 SERDES6G(1)>;
121 status = "okay"; 121 status = "okay";
122 }; 122 };
123 123
124 &port1 { 124 &port1 {
125 reg = <3>; 125 reg = <3>;
126 phy-handle = <&ext_phy3>; 126 phy-handle = <&ext_phy3>;
127 phy-mode = "qsgmii"; 127 phy-mode = "qsgmii";
128 phys = <&serdes 1 SERDES6G(1)>; 128 phys = <&serdes 1 SERDES6G(1)>;
129 status = "okay"; 129 status = "okay";
130 }; 130 };
131 131
132 &port2 { 132 &port2 {
133 reg = <0>; 133 reg = <0>;
134 phy-handle = <&ext_phy0>; 134 phy-handle = <&ext_phy0>;
135 phy-mode = "qsgmii"; 135 phy-mode = "qsgmii";
136 phys = <&serdes 2 SERDES6G(1)>; 136 phys = <&serdes 2 SERDES6G(1)>;
137 status = "okay"; 137 status = "okay";
138 }; 138 };
139 139
140 &port3 { 140 &port3 {
141 reg = <1>; 141 reg = <1>;
142 phy-handle = <&ext_phy1>; 142 phy-handle = <&ext_phy1>;
143 phy-mode = "qsgmii"; 143 phy-mode = "qsgmii";
144 phys = <&serdes 3 SERDES6G(1)>; 144 phys = <&serdes 3 SERDES6G(1)>;
145 status = "okay"; 145 status = "okay";
146 }; 146 };
147 147
148 &port4 { 148 &port4 {
149 reg = <6>; 149 reg = <6>;
150 phy-handle = <&ext_phy6>; 150 phy-handle = <&ext_phy6>;
151 phy-mode = "qsgmii"; 151 phy-mode = "qsgmii";
152 phys = <&serdes 4 SERDES6G(2)>; 152 phys = <&serdes 4 SERDES6G(2)>;
153 status = "okay"; 153 status = "okay";
154 }; 154 };
155 155
156 &port5 { 156 &port5 {
157 reg = <7>; 157 reg = <7>;
158 phy-handle = <&ext_phy7>; 158 phy-handle = <&ext_phy7>;
159 phy-mode = "qsgmii"; 159 phy-mode = "qsgmii";
160 phys = <&serdes 5 SERDES6G(2)>; 160 phys = <&serdes 5 SERDES6G(2)>;
161 status = "okay"; 161 status = "okay";
162 }; 162 };
163 163
164 &port6 { 164 &port6 {
165 reg = <4>; 165 reg = <4>;
166 phy-handle = <&ext_phy4>; 166 phy-handle = <&ext_phy4>;
167 phy-mode = "qsgmii"; 167 phy-mode = "qsgmii";
168 phys = <&serdes 6 SERDES6G(2)>; 168 phys = <&serdes 6 SERDES6G(2)>;
169 status = "okay"; 169 status = "okay";
170 }; 170 };
171 171
172 &port7 { 172 &port7 {
173 reg = <5>; 173 reg = <5>;
174 phy-handle = <&ext_phy5>; 174 phy-handle = <&ext_phy5>;
175 phy-mode = "qsgmii"; 175 phy-mode = "qsgmii";
176 phys = <&serdes 7 SERDES6G(2)>; 176 phys = <&serdes 7 SERDES6G(2)>;
177 status = "okay"; 177 status = "okay";
178 }; 178 };
179 179
180 &serdes { 180 &serdes {
181 status = "okay"; 181 status = "okay";
182 }; 182 };
183 183
184 &switch { 184 &switch {
185 pinctrl-0 = <&pps_out_pins>, <&ptp_ext 185 pinctrl-0 = <&pps_out_pins>, <&ptp_ext_pins>;
186 pinctrl-names = "default"; 186 pinctrl-names = "default";
187 status = "okay"; 187 status = "okay";
188 }; 188 };
189 189
190 &udc { 190 &udc {
191 pinctrl-0 = <&udc_pins>; 191 pinctrl-0 = <&udc_pins>;
192 pinctrl-names = "default"; 192 pinctrl-names = "default";
193 atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE 193 atmel,vbus-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
194 status = "okay"; 194 status = "okay";
195 }; 195 };
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