1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * sama5d2.dtsi - Device Tree Include file for
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludov
7 */
8
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc
14
15 / {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Atmel SAMA5D2 family SoC";
19 compatible = "atmel,sama5d2";
20 interrupt-parent = <&aic>;
21
22 aliases {
23 serial0 = &uart1;
24 serial1 = &uart3;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cort
34 reg = <0>;
35 next-level-cache = <&L
36 };
37 };
38
39 pmu {
40 compatible = "arm,cortex-a5-pm
41 interrupts = <2 IRQ_TYPE_LEVEL
42 };
43
44 etb@740000 {
45 compatible = "arm,coresight-et
46 reg = <0x740000 0x1000>;
47
48 clocks = <&pmc PMC_TYPE_CORE P
49 clock-names = "apb_pclk";
50
51 in-ports {
52 port {
53 etb_in: endpoi
54 remote
55 };
56 };
57 };
58 };
59
60 etm@73c000 {
61 compatible = "arm,coresight-et
62 reg = <0x73c000 0x1000>;
63
64 clocks = <&pmc PMC_TYPE_CORE P
65 clock-names = "apb_pclk";
66
67 out-ports {
68 port {
69 etm_out: endpo
70 remote
71 };
72 };
73 };
74 };
75
76 memory@20000000 {
77 device_type = "memory";
78 reg = <0x20000000 0x20000000>;
79 };
80
81 clocks {
82 slow_xtal: slow_xtal {
83 compatible = "fixed-cl
84 #clock-cells = <0>;
85 clock-frequency = <0>;
86 };
87
88 main_xtal: main_xtal {
89 compatible = "fixed-cl
90 #clock-cells = <0>;
91 clock-frequency = <0>;
92 };
93 };
94
95 ns_sram: sram@200000 {
96 compatible = "mmio-sram";
97 reg = <0x00200000 0x20000>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 0x00200000 0x20000
101 };
102
103 resistive_touch: resistive-touch {
104 compatible = "resistive-adc-to
105 io-channels = <&adc AT91_SAMA5
106 <&adc AT91_SAMA5
107 <&adc AT91_SAMA5
108 io-channel-names = "x", "y", "
109 touchscreen-min-pressure = <50
110 status = "disabled";
111 };
112
113 ahb {
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118
119 nfc_sram: sram@100000 {
120 compatible = "mmio-sra
121 no-memory-wc;
122 reg = <0x00100000 0x24
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x00100000
126
127 };
128
129 usb0: gadget@300000 {
130 compatible = "atmel,sa
131 reg = <0x00300000 0x10
132 0xfc02c000 0x40
133 interrupts = <42 IRQ_T
134 clocks = <&pmc PMC_TYP
135 clock-names = "pclk",
136 status = "disabled";
137 };
138
139 usb1: ohci@400000 {
140 compatible = "atmel,at
141 reg = <0x00400000 0x10
142 interrupts = <41 IRQ_T
143 clocks = <&pmc PMC_TYP
144 clock-names = "ohci_cl
145 status = "disabled";
146 };
147
148 usb2: ehci@500000 {
149 compatible = "atmel,at
150 reg = <0x00500000 0x10
151 interrupts = <41 IRQ_T
152 clocks = <&pmc PMC_TYP
153 clock-names = "usb_clk
154 status = "disabled";
155 };
156
157 L2: cache-controller@a00000 {
158 compatible = "arm,pl31
159 reg = <0x00a00000 0x10
160 interrupts = <63 IRQ_T
161 cache-unified;
162 cache-level = <2>;
163 };
164
165 ebi: ebi@10000000 {
166 compatible = "atmel,sa
167 #address-cells = <2>;
168 #size-cells = <1>;
169 atmel,smc = <&hsmc>;
170 reg = <0x10000000 0x10
171 0x60000000 0x30
172 ranges = <0x0 0x0 0x10
173 0x1 0x0 0x60
174 0x2 0x0 0x70
175 0x3 0x0 0x80
176 clocks = <&pmc PMC_TYP
177 status = "disabled";
178
179 nand_controller: nand-
180 compatible = "
181 atmel,nfc-sram
182 atmel,nfc-io =
183 ecc-engine = <
184 #address-cells
185 #size-cells =
186 ranges;
187 status = "disa
188 };
189 };
190
191 sdmmc0: sdio-host@a0000000 {
192 compatible = "atmel,sa
193 reg = <0xa0000000 0x30
194 interrupts = <31 IRQ_T
195 clocks = <&pmc PMC_TYP
196 clock-names = "hclock"
197 assigned-clocks = <&pm
198 assigned-clock-rates =
199 status = "disabled";
200 };
201
202 sdmmc1: sdio-host@b0000000 {
203 compatible = "atmel,sa
204 reg = <0xb0000000 0x30
205 interrupts = <32 IRQ_T
206 clocks = <&pmc PMC_TYP
207 clock-names = "hclock"
208 assigned-clocks = <&pm
209 assigned-clock-rates =
210 status = "disabled";
211 };
212
213 nfc_io: nfc-io@c0000000 {
214 compatible = "atmel,sa
215 reg = <0xc0000000 0x80
216 };
217
218 apb {
219 compatible = "simple-b
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges;
223
224 hlcdc: hlcdc@f0000000
225 compatible = "
226 reg = <0xf0000
227 interrupts = <
228 clocks = <&pmc
229 clock-names =
230 status = "disa
231
232 hlcdc-display-
233 compat
234 #addre
235 #size-
236
237 port@0
238
239
240
241 };
242 };
243
244 hlcdc_pwm: hlc
245 compat
246 #pwm-c
247 };
248 };
249
250 isc: isc@f0008000 {
251 compatible = "
252 reg = <0xf0008
253 interrupts = <
254 clocks = <&pmc
255 clock-names =
256 #clock-cells =
257 clock-output-n
258 status = "disa
259 };
260
261 ramc0: ramc@f000c000 {
262 compatible = "
263 reg = <0xf000c
264 clocks = <&pmc
265 clock-names =
266 };
267
268 dma0: dma-controller@f
269 compatible = "
270 reg = <0xf0010
271 interrupts = <
272 #dma-cells = <
273 clocks = <&pmc
274 clock-names =
275 };
276
277 /* Place dma1 here des
278 dma1: dma-controller@f
279 compatible = "
280 reg = <0xf0004
281 interrupts = <
282 #dma-cells = <
283 clocks = <&pmc
284 clock-names =
285 };
286
287 pmc: clock-controller@
288 compatible = "
289 reg = <0xf0014
290 interrupts = <
291 #clock-cells =
292 clocks = <&clk
293 clock-names =
294 };
295
296 qspi0: spi@f0020000 {
297 compatible = "
298 reg = <0xf0020
299 reg-names = "q
300 interrupts = <
301 clocks = <&pmc
302 clock-names =
303 #address-cells
304 #size-cells =
305 status = "disa
306 };
307
308 qspi1: spi@f0024000 {
309 compatible = "
310 reg = <0xf0024
311 reg-names = "q
312 interrupts = <
313 clocks = <&pmc
314 clock-names =
315 #address-cells
316 #size-cells =
317 status = "disa
318 };
319
320 sha: crypto@f0028000 {
321 compatible = "
322 reg = <0xf0028
323 interrupts = <
324 dmas = <&dma0
325 (AT91_
326 AT91_
327 dma-names = "t
328 clocks = <&pmc
329 clock-names =
330 };
331
332 aes: crypto@f002c000 {
333 compatible = "
334 reg = <0xf002c
335 interrupts = <
336 dmas = <&dma0
337 (AT91_
338 AT91_
339 <&dma0
340 (AT91_
341 AT91_
342 dma-names = "t
343 clocks = <&pmc
344 clock-names =
345 };
346
347 spi0: spi@f8000000 {
348 compatible = "
349 reg = <0xf8000
350 interrupts = <
351 dmas = <&dma0
352 (AT91_
353 AT91_
354 <&dma0
355 (AT91_
356 AT91_
357 dma-names = "t
358 clocks = <&pmc
359 clock-names =
360 atmel,fifo-siz
361 #address-cells
362 #size-cells =
363 status = "disa
364 };
365
366 ssc0: ssc@f8004000 {
367 compatible = "
368 reg = <0xf8004
369 interrupts = <
370 dmas = <&dma0
371 (AT91_
372 AT91_X
373 <&dma0
374 (AT91_
375 AT91_X
376 dma-names = "t
377 clocks = <&pmc
378 clock-names =
379 status = "disa
380 };
381
382 macb0: ethernet@f80080
383 compatible = "
384 reg = <0xf8008
385 interrupts = <
386 <
387 <
388 clocks = <&pmc
389 clock-names =
390 status = "disa
391 };
392
393 tcb0: timer@f800c000 {
394 compatible = "
395 #address-cells
396 #size-cells =
397 reg = <0xf800c
398 interrupts = <
399 clocks = <&pmc
400 clock-names =
401 };
402
403 tcb1: timer@f8010000 {
404 compatible = "
405 #address-cells
406 #size-cells =
407 reg = <0xf8010
408 interrupts = <
409 clocks = <&pmc
410 clock-names =
411 };
412
413 hsmc: hsmc@f8014000 {
414 compatible = "
415 reg = <0xf8014
416 interrupts = <
417 clocks = <&pmc
418 #address-cells
419 #size-cells =
420 ranges;
421
422 pmecc: ecc-eng
423 compat
424 reg =
425
426 };
427 };
428
429 pdmic: pdmic@f8018000
430 compatible = "
431 reg = <0xf8018
432 interrupts = <
433 dmas = <&dma0
434 (AT91_
435 | AT91
436 dma-names = "r
437 clocks = <&pmc
438 clock-names =
439 status = "disa
440 };
441
442 uart0: serial@f801c000
443 compatible = "
444 reg = <0xf801c
445 atmel,usart-mo
446 interrupts = <
447 dmas = <&dma0
448 (AT91_
449 AT91_
450 <&dma0
451 (AT91_
452 AT91_
453 dma-names = "t
454 clocks = <&pmc
455 clock-names =
456 status = "disa
457 };
458
459 uart1: serial@f8020000
460 compatible = "
461 reg = <0xf8020
462 atmel,usart-mo
463 interrupts = <
464 dmas = <&dma0
465 (AT91_
466 AT91_
467 <&dma0
468 (AT91_
469 AT91_
470 dma-names = "t
471 clocks = <&pmc
472 clock-names =
473 status = "disa
474 };
475
476 uart2: serial@f8024000
477 compatible = "
478 reg = <0xf8024
479 atmel,usart-mo
480 interrupts = <
481 dmas = <&dma0
482 (AT91_
483 AT91_
484 <&dma0
485 (AT91_
486 AT91_
487 dma-names = "t
488 clocks = <&pmc
489 clock-names =
490 status = "disa
491 };
492
493 i2c0: i2c@f8028000 {
494 compatible = "
495 reg = <0xf8028
496 interrupts = <
497 dmas = <&dma0
498 (AT91_
499 AT91_
500 <&dma0
501 (AT91_
502 AT91_
503 dma-names = "t
504 #address-cells
505 #size-cells =
506 clocks = <&pmc
507 atmel,fifo-siz
508 status = "disa
509 };
510
511 pwm0: pwm@f802c000 {
512 compatible = "
513 reg = <0xf802c
514 interrupts = <
515 #pwm-cells = <
516 clocks = <&pmc
517 status = "disa
518 };
519
520 sfr: sfr@f8030000 {
521 compatible = "
522 reg = <0xf8030
523 };
524
525 flx0: flexcom@f8034000
526 compatible = "
527 reg = <0xf8034
528 clocks = <&pmc
529 #address-cells
530 #size-cells =
531 ranges = <0x0
532 status = "disa
533
534 uart5: serial@
535 compat
536 reg =
537 atmel,
538 interr
539 clocks
540 clock-
541 dmas =
542
543
544
545
546
547
548
549 dma-na
550 atmel,
551 status
552 };
553
554 spi2: spi@400
555 compat
556 reg =
557 interr
558 #addre
559 #size-
560 clocks
561 clock-
562 dmas =
563
564
565
566
567
568
569
570 dma-na
571 atmel,
572 status
573 };
574
575 i2c2: i2c@600
576 compat
577 reg =
578 interr
579 #addre
580 #size-
581 clocks
582 dmas =
583
584
585
586
587
588
589
590 dma-na
591 atmel,
592 status
593 };
594 };
595
596 flx1: flexcom@f8038000
597 compatible = "
598 reg = <0xf8038
599 clocks = <&pmc
600 #address-cells
601 #size-cells =
602 ranges = <0x0
603 status = "disa
604
605 uart6: serial@
606 compat
607 reg =
608 atmel,
609 interr
610 clocks
611 clock-
612 dmas =
613
614
615
616
617
618
619
620 dma-na
621 atmel,
622 status
623 };
624
625 spi3: spi@400
626 compat
627 reg =
628 interr
629 #addre
630 #size-
631 clocks
632 clock-
633 dmas =
634
635
636
637
638
639
640
641 dma-na
642 atmel,
643 status
644 };
645
646 i2c3: i2c@600
647 compat
648 reg =
649 interr
650 #addre
651 #size-
652 clocks
653 dmas =
654
655
656
657
658
659
660
661 dma-na
662 atmel,
663 status
664 };
665 };
666
667 securam: sram@f8044000
668 compatible = "
669 reg = <0xf8044
670 clocks = <&pmc
671 #address-cells
672 #size-cells =
673 no-memory-wc;
674 ranges = <0 0x
675 };
676
677 reset_controller: rese
678 compatible = "
679 reg = <0xf8048
680 clocks = <&clk
681 };
682
683 shutdown_controller: p
684 compatible = "
685 reg = <0xf8048
686 clocks = <&clk
687 #address-cells
688 #size-cells =
689 atmel,wakeup-r
690 };
691
692 pit: timer@f8048030 {
693 compatible = "
694 reg = <0xf8048
695 interrupts = <
696 clocks = <&pmc
697 };
698
699 watchdog: watchdog@f80
700 compatible = "
701 reg = <0xf8048
702 interrupts = <
703 clocks = <&clk
704 status = "disa
705 };
706
707 clk32k: clock-controll
708 compatible = "
709 reg = <0xf8048
710 clocks = <&slo
711 #clock-cells =
712 };
713
714 rtc: rtc@f80480b0 {
715 compatible = "
716 reg = <0xf8048
717 interrupts = <
718 clocks = <&clk
719 };
720
721 i2s0: i2s@f8050000 {
722 compatible = "
723 reg = <0xf8050
724 interrupts = <
725 dmas = <&dma0
726 (AT91_
727 AT91_
728 <&dma0
729 (AT91_
730 AT91_
731 dma-names = "t
732 clocks = <&pmc
733 clock-names =
734 assigned-clock
735 assigned-clock
736 status = "disa
737 };
738
739 can0: can@f8054000 {
740 compatible = "
741 reg = <0xf8054
742 reg-names = "m
743 interrupts = <
744 <
745 interrupt-name
746 clocks = <&pmc
747 clock-names =
748 assigned-clock
749 assigned-clock
750 assigned-clock
751 bosch,mram-cfg
752 status = "disa
753 };
754
755 spi1: spi@fc000000 {
756 compatible = "
757 reg = <0xfc000
758 interrupts = <
759 dmas = <&dma0
760 (AT91_
761 AT91_
762 <&dma0
763 (AT91_
764 AT91_
765 dma-names = "t
766 clocks = <&pmc
767 clock-names =
768 atmel,fifo-siz
769 #address-cells
770 #size-cells =
771 status = "disa
772 };
773
774 uart3: serial@fc008000
775 compatible = "
776 reg = <0xfc008
777 atmel,usart-mo
778 interrupts = <
779 dmas = <&dma1
780 (AT91_
781 AT91_
782 <&dma1
783 (AT91_
784 AT91_
785 dma-names = "t
786 clocks = <&pmc
787 clock-names =
788 status = "disa
789 };
790
791 uart4: serial@fc00c000
792 compatible = "
793 reg = <0xfc00c
794 atmel,usart-mo
795 dmas = <&dma0
796 (AT91_
797 AT91_
798 <&dma0
799 (AT91_
800 AT91_
801 dma-names = "t
802 interrupts = <
803 clocks = <&pmc
804 clock-names =
805 status = "disa
806 };
807
808 flx2: flexcom@fc010000
809 compatible = "
810 reg = <0xfc010
811 clocks = <&pmc
812 #address-cells
813 #size-cells =
814 ranges = <0x0
815 status = "disa
816
817 uart7: serial@
818 compat
819 reg =
820 atmel,
821 interr
822 clocks
823 clock-
824 dmas =
825
826
827
828
829
830
831
832 dma-na
833 atmel,
834 status
835 };
836
837 spi4: spi@400
838 compat
839 reg =
840 interr
841 #addre
842 #size-
843 clocks
844 clock-
845 dmas =
846
847
848
849
850
851
852
853 dma-na
854 atmel,
855 status
856 };
857
858 i2c4: i2c@600
859 compat
860 reg =
861 interr
862 #addre
863 #size-
864 clocks
865 dmas =
866
867
868
869
870
871
872
873 dma-na
874 atmel,
875 status
876 };
877 };
878
879 flx3: flexcom@fc014000
880 compatible = "
881 reg = <0xfc014
882 clocks = <&pmc
883 #address-cells
884 #size-cells =
885 ranges = <0x0
886 status = "disa
887
888 uart8: serial@
889 compat
890 reg =
891 atmel,
892 interr
893 clocks
894 clock-
895 dmas =
896
897
898
899
900
901
902
903 dma-na
904 atmel,
905 status
906 };
907
908 spi5: spi@400
909 compat
910 reg =
911 interr
912 #addre
913 #size-
914 clocks
915 clock-
916 dmas =
917
918
919
920
921
922
923
924 dma-na
925 atmel,
926 status
927 };
928
929 i2c5: i2c@600
930 compat
931 reg =
932 interr
933 #addre
934 #size-
935 clocks
936 dmas =
937
938
939
940
941
942
943
944 dma-na
945 atmel,
946 status
947 };
948
949 };
950
951 flx4: flexcom@fc018000
952 compatible = "
953 reg = <0xfc018
954 clocks = <&pmc
955 #address-cells
956 #size-cells =
957 ranges = <0x0
958 status = "disa
959
960 uart9: serial@
961 compat
962 reg =
963 atmel,
964 interr
965 clocks
966 clock-
967 dmas =
968
969
970
971
972
973
974
975 dma-na
976 atmel,
977 status
978 };
979
980 spi6: spi@400
981 compat
982 reg =
983 interr
984 #addre
985 #size-
986 clocks
987 clock-
988 dmas =
989
990
991
992
993
994
995
996 dma-na
997 atmel,
998 status
999 };
1000
1001 i2c6: i2c@600
1002 compa
1003 reg =
1004 inter
1005 #addr
1006 #size
1007 clock
1008 dmas
1009
1010
1011
1012
1013
1014
1015
1016 dma-n
1017 atmel
1018 statu
1019 };
1020 };
1021
1022 trng@fc01c000 {
1023 compatible =
1024 reg = <0xfc01
1025 interrupts =
1026 clocks = <&pm
1027 };
1028
1029 aic: interrupt-contro
1030 #interrupt-ce
1031 compatible =
1032 interrupt-con
1033 reg = <0xfc02
1034 atmel,externa
1035 };
1036
1037 i2c1: i2c@fc028000 {
1038 compatible =
1039 reg = <0xfc02
1040 interrupts =
1041 dmas = <&dma0
1042 (AT91
1043 AT91
1044 <&dma0
1045 (AT91
1046 AT91
1047 dma-names = "
1048 #address-cell
1049 #size-cells =
1050 clocks = <&pm
1051 atmel,fifo-si
1052 status = "dis
1053 };
1054
1055 adc: adc@fc030000 {
1056 compatible =
1057 reg = <0xfc03
1058 interrupts =
1059 clocks = <&pm
1060 clock-names =
1061 dmas = <&dma0
1062 dma-names = "
1063 atmel,min-sam
1064 atmel,max-sam
1065 atmel,startup
1066 atmel,trigger
1067 #io-channel-c
1068 status = "dis
1069 };
1070
1071 pioA: pinctrl@fc03800
1072 compatible =
1073 reg = <0xfc03
1074 interrupts =
1075
1076
1077
1078 interrupt-con
1079 #interrupt-ce
1080 gpio-controll
1081 #gpio-cells =
1082 clocks = <&pm
1083 };
1084
1085 pioBU: secumod@fc0400
1086 compatible =
1087 reg = <0xfc04
1088
1089 gpio-controll
1090 #gpio-cells =
1091 };
1092
1093 tdes: crypto@fc044000
1094 compatible =
1095 reg = <0xfc04
1096 interrupts =
1097 dmas = <&dma0
1098 (AT91
1099 AT91
1100 <&dma0
1101 (AT91
1102 AT91
1103 dma-names = "
1104 clocks = <&pm
1105 clock-names =
1106 };
1107
1108 classd: classd@fc0480
1109 compatible =
1110 reg = <0xfc04
1111 interrupts =
1112 dmas = <&dma0
1113 (AT91
1114 AT91
1115 dma-names = "
1116 clocks = <&pm
1117 clock-names =
1118 status = "dis
1119 };
1120
1121 i2s1: i2s@fc04c000 {
1122 compatible =
1123 reg = <0xfc04
1124 interrupts =
1125 dmas = <&dma0
1126 (AT91
1127 AT91
1128 <&dma0
1129 (AT91
1130 AT91
1131 dma-names = "
1132 clocks = <&pm
1133 clock-names =
1134 assigned-cloc
1135 assigned-cloc
1136 status = "dis
1137 };
1138
1139 can1: can@fc050000 {
1140 compatible =
1141 reg = <0xfc05
1142 reg-names = "
1143 interrupts =
1144
1145 interrupt-nam
1146 clocks = <&pm
1147 clock-names =
1148 assigned-cloc
1149 assigned-cloc
1150 assigned-cloc
1151 bosch,mram-cf
1152 status = "dis
1153 };
1154
1155 sfrbu: sfr@fc05c000 {
1156 compatible =
1157 reg = <0xfc05
1158 };
1159
1160 chipid@fc069000 {
1161 compatible =
1162 reg = <0xfc06
1163 };
1164 };
1165 };
1166 };
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