1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * sama5d2.dtsi - Device Tree Include file for 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * 4 *
5 * Copyright (C) 2015 Atmel, 5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludov 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */ 7 */
8 8
9 #include <dt-bindings/dma/at91.h> 9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h> 11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h> 12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc 13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
14 14
15 / { 15 / {
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 model = "Atmel SAMA5D2 family SoC"; 18 model = "Atmel SAMA5D2 family SoC";
19 compatible = "atmel,sama5d2"; 19 compatible = "atmel,sama5d2";
20 interrupt-parent = <&aic>; 20 interrupt-parent = <&aic>;
21 21
22 aliases { 22 aliases {
23 serial0 = &uart1; 23 serial0 = &uart1;
24 serial1 = &uart3; 24 serial1 = &uart3;
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <0>; 29 #size-cells = <0>;
30 30
31 cpu@0 { 31 cpu@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 compatible = "arm,cort 33 compatible = "arm,cortex-a5";
34 reg = <0>; 34 reg = <0>;
35 next-level-cache = <&L 35 next-level-cache = <&L2>;
36 }; 36 };
37 }; 37 };
38 38
39 pmu { 39 pmu {
40 compatible = "arm,cortex-a5-pm 40 compatible = "arm,cortex-a5-pmu";
41 interrupts = <2 IRQ_TYPE_LEVEL 41 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
42 }; 42 };
43 43
44 etb@740000 { 44 etb@740000 {
45 compatible = "arm,coresight-et 45 compatible = "arm,coresight-etb10", "arm,primecell";
46 reg = <0x740000 0x1000>; 46 reg = <0x740000 0x1000>;
47 47
48 clocks = <&pmc PMC_TYPE_CORE P 48 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
49 clock-names = "apb_pclk"; 49 clock-names = "apb_pclk";
50 50
51 in-ports { 51 in-ports {
52 port { 52 port {
53 etb_in: endpoi 53 etb_in: endpoint {
54 remote 54 remote-endpoint = <&etm_out>;
55 }; 55 };
56 }; 56 };
57 }; 57 };
58 }; 58 };
59 59
60 etm@73c000 { 60 etm@73c000 {
61 compatible = "arm,coresight-et 61 compatible = "arm,coresight-etm3x", "arm,primecell";
62 reg = <0x73c000 0x1000>; 62 reg = <0x73c000 0x1000>;
63 63
64 clocks = <&pmc PMC_TYPE_CORE P 64 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
65 clock-names = "apb_pclk"; 65 clock-names = "apb_pclk";
66 66
67 out-ports { 67 out-ports {
68 port { 68 port {
69 etm_out: endpo 69 etm_out: endpoint {
70 remote 70 remote-endpoint = <&etb_in>;
71 }; 71 };
72 }; 72 };
73 }; 73 };
74 }; 74 };
75 75
76 memory@20000000 { 76 memory@20000000 {
77 device_type = "memory"; 77 device_type = "memory";
78 reg = <0x20000000 0x20000000>; 78 reg = <0x20000000 0x20000000>;
79 }; 79 };
80 80
81 clocks { 81 clocks {
82 slow_xtal: slow_xtal { 82 slow_xtal: slow_xtal {
83 compatible = "fixed-cl 83 compatible = "fixed-clock";
84 #clock-cells = <0>; 84 #clock-cells = <0>;
85 clock-frequency = <0>; 85 clock-frequency = <0>;
86 }; 86 };
87 87
88 main_xtal: main_xtal { 88 main_xtal: main_xtal {
89 compatible = "fixed-cl 89 compatible = "fixed-clock";
90 #clock-cells = <0>; 90 #clock-cells = <0>;
91 clock-frequency = <0>; 91 clock-frequency = <0>;
92 }; 92 };
93 }; 93 };
94 94
95 ns_sram: sram@200000 { 95 ns_sram: sram@200000 {
96 compatible = "mmio-sram"; 96 compatible = "mmio-sram";
97 reg = <0x00200000 0x20000>; 97 reg = <0x00200000 0x20000>;
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <1>; 99 #size-cells = <1>;
100 ranges = <0 0x00200000 0x20000 100 ranges = <0 0x00200000 0x20000>;
101 }; 101 };
102 102
103 resistive_touch: resistive-touch { 103 resistive_touch: resistive-touch {
104 compatible = "resistive-adc-to 104 compatible = "resistive-adc-touch";
105 io-channels = <&adc AT91_SAMA5 105 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
106 <&adc AT91_SAMA5 106 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
107 <&adc AT91_SAMA5 107 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
108 io-channel-names = "x", "y", " 108 io-channel-names = "x", "y", "pressure";
109 touchscreen-min-pressure = <50 109 touchscreen-min-pressure = <50000>;
110 status = "disabled"; 110 status = "disabled";
111 }; 111 };
112 112
113 ahb { 113 ahb {
114 compatible = "simple-bus"; 114 compatible = "simple-bus";
115 #address-cells = <1>; 115 #address-cells = <1>;
116 #size-cells = <1>; 116 #size-cells = <1>;
117 ranges; 117 ranges;
118 118
119 nfc_sram: sram@100000 { 119 nfc_sram: sram@100000 {
120 compatible = "mmio-sra 120 compatible = "mmio-sram";
121 no-memory-wc; 121 no-memory-wc;
122 reg = <0x00100000 0x24 122 reg = <0x00100000 0x2400>;
123 #address-cells = <1>; 123 #address-cells = <1>;
124 #size-cells = <1>; 124 #size-cells = <1>;
125 ranges = <0 0x00100000 125 ranges = <0 0x00100000 0x2400>;
126 126
127 }; 127 };
128 128
129 usb0: gadget@300000 { 129 usb0: gadget@300000 {
130 compatible = "atmel,sa 130 compatible = "atmel,sama5d3-udc";
131 reg = <0x00300000 0x10 131 reg = <0x00300000 0x100000
132 0xfc02c000 0x40 132 0xfc02c000 0x400>;
133 interrupts = <42 IRQ_T 133 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&pmc PMC_TYP 134 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
135 clock-names = "pclk", 135 clock-names = "pclk", "hclk";
136 status = "disabled"; 136 status = "disabled";
137 }; 137 };
138 138
139 usb1: ohci@400000 { 139 usb1: ohci@400000 {
140 compatible = "atmel,at 140 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
141 reg = <0x00400000 0x10 141 reg = <0x00400000 0x100000>;
142 interrupts = <41 IRQ_T 142 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
143 clocks = <&pmc PMC_TYP 143 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
144 clock-names = "ohci_cl 144 clock-names = "ohci_clk", "hclk", "uhpck";
145 status = "disabled"; 145 status = "disabled";
146 }; 146 };
147 147
148 usb2: ehci@500000 { 148 usb2: ehci@500000 {
149 compatible = "atmel,at 149 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
150 reg = <0x00500000 0x10 150 reg = <0x00500000 0x100000>;
151 interrupts = <41 IRQ_T 151 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
152 clocks = <&pmc PMC_TYP 152 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
153 clock-names = "usb_clk 153 clock-names = "usb_clk", "ehci_clk";
154 status = "disabled"; 154 status = "disabled";
155 }; 155 };
156 156
157 L2: cache-controller@a00000 { 157 L2: cache-controller@a00000 {
158 compatible = "arm,pl31 158 compatible = "arm,pl310-cache";
159 reg = <0x00a00000 0x10 159 reg = <0x00a00000 0x1000>;
160 interrupts = <63 IRQ_T 160 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
161 cache-unified; 161 cache-unified;
162 cache-level = <2>; 162 cache-level = <2>;
163 }; 163 };
164 164
165 ebi: ebi@10000000 { 165 ebi: ebi@10000000 {
166 compatible = "atmel,sa 166 compatible = "atmel,sama5d3-ebi";
167 #address-cells = <2>; 167 #address-cells = <2>;
168 #size-cells = <1>; 168 #size-cells = <1>;
169 atmel,smc = <&hsmc>; 169 atmel,smc = <&hsmc>;
170 reg = <0x10000000 0x10 170 reg = <0x10000000 0x10000000
171 0x60000000 0x30 171 0x60000000 0x30000000>;
172 ranges = <0x0 0x0 0x10 172 ranges = <0x0 0x0 0x10000000 0x10000000
173 0x1 0x0 0x60 173 0x1 0x0 0x60000000 0x10000000
174 0x2 0x0 0x70 174 0x2 0x0 0x70000000 0x10000000
175 0x3 0x0 0x80 175 0x3 0x0 0x80000000 0x10000000>;
176 clocks = <&pmc PMC_TYP 176 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
177 status = "disabled"; 177 status = "disabled";
178 178
179 nand_controller: nand- 179 nand_controller: nand-controller {
180 compatible = " 180 compatible = "atmel,sama5d3-nand-controller";
181 atmel,nfc-sram 181 atmel,nfc-sram = <&nfc_sram>;
182 atmel,nfc-io = 182 atmel,nfc-io = <&nfc_io>;
183 ecc-engine = < 183 ecc-engine = <&pmecc>;
184 #address-cells 184 #address-cells = <2>;
185 #size-cells = 185 #size-cells = <1>;
186 ranges; 186 ranges;
187 status = "disa 187 status = "disabled";
188 }; 188 };
189 }; 189 };
190 190
191 sdmmc0: sdio-host@a0000000 { 191 sdmmc0: sdio-host@a0000000 {
192 compatible = "atmel,sa 192 compatible = "atmel,sama5d2-sdhci";
193 reg = <0xa0000000 0x30 193 reg = <0xa0000000 0x300>;
194 interrupts = <31 IRQ_T 194 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
195 clocks = <&pmc PMC_TYP 195 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
196 clock-names = "hclock" 196 clock-names = "hclock", "multclk", "baseclk";
197 assigned-clocks = <&pm 197 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
198 assigned-clock-rates = 198 assigned-clock-rates = <480000000>;
199 status = "disabled"; 199 status = "disabled";
200 }; 200 };
201 201
202 sdmmc1: sdio-host@b0000000 { 202 sdmmc1: sdio-host@b0000000 {
203 compatible = "atmel,sa 203 compatible = "atmel,sama5d2-sdhci";
204 reg = <0xb0000000 0x30 204 reg = <0xb0000000 0x300>;
205 interrupts = <32 IRQ_T 205 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
206 clocks = <&pmc PMC_TYP 206 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
207 clock-names = "hclock" 207 clock-names = "hclock", "multclk", "baseclk";
208 assigned-clocks = <&pm 208 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
209 assigned-clock-rates = 209 assigned-clock-rates = <480000000>;
210 status = "disabled"; 210 status = "disabled";
211 }; 211 };
212 212
213 nfc_io: nfc-io@c0000000 { 213 nfc_io: nfc-io@c0000000 {
214 compatible = "atmel,sa 214 compatible = "atmel,sama5d3-nfc-io", "syscon";
215 reg = <0xc0000000 0x80 215 reg = <0xc0000000 0x8000000>;
216 }; 216 };
217 217
218 apb { 218 apb {
219 compatible = "simple-b 219 compatible = "simple-bus";
220 #address-cells = <1>; 220 #address-cells = <1>;
221 #size-cells = <1>; 221 #size-cells = <1>;
222 ranges; 222 ranges;
223 223
224 hlcdc: hlcdc@f0000000 224 hlcdc: hlcdc@f0000000 {
225 compatible = " 225 compatible = "atmel,sama5d2-hlcdc";
226 reg = <0xf0000 226 reg = <0xf0000000 0x2000>;
227 interrupts = < 227 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
228 clocks = <&pmc 228 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
229 clock-names = 229 clock-names = "periph_clk","sys_clk", "slow_clk";
230 status = "disa 230 status = "disabled";
231 231
232 hlcdc-display- 232 hlcdc-display-controller {
233 compat 233 compatible = "atmel,hlcdc-display-controller";
234 #addre 234 #address-cells = <1>;
235 #size- 235 #size-cells = <0>;
236 236
237 port@0 237 port@0 {
238 238 #address-cells = <1>;
239 239 #size-cells = <0>;
240 240 reg = <0>;
241 }; 241 };
242 }; 242 };
243 243
244 hlcdc_pwm: hlc 244 hlcdc_pwm: hlcdc-pwm {
245 compat 245 compatible = "atmel,hlcdc-pwm";
246 #pwm-c 246 #pwm-cells = <3>;
247 }; 247 };
248 }; 248 };
249 249
250 isc: isc@f0008000 { 250 isc: isc@f0008000 {
251 compatible = " 251 compatible = "atmel,sama5d2-isc";
252 reg = <0xf0008 252 reg = <0xf0008000 0x4000>;
253 interrupts = < 253 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
254 clocks = <&pmc 254 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
255 clock-names = 255 clock-names = "hclock", "iscck", "gck";
256 #clock-cells = 256 #clock-cells = <0>;
257 clock-output-n 257 clock-output-names = "isc-mck";
258 status = "disa 258 status = "disabled";
259 }; 259 };
260 260
261 ramc0: ramc@f000c000 { 261 ramc0: ramc@f000c000 {
262 compatible = " 262 compatible = "atmel,sama5d3-ddramc";
263 reg = <0xf000c 263 reg = <0xf000c000 0x200>;
264 clocks = <&pmc 264 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
265 clock-names = 265 clock-names = "ddrck", "mpddr";
266 }; 266 };
267 267
268 dma0: dma-controller@f 268 dma0: dma-controller@f0010000 {
269 compatible = " 269 compatible = "atmel,sama5d4-dma";
270 reg = <0xf0010 270 reg = <0xf0010000 0x1000>;
271 interrupts = < 271 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
272 #dma-cells = < 272 #dma-cells = <1>;
273 clocks = <&pmc 273 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
274 clock-names = 274 clock-names = "dma_clk";
275 }; 275 };
276 276
277 /* Place dma1 here des 277 /* Place dma1 here despite its address */
278 dma1: dma-controller@f 278 dma1: dma-controller@f0004000 {
279 compatible = " 279 compatible = "atmel,sama5d4-dma";
280 reg = <0xf0004 280 reg = <0xf0004000 0x1000>;
281 interrupts = < 281 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
282 #dma-cells = < 282 #dma-cells = <1>;
283 clocks = <&pmc 283 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
284 clock-names = 284 clock-names = "dma_clk";
285 }; 285 };
286 286
287 pmc: clock-controller@ 287 pmc: clock-controller@f0014000 {
288 compatible = " 288 compatible = "atmel,sama5d2-pmc", "syscon";
289 reg = <0xf0014 289 reg = <0xf0014000 0x160>;
290 interrupts = < 290 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
291 #clock-cells = 291 #clock-cells = <2>;
292 clocks = <&clk 292 clocks = <&clk32k>, <&main_xtal>;
293 clock-names = 293 clock-names = "slow_clk", "main_xtal";
294 }; 294 };
295 295
296 qspi0: spi@f0020000 { 296 qspi0: spi@f0020000 {
297 compatible = " 297 compatible = "atmel,sama5d2-qspi";
298 reg = <0xf0020 298 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
299 reg-names = "q 299 reg-names = "qspi_base", "qspi_mmap";
300 interrupts = < 300 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
301 clocks = <&pmc 301 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
302 clock-names = 302 clock-names = "pclk";
303 #address-cells 303 #address-cells = <1>;
304 #size-cells = 304 #size-cells = <0>;
305 status = "disa 305 status = "disabled";
306 }; 306 };
307 307
308 qspi1: spi@f0024000 { 308 qspi1: spi@f0024000 {
309 compatible = " 309 compatible = "atmel,sama5d2-qspi";
310 reg = <0xf0024 310 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
311 reg-names = "q 311 reg-names = "qspi_base", "qspi_mmap";
312 interrupts = < 312 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
313 clocks = <&pmc 313 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
314 clock-names = 314 clock-names = "pclk";
315 #address-cells 315 #address-cells = <1>;
316 #size-cells = 316 #size-cells = <0>;
317 status = "disa 317 status = "disabled";
318 }; 318 };
319 319
320 sha: crypto@f0028000 { 320 sha: crypto@f0028000 {
321 compatible = " 321 compatible = "atmel,at91sam9g46-sha";
322 reg = <0xf0028 322 reg = <0xf0028000 0x100>;
323 interrupts = < 323 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
324 dmas = <&dma0 324 dmas = <&dma0
325 (AT91_ 325 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
326 AT91_ 326 AT91_XDMAC_DT_PERID(30))>;
327 dma-names = "t 327 dma-names = "tx";
328 clocks = <&pmc 328 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
329 clock-names = 329 clock-names = "sha_clk";
330 }; 330 };
331 331
332 aes: crypto@f002c000 { 332 aes: crypto@f002c000 {
333 compatible = " 333 compatible = "atmel,at91sam9g46-aes";
334 reg = <0xf002c 334 reg = <0xf002c000 0x100>;
335 interrupts = < 335 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
336 dmas = <&dma0 336 dmas = <&dma0
337 (AT91_ 337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 AT91_ 338 AT91_XDMAC_DT_PERID(26))>,
339 <&dma0 339 <&dma0
340 (AT91_ 340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
341 AT91_ 341 AT91_XDMAC_DT_PERID(27))>;
342 dma-names = "t 342 dma-names = "tx", "rx";
343 clocks = <&pmc 343 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
344 clock-names = 344 clock-names = "aes_clk";
345 }; 345 };
346 346
347 spi0: spi@f8000000 { 347 spi0: spi@f8000000 {
348 compatible = " 348 compatible = "atmel,at91rm9200-spi";
349 reg = <0xf8000 349 reg = <0xf8000000 0x100>;
350 interrupts = < 350 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
351 dmas = <&dma0 351 dmas = <&dma0
352 (AT91_ 352 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
353 AT91_ 353 AT91_XDMAC_DT_PERID(6))>,
354 <&dma0 354 <&dma0
355 (AT91_ 355 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
356 AT91_ 356 AT91_XDMAC_DT_PERID(7))>;
357 dma-names = "t 357 dma-names = "tx", "rx";
358 clocks = <&pmc 358 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
359 clock-names = 359 clock-names = "spi_clk";
360 atmel,fifo-siz 360 atmel,fifo-size = <16>;
361 #address-cells 361 #address-cells = <1>;
362 #size-cells = 362 #size-cells = <0>;
363 status = "disa 363 status = "disabled";
364 }; 364 };
365 365
366 ssc0: ssc@f8004000 { 366 ssc0: ssc@f8004000 {
367 compatible = " 367 compatible = "atmel,at91sam9g45-ssc";
368 reg = <0xf8004 368 reg = <0xf8004000 0x4000>;
369 interrupts = < 369 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
370 dmas = <&dma0 370 dmas = <&dma0
371 (AT91_ 371 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
372 AT91_X 372 AT91_XDMAC_DT_PERID(21))>,
373 <&dma0 373 <&dma0
374 (AT91_ 374 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
375 AT91_X 375 AT91_XDMAC_DT_PERID(22))>;
376 dma-names = "t 376 dma-names = "tx", "rx";
377 clocks = <&pmc 377 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
378 clock-names = 378 clock-names = "pclk";
379 status = "disa 379 status = "disabled";
380 }; 380 };
381 381
382 macb0: ethernet@f80080 382 macb0: ethernet@f8008000 {
383 compatible = " 383 compatible = "atmel,sama5d2-gem";
384 reg = <0xf8008 384 reg = <0xf8008000 0x1000>;
385 interrupts = < 385 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */
386 < 386 <66 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */
387 < 387 <67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
388 clocks = <&pmc 388 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
389 clock-names = 389 clock-names = "hclk", "pclk";
390 status = "disa 390 status = "disabled";
391 }; 391 };
392 392
393 tcb0: timer@f800c000 { 393 tcb0: timer@f800c000 {
394 compatible = " 394 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
395 #address-cells 395 #address-cells = <1>;
396 #size-cells = 396 #size-cells = <0>;
397 reg = <0xf800c 397 reg = <0xf800c000 0x100>;
398 interrupts = < 398 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
399 clocks = <&pmc 399 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
400 clock-names = 400 clock-names = "t0_clk", "gclk", "slow_clk";
401 }; 401 };
402 402
403 tcb1: timer@f8010000 { 403 tcb1: timer@f8010000 {
404 compatible = " 404 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
405 #address-cells 405 #address-cells = <1>;
406 #size-cells = 406 #size-cells = <0>;
407 reg = <0xf8010 407 reg = <0xf8010000 0x100>;
408 interrupts = < 408 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
409 clocks = <&pmc 409 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
410 clock-names = 410 clock-names = "t0_clk", "gclk", "slow_clk";
411 }; 411 };
412 412
413 hsmc: hsmc@f8014000 { 413 hsmc: hsmc@f8014000 {
414 compatible = " 414 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
415 reg = <0xf8014 415 reg = <0xf8014000 0x1000>;
416 interrupts = < 416 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
417 clocks = <&pmc 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
418 #address-cells 418 #address-cells = <1>;
419 #size-cells = 419 #size-cells = <1>;
420 ranges; 420 ranges;
421 421
422 pmecc: ecc-eng 422 pmecc: ecc-engine@f8014070 {
423 compat 423 compatible = "atmel,sama5d2-pmecc";
424 reg = 424 reg = <0xf8014070 0x490>,
425 425 <0xf8014500 0x200>;
426 }; 426 };
427 }; 427 };
428 428
429 pdmic: pdmic@f8018000 429 pdmic: pdmic@f8018000 {
430 compatible = " 430 compatible = "atmel,sama5d2-pdmic";
431 reg = <0xf8018 431 reg = <0xf8018000 0x124>;
432 interrupts = < 432 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
433 dmas = <&dma0 433 dmas = <&dma0
434 (AT91_ 434 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
435 | AT91 435 | AT91_XDMAC_DT_PERID(50))>;
436 dma-names = "r 436 dma-names = "rx";
437 clocks = <&pmc 437 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
438 clock-names = 438 clock-names = "pclk", "gclk";
439 status = "disa 439 status = "disabled";
440 }; 440 };
441 441
442 uart0: serial@f801c000 442 uart0: serial@f801c000 {
443 compatible = " 443 compatible = "atmel,at91sam9260-usart";
444 reg = <0xf801c 444 reg = <0xf801c000 0x100>;
445 atmel,usart-mo 445 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
446 interrupts = < 446 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
447 dmas = <&dma0 447 dmas = <&dma0
448 (AT91_ 448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
449 AT91_ 449 AT91_XDMAC_DT_PERID(35))>,
450 <&dma0 450 <&dma0
451 (AT91_ 451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
452 AT91_ 452 AT91_XDMAC_DT_PERID(36))>;
453 dma-names = "t 453 dma-names = "tx", "rx";
454 clocks = <&pmc 454 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
455 clock-names = 455 clock-names = "usart";
456 status = "disa 456 status = "disabled";
457 }; 457 };
458 458
459 uart1: serial@f8020000 459 uart1: serial@f8020000 {
460 compatible = " 460 compatible = "atmel,at91sam9260-usart";
461 reg = <0xf8020 461 reg = <0xf8020000 0x100>;
462 atmel,usart-mo 462 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
463 interrupts = < 463 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
464 dmas = <&dma0 464 dmas = <&dma0
465 (AT91_ 465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
466 AT91_ 466 AT91_XDMAC_DT_PERID(37))>,
467 <&dma0 467 <&dma0
468 (AT91_ 468 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
469 AT91_ 469 AT91_XDMAC_DT_PERID(38))>;
470 dma-names = "t 470 dma-names = "tx", "rx";
471 clocks = <&pmc 471 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
472 clock-names = 472 clock-names = "usart";
473 status = "disa 473 status = "disabled";
474 }; 474 };
475 475
476 uart2: serial@f8024000 476 uart2: serial@f8024000 {
477 compatible = " 477 compatible = "atmel,at91sam9260-usart";
478 reg = <0xf8024 478 reg = <0xf8024000 0x100>;
479 atmel,usart-mo 479 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
480 interrupts = < 480 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
481 dmas = <&dma0 481 dmas = <&dma0
482 (AT91_ 482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
483 AT91_ 483 AT91_XDMAC_DT_PERID(39))>,
484 <&dma0 484 <&dma0
485 (AT91_ 485 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
486 AT91_ 486 AT91_XDMAC_DT_PERID(40))>;
487 dma-names = "t 487 dma-names = "tx", "rx";
488 clocks = <&pmc 488 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
489 clock-names = 489 clock-names = "usart";
490 status = "disa 490 status = "disabled";
491 }; 491 };
492 492
493 i2c0: i2c@f8028000 { 493 i2c0: i2c@f8028000 {
494 compatible = " 494 compatible = "atmel,sama5d2-i2c";
495 reg = <0xf8028 495 reg = <0xf8028000 0x100>;
496 interrupts = < 496 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
497 dmas = <&dma0 497 dmas = <&dma0
498 (AT91_ 498 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
499 AT91_ 499 AT91_XDMAC_DT_PERID(0))>,
500 <&dma0 500 <&dma0
501 (AT91_ 501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
502 AT91_ 502 AT91_XDMAC_DT_PERID(1))>;
503 dma-names = "t 503 dma-names = "tx", "rx";
504 #address-cells 504 #address-cells = <1>;
505 #size-cells = 505 #size-cells = <0>;
506 clocks = <&pmc 506 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
507 atmel,fifo-siz 507 atmel,fifo-size = <16>;
508 status = "disa 508 status = "disabled";
509 }; 509 };
510 510
511 pwm0: pwm@f802c000 { 511 pwm0: pwm@f802c000 {
512 compatible = " 512 compatible = "atmel,sama5d2-pwm";
513 reg = <0xf802c 513 reg = <0xf802c000 0x4000>;
514 interrupts = < 514 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
515 #pwm-cells = < 515 #pwm-cells = <3>;
516 clocks = <&pmc 516 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
517 status = "disa 517 status = "disabled";
518 }; 518 };
519 519
520 sfr: sfr@f8030000 { 520 sfr: sfr@f8030000 {
521 compatible = " 521 compatible = "atmel,sama5d2-sfr", "syscon";
522 reg = <0xf8030 522 reg = <0xf8030000 0x98>;
523 }; 523 };
524 524
525 flx0: flexcom@f8034000 525 flx0: flexcom@f8034000 {
526 compatible = " 526 compatible = "atmel,sama5d2-flexcom";
527 reg = <0xf8034 527 reg = <0xf8034000 0x200>;
528 clocks = <&pmc 528 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
529 #address-cells 529 #address-cells = <1>;
530 #size-cells = 530 #size-cells = <1>;
531 ranges = <0x0 531 ranges = <0x0 0xf8034000 0x800>;
532 status = "disa 532 status = "disabled";
533 533
534 uart5: serial@ 534 uart5: serial@200 {
535 compat 535 compatible = "atmel,at91sam9260-usart";
536 reg = 536 reg = <0x200 0x200>;
537 atmel, 537 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
538 interr 538 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
539 clocks 539 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
540 clock- 540 clock-names = "usart";
541 dmas = 541 dmas = <&dma0
542 542 (AT91_XDMAC_DT_MEM_IF(0) |
543 543 AT91_XDMAC_DT_PER_IF(1) |
544 544 AT91_XDMAC_DT_PERID(11))>,
545 545 <&dma0
546 546 (AT91_XDMAC_DT_MEM_IF(0) |
547 547 AT91_XDMAC_DT_PER_IF(1) |
548 548 AT91_XDMAC_DT_PERID(12))>;
549 dma-na 549 dma-names = "tx", "rx";
550 atmel, 550 atmel,fifo-size = <32>;
551 status 551 status = "disabled";
552 }; 552 };
553 553
554 spi2: spi@400 554 spi2: spi@400 {
555 compat 555 compatible = "atmel,at91rm9200-spi";
556 reg = 556 reg = <0x400 0x200>;
557 interr 557 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
558 #addre 558 #address-cells = <1>;
559 #size- 559 #size-cells = <0>;
560 clocks 560 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
561 clock- 561 clock-names = "spi_clk";
562 dmas = 562 dmas = <&dma0
563 563 (AT91_XDMAC_DT_MEM_IF(0) |
564 564 AT91_XDMAC_DT_PER_IF(1) |
565 565 AT91_XDMAC_DT_PERID(11))>,
566 566 <&dma0
567 567 (AT91_XDMAC_DT_MEM_IF(0) |
568 568 AT91_XDMAC_DT_PER_IF(1) |
569 569 AT91_XDMAC_DT_PERID(12))>;
570 dma-na 570 dma-names = "tx", "rx";
571 atmel, 571 atmel,fifo-size = <16>;
572 status 572 status = "disabled";
573 }; 573 };
574 574
575 i2c2: i2c@600 575 i2c2: i2c@600 {
576 compat 576 compatible = "atmel,sama5d2-i2c";
577 reg = 577 reg = <0x600 0x200>;
578 interr 578 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
579 #addre 579 #address-cells = <1>;
580 #size- 580 #size-cells = <0>;
581 clocks 581 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
582 dmas = 582 dmas = <&dma0
583 583 (AT91_XDMAC_DT_MEM_IF(0) |
584 584 AT91_XDMAC_DT_PER_IF(1) |
585 585 AT91_XDMAC_DT_PERID(11))>,
586 586 <&dma0
587 587 (AT91_XDMAC_DT_MEM_IF(0) |
588 588 AT91_XDMAC_DT_PER_IF(1) |
589 589 AT91_XDMAC_DT_PERID(12))>;
590 dma-na 590 dma-names = "tx", "rx";
591 atmel, 591 atmel,fifo-size = <16>;
592 status 592 status = "disabled";
593 }; 593 };
594 }; 594 };
595 595
596 flx1: flexcom@f8038000 596 flx1: flexcom@f8038000 {
597 compatible = " 597 compatible = "atmel,sama5d2-flexcom";
598 reg = <0xf8038 598 reg = <0xf8038000 0x200>;
599 clocks = <&pmc 599 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
600 #address-cells 600 #address-cells = <1>;
601 #size-cells = 601 #size-cells = <1>;
602 ranges = <0x0 602 ranges = <0x0 0xf8038000 0x800>;
603 status = "disa 603 status = "disabled";
604 604
605 uart6: serial@ 605 uart6: serial@200 {
606 compat 606 compatible = "atmel,at91sam9260-usart";
607 reg = 607 reg = <0x200 0x200>;
608 atmel, 608 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
609 interr 609 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
610 clocks 610 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
611 clock- 611 clock-names = "usart";
612 dmas = 612 dmas = <&dma0
613 613 (AT91_XDMAC_DT_MEM_IF(0) |
614 614 AT91_XDMAC_DT_PER_IF(1) |
615 615 AT91_XDMAC_DT_PERID(13))>,
616 616 <&dma0
617 617 (AT91_XDMAC_DT_MEM_IF(0) |
618 618 AT91_XDMAC_DT_PER_IF(1) |
619 619 AT91_XDMAC_DT_PERID(14))>;
620 dma-na 620 dma-names = "tx", "rx";
621 atmel, 621 atmel,fifo-size = <32>;
622 status 622 status = "disabled";
623 }; 623 };
624 624
625 spi3: spi@400 625 spi3: spi@400 {
626 compat 626 compatible = "atmel,at91rm9200-spi";
627 reg = 627 reg = <0x400 0x200>;
628 interr 628 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
629 #addre 629 #address-cells = <1>;
630 #size- 630 #size-cells = <0>;
631 clocks 631 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
632 clock- 632 clock-names = "spi_clk";
633 dmas = 633 dmas = <&dma0
634 634 (AT91_XDMAC_DT_MEM_IF(0) |
635 635 AT91_XDMAC_DT_PER_IF(1) |
636 636 AT91_XDMAC_DT_PERID(13))>,
637 637 <&dma0
638 638 (AT91_XDMAC_DT_MEM_IF(0) |
639 639 AT91_XDMAC_DT_PER_IF(1) |
640 640 AT91_XDMAC_DT_PERID(14))>;
641 dma-na 641 dma-names = "tx", "rx";
642 atmel, 642 atmel,fifo-size = <16>;
643 status 643 status = "disabled";
644 }; 644 };
645 645
646 i2c3: i2c@600 646 i2c3: i2c@600 {
647 compat 647 compatible = "atmel,sama5d2-i2c";
648 reg = 648 reg = <0x600 0x200>;
649 interr 649 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
650 #addre 650 #address-cells = <1>;
651 #size- 651 #size-cells = <0>;
652 clocks 652 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
653 dmas = 653 dmas = <&dma0
654 654 (AT91_XDMAC_DT_MEM_IF(0) |
655 655 AT91_XDMAC_DT_PER_IF(1) |
656 656 AT91_XDMAC_DT_PERID(13))>,
657 657 <&dma0
658 658 (AT91_XDMAC_DT_MEM_IF(0) |
659 659 AT91_XDMAC_DT_PER_IF(1) |
660 660 AT91_XDMAC_DT_PERID(14))>;
661 dma-na 661 dma-names = "tx", "rx";
662 atmel, 662 atmel,fifo-size = <16>;
663 status 663 status = "disabled";
664 }; 664 };
665 }; 665 };
666 666
667 securam: sram@f8044000 667 securam: sram@f8044000 {
668 compatible = " 668 compatible = "atmel,sama5d2-securam", "mmio-sram";
669 reg = <0xf8044 669 reg = <0xf8044000 0x1420>;
670 clocks = <&pmc 670 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
671 #address-cells 671 #address-cells = <1>;
672 #size-cells = 672 #size-cells = <1>;
673 no-memory-wc; 673 no-memory-wc;
674 ranges = <0 0x 674 ranges = <0 0xf8044000 0x1420>;
675 }; 675 };
676 676
677 reset_controller: rese 677 reset_controller: reset-controller@f8048000 {
678 compatible = " 678 compatible = "atmel,sama5d3-rstc";
679 reg = <0xf8048 679 reg = <0xf8048000 0x10>;
680 clocks = <&clk 680 clocks = <&clk32k>;
681 }; 681 };
682 682
683 shutdown_controller: p 683 shutdown_controller: poweroff@f8048010 {
684 compatible = " 684 compatible = "atmel,sama5d2-shdwc";
685 reg = <0xf8048 685 reg = <0xf8048010 0x10>;
686 clocks = <&clk 686 clocks = <&clk32k>;
687 #address-cells 687 #address-cells = <1>;
688 #size-cells = 688 #size-cells = <0>;
689 atmel,wakeup-r 689 atmel,wakeup-rtc-timer;
690 }; 690 };
691 691
692 pit: timer@f8048030 { 692 pit: timer@f8048030 {
693 compatible = " 693 compatible = "atmel,at91sam9260-pit";
694 reg = <0xf8048 694 reg = <0xf8048030 0x10>;
695 interrupts = < 695 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
696 clocks = <&pmc 696 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
697 }; 697 };
698 698
699 watchdog: watchdog@f80 699 watchdog: watchdog@f8048040 {
700 compatible = " 700 compatible = "atmel,sama5d4-wdt";
701 reg = <0xf8048 701 reg = <0xf8048040 0x10>;
702 interrupts = < 702 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
703 clocks = <&clk 703 clocks = <&clk32k>;
704 status = "disa 704 status = "disabled";
705 }; 705 };
706 706
707 clk32k: clock-controll 707 clk32k: clock-controller@f8048050 {
708 compatible = " 708 compatible = "atmel,sama5d4-sckc";
709 reg = <0xf8048 709 reg = <0xf8048050 0x4>;
710 clocks = <&slo 710 clocks = <&slow_xtal>;
711 #clock-cells = 711 #clock-cells = <0>;
712 }; 712 };
713 713
714 rtc: rtc@f80480b0 { 714 rtc: rtc@f80480b0 {
715 compatible = " 715 compatible = "atmel,sama5d2-rtc";
716 reg = <0xf8048 716 reg = <0xf80480b0 0x30>;
717 interrupts = < 717 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
718 clocks = <&clk 718 clocks = <&clk32k>;
719 }; 719 };
720 720
721 i2s0: i2s@f8050000 { 721 i2s0: i2s@f8050000 {
722 compatible = " 722 compatible = "atmel,sama5d2-i2s";
723 reg = <0xf8050 723 reg = <0xf8050000 0x100>;
724 interrupts = < 724 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
725 dmas = <&dma0 725 dmas = <&dma0
726 (AT91_ 726 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
727 AT91_ 727 AT91_XDMAC_DT_PERID(31))>,
728 <&dma0 728 <&dma0
729 (AT91_ 729 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
730 AT91_ 730 AT91_XDMAC_DT_PERID(32))>;
731 dma-names = "t 731 dma-names = "tx", "rx";
732 clocks = <&pmc 732 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
733 clock-names = 733 clock-names = "pclk", "gclk";
734 assigned-clock 734 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
735 assigned-clock 735 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
736 status = "disa 736 status = "disabled";
737 }; 737 };
738 738
739 can0: can@f8054000 { 739 can0: can@f8054000 {
740 compatible = " 740 compatible = "bosch,m_can";
741 reg = <0xf8054 741 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
742 reg-names = "m 742 reg-names = "m_can", "message_ram";
743 interrupts = < 743 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
744 < 744 <64 IRQ_TYPE_LEVEL_HIGH 7>;
745 interrupt-name 745 interrupt-names = "int0", "int1";
746 clocks = <&pmc 746 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
747 clock-names = 747 clock-names = "hclk", "cclk";
748 assigned-clock 748 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
749 assigned-clock 749 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
750 assigned-clock 750 assigned-clock-rates = <40000000>;
751 bosch,mram-cfg 751 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
752 status = "disa 752 status = "disabled";
753 }; 753 };
754 754
755 spi1: spi@fc000000 { 755 spi1: spi@fc000000 {
756 compatible = " 756 compatible = "atmel,at91rm9200-spi";
757 reg = <0xfc000 757 reg = <0xfc000000 0x100>;
758 interrupts = < 758 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
759 dmas = <&dma0 759 dmas = <&dma0
760 (AT91_ 760 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
761 AT91_ 761 AT91_XDMAC_DT_PERID(8))>,
762 <&dma0 762 <&dma0
763 (AT91_ 763 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
764 AT91_ 764 AT91_XDMAC_DT_PERID(9))>;
765 dma-names = "t 765 dma-names = "tx", "rx";
766 clocks = <&pmc 766 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
767 clock-names = 767 clock-names = "spi_clk";
768 atmel,fifo-siz 768 atmel,fifo-size = <16>;
769 #address-cells 769 #address-cells = <1>;
770 #size-cells = 770 #size-cells = <0>;
771 status = "disa 771 status = "disabled";
772 }; 772 };
773 773
774 uart3: serial@fc008000 774 uart3: serial@fc008000 {
775 compatible = " 775 compatible = "atmel,at91sam9260-usart";
776 reg = <0xfc008 776 reg = <0xfc008000 0x100>;
777 atmel,usart-mo 777 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
778 interrupts = < 778 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
779 dmas = <&dma1 779 dmas = <&dma1
780 (AT91_ 780 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
781 AT91_ 781 AT91_XDMAC_DT_PERID(41))>,
782 <&dma1 782 <&dma1
783 (AT91_ 783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
784 AT91_ 784 AT91_XDMAC_DT_PERID(42))>;
785 dma-names = "t 785 dma-names = "tx", "rx";
786 clocks = <&pmc 786 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
787 clock-names = 787 clock-names = "usart";
788 status = "disa 788 status = "disabled";
789 }; 789 };
790 790
791 uart4: serial@fc00c000 791 uart4: serial@fc00c000 {
792 compatible = " 792 compatible = "atmel,at91sam9260-usart";
793 reg = <0xfc00c 793 reg = <0xfc00c000 0x100>;
794 atmel,usart-mo 794 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
795 dmas = <&dma0 795 dmas = <&dma0
796 (AT91_ 796 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
797 AT91_ 797 AT91_XDMAC_DT_PERID(43))>,
798 <&dma0 798 <&dma0
799 (AT91_ 799 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
800 AT91_ 800 AT91_XDMAC_DT_PERID(44))>;
801 dma-names = "t 801 dma-names = "tx", "rx";
802 interrupts = < 802 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
803 clocks = <&pmc 803 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
804 clock-names = 804 clock-names = "usart";
805 status = "disa 805 status = "disabled";
806 }; 806 };
807 807
808 flx2: flexcom@fc010000 808 flx2: flexcom@fc010000 {
809 compatible = " 809 compatible = "atmel,sama5d2-flexcom";
810 reg = <0xfc010 810 reg = <0xfc010000 0x200>;
811 clocks = <&pmc 811 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
812 #address-cells 812 #address-cells = <1>;
813 #size-cells = 813 #size-cells = <1>;
814 ranges = <0x0 814 ranges = <0x0 0xfc010000 0x800>;
815 status = "disa 815 status = "disabled";
816 816
817 uart7: serial@ 817 uart7: serial@200 {
818 compat 818 compatible = "atmel,at91sam9260-usart";
819 reg = 819 reg = <0x200 0x200>;
820 atmel, 820 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
821 interr 821 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
822 clocks 822 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
823 clock- 823 clock-names = "usart";
824 dmas = 824 dmas = <&dma0
825 825 (AT91_XDMAC_DT_MEM_IF(0) |
826 826 AT91_XDMAC_DT_PER_IF(1) |
827 827 AT91_XDMAC_DT_PERID(15))>,
828 828 <&dma0
829 829 (AT91_XDMAC_DT_MEM_IF(0) |
830 830 AT91_XDMAC_DT_PER_IF(1) |
831 831 AT91_XDMAC_DT_PERID(16))>;
832 dma-na 832 dma-names = "tx", "rx";
833 atmel, 833 atmel,fifo-size = <32>;
834 status 834 status = "disabled";
835 }; 835 };
836 836
837 spi4: spi@400 837 spi4: spi@400 {
838 compat 838 compatible = "atmel,at91rm9200-spi";
839 reg = 839 reg = <0x400 0x200>;
840 interr 840 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
841 #addre 841 #address-cells = <1>;
842 #size- 842 #size-cells = <0>;
843 clocks 843 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
844 clock- 844 clock-names = "spi_clk";
845 dmas = 845 dmas = <&dma0
846 846 (AT91_XDMAC_DT_MEM_IF(0) |
847 847 AT91_XDMAC_DT_PER_IF(1) |
848 848 AT91_XDMAC_DT_PERID(15))>,
849 849 <&dma0
850 850 (AT91_XDMAC_DT_MEM_IF(0) |
851 851 AT91_XDMAC_DT_PER_IF(1) |
852 852 AT91_XDMAC_DT_PERID(16))>;
853 dma-na 853 dma-names = "tx", "rx";
854 atmel, 854 atmel,fifo-size = <16>;
855 status 855 status = "disabled";
856 }; 856 };
857 857
858 i2c4: i2c@600 858 i2c4: i2c@600 {
859 compat 859 compatible = "atmel,sama5d2-i2c";
860 reg = 860 reg = <0x600 0x200>;
861 interr 861 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
862 #addre 862 #address-cells = <1>;
863 #size- 863 #size-cells = <0>;
864 clocks 864 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
865 dmas = 865 dmas = <&dma0
866 866 (AT91_XDMAC_DT_MEM_IF(0) |
867 867 AT91_XDMAC_DT_PER_IF(1) |
868 868 AT91_XDMAC_DT_PERID(15))>,
869 869 <&dma0
870 870 (AT91_XDMAC_DT_MEM_IF(0) |
871 871 AT91_XDMAC_DT_PER_IF(1) |
872 872 AT91_XDMAC_DT_PERID(16))>;
873 dma-na 873 dma-names = "tx", "rx";
874 atmel, 874 atmel,fifo-size = <16>;
875 status 875 status = "disabled";
876 }; 876 };
877 }; 877 };
878 878
879 flx3: flexcom@fc014000 879 flx3: flexcom@fc014000 {
880 compatible = " 880 compatible = "atmel,sama5d2-flexcom";
881 reg = <0xfc014 881 reg = <0xfc014000 0x200>;
882 clocks = <&pmc 882 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
883 #address-cells 883 #address-cells = <1>;
884 #size-cells = 884 #size-cells = <1>;
885 ranges = <0x0 885 ranges = <0x0 0xfc014000 0x800>;
886 status = "disa 886 status = "disabled";
887 887
888 uart8: serial@ 888 uart8: serial@200 {
889 compat 889 compatible = "atmel,at91sam9260-usart";
890 reg = 890 reg = <0x200 0x200>;
891 atmel, 891 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
892 interr 892 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
893 clocks 893 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
894 clock- 894 clock-names = "usart";
895 dmas = 895 dmas = <&dma0
896 896 (AT91_XDMAC_DT_MEM_IF(0) |
897 897 AT91_XDMAC_DT_PER_IF(1) |
898 898 AT91_XDMAC_DT_PERID(17))>,
899 899 <&dma0
900 900 (AT91_XDMAC_DT_MEM_IF(0) |
901 901 AT91_XDMAC_DT_PER_IF(1) |
902 902 AT91_XDMAC_DT_PERID(18))>;
903 dma-na 903 dma-names = "tx", "rx";
904 atmel, 904 atmel,fifo-size = <32>;
905 status 905 status = "disabled";
906 }; 906 };
907 907
908 spi5: spi@400 908 spi5: spi@400 {
909 compat 909 compatible = "atmel,at91rm9200-spi";
910 reg = 910 reg = <0x400 0x200>;
911 interr 911 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
912 #addre 912 #address-cells = <1>;
913 #size- 913 #size-cells = <0>;
914 clocks 914 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
915 clock- 915 clock-names = "spi_clk";
916 dmas = 916 dmas = <&dma0
917 917 (AT91_XDMAC_DT_MEM_IF(0) |
918 918 AT91_XDMAC_DT_PER_IF(1) |
919 919 AT91_XDMAC_DT_PERID(17))>,
920 920 <&dma0
921 921 (AT91_XDMAC_DT_MEM_IF(0) |
922 922 AT91_XDMAC_DT_PER_IF(1) |
923 923 AT91_XDMAC_DT_PERID(18))>;
924 dma-na 924 dma-names = "tx", "rx";
925 atmel, 925 atmel,fifo-size = <16>;
926 status 926 status = "disabled";
927 }; 927 };
928 928
929 i2c5: i2c@600 929 i2c5: i2c@600 {
930 compat 930 compatible = "atmel,sama5d2-i2c";
931 reg = 931 reg = <0x600 0x200>;
932 interr 932 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
933 #addre 933 #address-cells = <1>;
934 #size- 934 #size-cells = <0>;
935 clocks 935 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
936 dmas = 936 dmas = <&dma0
937 937 (AT91_XDMAC_DT_MEM_IF(0) |
938 938 AT91_XDMAC_DT_PER_IF(1) |
939 939 AT91_XDMAC_DT_PERID(17))>,
940 940 <&dma0
941 941 (AT91_XDMAC_DT_MEM_IF(0) |
942 942 AT91_XDMAC_DT_PER_IF(1) |
943 943 AT91_XDMAC_DT_PERID(18))>;
944 dma-na 944 dma-names = "tx", "rx";
945 atmel, 945 atmel,fifo-size = <16>;
946 status 946 status = "disabled";
947 }; 947 };
948 948
949 }; 949 };
950 950
951 flx4: flexcom@fc018000 951 flx4: flexcom@fc018000 {
952 compatible = " 952 compatible = "atmel,sama5d2-flexcom";
953 reg = <0xfc018 953 reg = <0xfc018000 0x200>;
954 clocks = <&pmc 954 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
955 #address-cells 955 #address-cells = <1>;
956 #size-cells = 956 #size-cells = <1>;
957 ranges = <0x0 957 ranges = <0x0 0xfc018000 0x800>;
958 status = "disa 958 status = "disabled";
959 959
960 uart9: serial@ 960 uart9: serial@200 {
961 compat 961 compatible = "atmel,at91sam9260-usart";
962 reg = 962 reg = <0x200 0x200>;
963 atmel, 963 atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
964 interr 964 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
965 clocks 965 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
966 clock- 966 clock-names = "usart";
967 dmas = 967 dmas = <&dma0
968 968 (AT91_XDMAC_DT_MEM_IF(0) |
969 969 AT91_XDMAC_DT_PER_IF(1) |
970 970 AT91_XDMAC_DT_PERID(19))>,
971 971 <&dma0
972 972 (AT91_XDMAC_DT_MEM_IF(0) |
973 973 AT91_XDMAC_DT_PER_IF(1) |
974 974 AT91_XDMAC_DT_PERID(20))>;
975 dma-na 975 dma-names = "tx", "rx";
976 atmel, 976 atmel,fifo-size = <32>;
977 status 977 status = "disabled";
978 }; 978 };
979 979
980 spi6: spi@400 980 spi6: spi@400 {
981 compat 981 compatible = "atmel,at91rm9200-spi";
982 reg = 982 reg = <0x400 0x200>;
983 interr 983 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
984 #addre 984 #address-cells = <1>;
985 #size- 985 #size-cells = <0>;
986 clocks 986 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
987 clock- 987 clock-names = "spi_clk";
988 dmas = 988 dmas = <&dma0
989 989 (AT91_XDMAC_DT_MEM_IF(0) |
990 990 AT91_XDMAC_DT_PER_IF(1) |
991 991 AT91_XDMAC_DT_PERID(19))>,
992 992 <&dma0
993 993 (AT91_XDMAC_DT_MEM_IF(0) |
994 994 AT91_XDMAC_DT_PER_IF(1) |
995 995 AT91_XDMAC_DT_PERID(20))>;
996 dma-na 996 dma-names = "tx", "rx";
997 atmel, 997 atmel,fifo-size = <16>;
998 status 998 status = "disabled";
999 }; 999 };
1000 1000
1001 i2c6: i2c@600 1001 i2c6: i2c@600 {
1002 compa 1002 compatible = "atmel,sama5d2-i2c";
1003 reg = 1003 reg = <0x600 0x200>;
1004 inter 1004 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
1005 #addr 1005 #address-cells = <1>;
1006 #size 1006 #size-cells = <0>;
1007 clock 1007 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
1008 dmas 1008 dmas = <&dma0
1009 1009 (AT91_XDMAC_DT_MEM_IF(0) |
1010 1010 AT91_XDMAC_DT_PER_IF(1) |
1011 1011 AT91_XDMAC_DT_PERID(19))>,
1012 1012 <&dma0
1013 1013 (AT91_XDMAC_DT_MEM_IF(0) |
1014 1014 AT91_XDMAC_DT_PER_IF(1) |
1015 1015 AT91_XDMAC_DT_PERID(20))>;
1016 dma-n 1016 dma-names = "tx", "rx";
1017 atmel 1017 atmel,fifo-size = <16>;
1018 statu 1018 status = "disabled";
1019 }; 1019 };
1020 }; 1020 };
1021 1021
1022 trng@fc01c000 { 1022 trng@fc01c000 {
1023 compatible = 1023 compatible = "atmel,at91sam9g45-trng";
1024 reg = <0xfc01 1024 reg = <0xfc01c000 0x100>;
1025 interrupts = 1025 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1026 clocks = <&pm 1026 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
1027 }; 1027 };
1028 1028
1029 aic: interrupt-contro 1029 aic: interrupt-controller@fc020000 {
1030 #interrupt-ce 1030 #interrupt-cells = <3>;
1031 compatible = 1031 compatible = "atmel,sama5d2-aic";
1032 interrupt-con 1032 interrupt-controller;
1033 reg = <0xfc02 1033 reg = <0xfc020000 0x200>;
1034 atmel,externa 1034 atmel,external-irqs = <49>;
1035 }; 1035 };
1036 1036
1037 i2c1: i2c@fc028000 { 1037 i2c1: i2c@fc028000 {
1038 compatible = 1038 compatible = "atmel,sama5d2-i2c";
1039 reg = <0xfc02 1039 reg = <0xfc028000 0x100>;
1040 interrupts = 1040 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1041 dmas = <&dma0 1041 dmas = <&dma0
1042 (AT91 1042 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1043 AT91 1043 AT91_XDMAC_DT_PERID(2))>,
1044 <&dma0 1044 <&dma0
1045 (AT91 1045 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1046 AT91 1046 AT91_XDMAC_DT_PERID(3))>;
1047 dma-names = " 1047 dma-names = "tx", "rx";
1048 #address-cell 1048 #address-cells = <1>;
1049 #size-cells = 1049 #size-cells = <0>;
1050 clocks = <&pm 1050 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
1051 atmel,fifo-si 1051 atmel,fifo-size = <16>;
1052 status = "dis 1052 status = "disabled";
1053 }; 1053 };
1054 1054
1055 adc: adc@fc030000 { 1055 adc: adc@fc030000 {
1056 compatible = 1056 compatible = "atmel,sama5d2-adc";
1057 reg = <0xfc03 1057 reg = <0xfc030000 0x100>;
1058 interrupts = 1058 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1059 clocks = <&pm 1059 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
1060 clock-names = 1060 clock-names = "adc_clk";
1061 dmas = <&dma0 1061 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1062 dma-names = " 1062 dma-names = "rx";
1063 atmel,min-sam 1063 atmel,min-sample-rate-hz = <200000>;
1064 atmel,max-sam 1064 atmel,max-sample-rate-hz = <20000000>;
1065 atmel,startup 1065 atmel,startup-time-ms = <4>;
1066 atmel,trigger 1066 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1067 #io-channel-c 1067 #io-channel-cells = <1>;
1068 status = "dis 1068 status = "disabled";
1069 }; 1069 };
1070 1070
1071 pioA: pinctrl@fc03800 1071 pioA: pinctrl@fc038000 {
1072 compatible = 1072 compatible = "atmel,sama5d2-pinctrl";
1073 reg = <0xfc03 1073 reg = <0xfc038000 0x600>;
1074 interrupts = 1074 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1075 1075 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1076 1076 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1077 1077 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1078 interrupt-con 1078 interrupt-controller;
1079 #interrupt-ce 1079 #interrupt-cells = <2>;
1080 gpio-controll 1080 gpio-controller;
1081 #gpio-cells = 1081 #gpio-cells = <2>;
1082 clocks = <&pm 1082 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1083 }; 1083 };
1084 1084
1085 pioBU: secumod@fc0400 1085 pioBU: secumod@fc040000 {
1086 compatible = 1086 compatible = "atmel,sama5d2-secumod", "syscon";
1087 reg = <0xfc04 1087 reg = <0xfc040000 0x100>;
1088 1088
1089 gpio-controll 1089 gpio-controller;
1090 #gpio-cells = 1090 #gpio-cells = <2>;
1091 }; 1091 };
1092 1092
1093 tdes: crypto@fc044000 1093 tdes: crypto@fc044000 {
1094 compatible = 1094 compatible = "atmel,at91sam9g46-tdes";
1095 reg = <0xfc04 1095 reg = <0xfc044000 0x100>;
1096 interrupts = 1096 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1097 dmas = <&dma0 1097 dmas = <&dma0
1098 (AT91 1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1099 AT91 1099 AT91_XDMAC_DT_PERID(28))>,
1100 <&dma0 1100 <&dma0
1101 (AT91 1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1102 AT91 1102 AT91_XDMAC_DT_PERID(29))>;
1103 dma-names = " 1103 dma-names = "tx", "rx";
1104 clocks = <&pm 1104 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1105 clock-names = 1105 clock-names = "tdes_clk";
1106 }; 1106 };
1107 1107
1108 classd: classd@fc0480 1108 classd: classd@fc048000 {
1109 compatible = 1109 compatible = "atmel,sama5d2-classd";
1110 reg = <0xfc04 1110 reg = <0xfc048000 0x100>;
1111 interrupts = 1111 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1112 dmas = <&dma0 1112 dmas = <&dma0
1113 (AT91 1113 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1114 AT91 1114 AT91_XDMAC_DT_PERID(47))>;
1115 dma-names = " 1115 dma-names = "tx";
1116 clocks = <&pm 1116 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
1117 clock-names = 1117 clock-names = "pclk", "gclk";
1118 status = "dis 1118 status = "disabled";
1119 }; 1119 };
1120 1120
1121 i2s1: i2s@fc04c000 { 1121 i2s1: i2s@fc04c000 {
1122 compatible = 1122 compatible = "atmel,sama5d2-i2s";
1123 reg = <0xfc04 1123 reg = <0xfc04c000 0x100>;
1124 interrupts = 1124 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1125 dmas = <&dma0 1125 dmas = <&dma0
1126 (AT91 1126 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1127 AT91 1127 AT91_XDMAC_DT_PERID(33))>,
1128 <&dma0 1128 <&dma0
1129 (AT91 1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1130 AT91 1130 AT91_XDMAC_DT_PERID(34))>;
1131 dma-names = " 1131 dma-names = "tx", "rx";
1132 clocks = <&pm 1132 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
1133 clock-names = 1133 clock-names = "pclk", "gclk";
1134 assigned-cloc 1134 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
1135 assigned-cloc 1135 assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>;
1136 status = "dis 1136 status = "disabled";
1137 }; 1137 };
1138 1138
1139 can1: can@fc050000 { 1139 can1: can@fc050000 {
1140 compatible = 1140 compatible = "bosch,m_can";
1141 reg = <0xfc05 1141 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1142 reg-names = " 1142 reg-names = "m_can", "message_ram";
1143 interrupts = 1143 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1144 1144 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1145 interrupt-nam 1145 interrupt-names = "int0", "int1";
1146 clocks = <&pm 1146 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1147 clock-names = 1147 clock-names = "hclk", "cclk";
1148 assigned-cloc 1148 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
1149 assigned-cloc 1149 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
1150 assigned-cloc 1150 assigned-clock-rates = <40000000>;
1151 bosch,mram-cf 1151 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1152 status = "dis 1152 status = "disabled";
1153 }; 1153 };
1154 1154
1155 sfrbu: sfr@fc05c000 { 1155 sfrbu: sfr@fc05c000 {
1156 compatible = 1156 compatible = "atmel,sama5d2-sfrbu", "syscon";
1157 reg = <0xfc05 1157 reg = <0xfc05c000 0x20>;
1158 }; 1158 };
1159 1159
1160 chipid@fc069000 { 1160 chipid@fc069000 {
1161 compatible = 1161 compatible = "atmel,sama5d2-chipid";
1162 reg = <0xfc06 1162 reg = <0xfc069000 0x8>;
1163 }; 1163 };
1164 }; 1164 };
1165 }; 1165 };
1166 }; 1166 };
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