1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
>> 3 * linux/arch/arm/boot/nspire.dtsi
>> 4 *
3 * Copyright (C) 2013 Daniel Tang <tangrs@tang 5 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
4 */ 6 */
5 7
6 / { 8 / {
7 #address-cells = <1>; 9 #address-cells = <1>;
8 #size-cells = <1>; 10 #size-cells = <1>;
9 interrupt-parent = <&intc>; 11 interrupt-parent = <&intc>;
10 12
11 cpus { 13 cpus {
12 #address-cells = <1>; <<
13 #size-cells = <0>; <<
14 <<
15 cpu@0 { 14 cpu@0 {
16 compatible = "arm,arm9 15 compatible = "arm,arm926ej-s";
17 device_type = "cpu"; <<
18 reg = <0>; <<
19 }; 16 };
20 }; 17 };
21 18
22 bootrom: bootrom@0 { 19 bootrom: bootrom@0 {
23 reg = <0x00000000 0x80000>; 20 reg = <0x00000000 0x80000>;
24 }; 21 };
25 22
26 sram: sram@a4000000 { 23 sram: sram@a4000000 {
27 compatible = "mmio-sram"; !! 24 device = "memory";
28 reg = <0xa4000000 0x20000>; /* !! 25 reg = <0xa4000000 0x20000>;
29 #address-cells = <1>; <<
30 #size-cells = <1>; <<
31 ranges = <0 0xa4000000 0x20000 <<
32 <<
33 sram@0 { <<
34 reg = <0x0 0x20000>; <<
35 }; <<
36 }; 26 };
37 27
38 timer_clk: timer_clk { 28 timer_clk: timer_clk {
39 #clock-cells = <0>; 29 #clock-cells = <0>;
40 compatible = "fixed-clock"; 30 compatible = "fixed-clock";
41 clock-frequency = <32768>; 31 clock-frequency = <32768>;
42 }; 32 };
43 33
44 base_clk: base_clk { 34 base_clk: base_clk {
45 #clock-cells = <0>; 35 #clock-cells = <0>;
46 reg = <0x900b0024 0x4>; 36 reg = <0x900b0024 0x4>;
47 }; 37 };
48 38
49 ahb_clk: ahb_clk { 39 ahb_clk: ahb_clk {
50 #clock-cells = <0>; 40 #clock-cells = <0>;
51 reg = <0x900b0024 0x4>; 41 reg = <0x900b0024 0x4>;
52 clocks = <&base_clk>; 42 clocks = <&base_clk>;
53 }; 43 };
54 44
55 apb_pclk: apb_pclk { 45 apb_pclk: apb_pclk {
56 #clock-cells = <0>; 46 #clock-cells = <0>;
57 compatible = "fixed-factor-clo 47 compatible = "fixed-factor-clock";
58 clock-div = <2>; 48 clock-div = <2>;
59 clock-mult = <1>; 49 clock-mult = <1>;
60 clocks = <&ahb_clk>; 50 clocks = <&ahb_clk>;
61 }; 51 };
62 52
63 usb_phy: usb_phy { 53 usb_phy: usb_phy {
64 compatible = "usb-nop-xceiv"; 54 compatible = "usb-nop-xceiv";
65 #phy-cells = <0>; 55 #phy-cells = <0>;
66 }; 56 };
67 57
68 vbus_reg: vbus_reg { 58 vbus_reg: vbus_reg {
69 compatible = "regulator-fixed" 59 compatible = "regulator-fixed";
70 60
71 regulator-name = "USB VBUS out 61 regulator-name = "USB VBUS output";
>> 62 regulator-type = "voltage";
72 63
73 regulator-min-microvolt = <500 64 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <500 65 regulator-max-microvolt = <5000000>;
75 }; 66 };
76 67
77 ahb { 68 ahb {
78 compatible = "simple-bus"; 69 compatible = "simple-bus";
79 #address-cells = <1>; 70 #address-cells = <1>;
80 #size-cells = <1>; 71 #size-cells = <1>;
81 ranges; 72 ranges;
82 73
83 spi: spi@a9000000 { 74 spi: spi@a9000000 {
84 reg = <0xa9000000 0x10 75 reg = <0xa9000000 0x1000>;
85 }; 76 };
86 77
87 usb0: usb@b0000000 { 78 usb0: usb@b0000000 {
88 compatible = "lsi,zevi 79 compatible = "lsi,zevio-usb";
89 reg = <0xb0000000 0x10 80 reg = <0xb0000000 0x1000>;
90 interrupts = <8>; 81 interrupts = <8>;
91 82
92 usb-phy = <&usb_phy>; 83 usb-phy = <&usb_phy>;
93 vbus-supply = <&vbus_r 84 vbus-supply = <&vbus_reg>;
94 }; 85 };
95 86
96 usb1: usb@b4000000 { 87 usb1: usb@b4000000 {
97 reg = <0xb4000000 0x10 88 reg = <0xb4000000 0x1000>;
98 interrupts = <9>; 89 interrupts = <9>;
99 status = "disabled"; 90 status = "disabled";
100 }; 91 };
101 92
102 lcd: lcd@c0000000 { 93 lcd: lcd@c0000000 {
103 compatible = "arm,pl11 94 compatible = "arm,pl111", "arm,primecell";
104 reg = <0xc0000000 0x10 95 reg = <0xc0000000 0x1000>;
105 interrupts = <21>; 96 interrupts = <21>;
106 97
107 /* 98 /*
108 * We assume the same 99 * We assume the same clock is fed to APB and CLCDCLK.
109 * There is some code 100 * There is some code to scale the clock down by a factor
110 * 48 for the display 101 * 48 for the display so likely the frequency to the
111 * display is 1MHz and 102 * display is 1MHz and the CLCDCLK is 48 MHz.
112 */ 103 */
113 clocks = <&apb_pclk>, 104 clocks = <&apb_pclk>, <&apb_pclk>;
114 clock-names = "clcdclk 105 clock-names = "clcdclk", "apb_pclk";
115 }; 106 };
116 107
117 adc: adc@c4000000 { 108 adc: adc@c4000000 {
118 reg = <0xc4000000 0x10 109 reg = <0xc4000000 0x1000>;
119 interrupts = <11>; 110 interrupts = <11>;
120 }; 111 };
121 112
122 tdes: crypto@c8010000 { 113 tdes: crypto@c8010000 {
123 reg = <0xc8010000 0x10 114 reg = <0xc8010000 0x1000>;
124 }; 115 };
125 116
126 sha256: crypto@cc000000 { 117 sha256: crypto@cc000000 {
127 reg = <0xcc000000 0x10 118 reg = <0xcc000000 0x1000>;
128 }; 119 };
129 120
130 apb@90000000 { 121 apb@90000000 {
131 compatible = "simple-b 122 compatible = "simple-bus";
132 #address-cells = <1>; 123 #address-cells = <1>;
133 #size-cells = <1>; 124 #size-cells = <1>;
134 clock-ranges; 125 clock-ranges;
135 ranges; 126 ranges;
136 127
137 gpio: gpio@90000000 { 128 gpio: gpio@90000000 {
138 compatible = " 129 compatible = "lsi,zevio-gpio";
139 reg = <0x90000 130 reg = <0x90000000 0x1000>;
140 interrupts = < 131 interrupts = <7>;
141 gpio-controlle 132 gpio-controller;
142 #gpio-cells = 133 #gpio-cells = <2>;
143 }; 134 };
144 135
145 fast_timer: timer@9001 136 fast_timer: timer@90010000 {
146 reg = <0x90010 137 reg = <0x90010000 0x1000>;
147 interrupts = < 138 interrupts = <17>;
148 }; 139 };
149 140
150 uart: serial@90020000 141 uart: serial@90020000 {
151 reg = <0x90020 142 reg = <0x90020000 0x1000>;
152 interrupts = < 143 interrupts = <1>;
153 }; 144 };
154 145
155 timer0: timer@900c0000 146 timer0: timer@900c0000 {
156 reg = <0x900c0 147 reg = <0x900c0000 0x1000>;
157 clocks = <&tim 148 clocks = <&timer_clk>, <&timer_clk>,
158 <&tim 149 <&timer_clk>;
159 clock-names = 150 clock-names = "timer0clk", "timer1clk",
160 151 "apb_pclk";
161 }; 152 };
162 153
163 timer1: timer@900d0000 154 timer1: timer@900d0000 {
164 reg = <0x900d0 155 reg = <0x900d0000 0x1000>;
165 interrupts = < 156 interrupts = <19>;
166 clocks = <&tim 157 clocks = <&timer_clk>, <&timer_clk>,
167 <&tim 158 <&timer_clk>;
168 clock-names = 159 clock-names = "timer0clk", "timer1clk",
169 160 "apb_pclk";
170 }; 161 };
171 162
172 watchdog: watchdog@900 163 watchdog: watchdog@90060000 {
173 compatible = " !! 164 compatible = "arm,primecell";
174 reg = <0x90060 165 reg = <0x90060000 0x1000>;
175 interrupts = < 166 interrupts = <3>;
176 clocks = <&apb <<
177 clock-names = <<
178 status = "disa <<
179 }; 167 };
180 168
181 rtc: rtc@90090000 { 169 rtc: rtc@90090000 {
182 reg = <0x90090 170 reg = <0x90090000 0x1000>;
183 interrupts = < 171 interrupts = <4>;
184 }; 172 };
185 173
186 misc: misc@900a0000 { 174 misc: misc@900a0000 {
187 compatible = " <<
188 reg = <0x900a0 175 reg = <0x900a0000 0x1000>;
189 <<
190 reboot { <<
191 compat <<
192 offset <<
193 value <<
194 }; <<
195 }; 176 };
196 177
197 pwr: pwr@900b0000 { 178 pwr: pwr@900b0000 {
198 reg = <0x900b0 179 reg = <0x900b0000 0x1000>;
199 interrupts = < 180 interrupts = <15>;
200 }; 181 };
201 182
202 keypad: input@900e0000 183 keypad: input@900e0000 {
203 compatible = " 184 compatible = "ti,nspire-keypad";
204 reg = <0x900e0 185 reg = <0x900e0000 0x1000>;
205 interrupts = < 186 interrupts = <16>;
206 187
207 scan-interval 188 scan-interval = <1000>;
208 row-delay = <2 189 row-delay = <200>;
209 190
210 clocks = <&apb 191 clocks = <&apb_pclk>;
211 }; 192 };
212 193
213 contrast: contrast@900 194 contrast: contrast@900f0000 {
214 reg = <0x900f0 195 reg = <0x900f0000 0x1000>;
215 }; 196 };
216 197
217 led: led@90110000 { 198 led: led@90110000 {
218 reg = <0x90110 199 reg = <0x90110000 0x1000>;
219 }; 200 };
220 }; 201 };
221 }; 202 };
222 }; 203 };
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