1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2013 Daniel Tang <tangrs@tang 3 * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
4 */ 4 */
5 5
6 / { 6 / {
7 #address-cells = <1>; 7 #address-cells = <1>;
8 #size-cells = <1>; 8 #size-cells = <1>;
9 interrupt-parent = <&intc>; 9 interrupt-parent = <&intc>;
10 10
11 cpus { 11 cpus {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <0>; 13 #size-cells = <0>;
14 14
15 cpu@0 { 15 cpu@0 {
16 compatible = "arm,arm9 16 compatible = "arm,arm926ej-s";
17 device_type = "cpu"; 17 device_type = "cpu";
18 reg = <0>; 18 reg = <0>;
19 }; 19 };
20 }; 20 };
21 21
22 bootrom: bootrom@0 { 22 bootrom: bootrom@0 {
23 reg = <0x00000000 0x80000>; 23 reg = <0x00000000 0x80000>;
24 }; 24 };
25 25
26 sram: sram@a4000000 { 26 sram: sram@a4000000 {
27 compatible = "mmio-sram"; 27 compatible = "mmio-sram";
28 reg = <0xa4000000 0x20000>; /* 28 reg = <0xa4000000 0x20000>; /* 128k */
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <1>; 30 #size-cells = <1>;
31 ranges = <0 0xa4000000 0x20000 31 ranges = <0 0xa4000000 0x20000>;
32 32
33 sram@0 { 33 sram@0 {
34 reg = <0x0 0x20000>; 34 reg = <0x0 0x20000>;
35 }; 35 };
36 }; 36 };
37 37
38 timer_clk: timer_clk { 38 timer_clk: timer_clk {
39 #clock-cells = <0>; 39 #clock-cells = <0>;
40 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
41 clock-frequency = <32768>; 41 clock-frequency = <32768>;
42 }; 42 };
43 43
44 base_clk: base_clk { 44 base_clk: base_clk {
45 #clock-cells = <0>; 45 #clock-cells = <0>;
46 reg = <0x900b0024 0x4>; 46 reg = <0x900b0024 0x4>;
47 }; 47 };
48 48
49 ahb_clk: ahb_clk { 49 ahb_clk: ahb_clk {
50 #clock-cells = <0>; 50 #clock-cells = <0>;
51 reg = <0x900b0024 0x4>; 51 reg = <0x900b0024 0x4>;
52 clocks = <&base_clk>; 52 clocks = <&base_clk>;
53 }; 53 };
54 54
55 apb_pclk: apb_pclk { 55 apb_pclk: apb_pclk {
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 compatible = "fixed-factor-clo 57 compatible = "fixed-factor-clock";
58 clock-div = <2>; 58 clock-div = <2>;
59 clock-mult = <1>; 59 clock-mult = <1>;
60 clocks = <&ahb_clk>; 60 clocks = <&ahb_clk>;
61 }; 61 };
62 62
63 usb_phy: usb_phy { 63 usb_phy: usb_phy {
64 compatible = "usb-nop-xceiv"; 64 compatible = "usb-nop-xceiv";
65 #phy-cells = <0>; 65 #phy-cells = <0>;
66 }; 66 };
67 67
68 vbus_reg: vbus_reg { 68 vbus_reg: vbus_reg {
69 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
70 70
71 regulator-name = "USB VBUS out 71 regulator-name = "USB VBUS output";
72 72
73 regulator-min-microvolt = <500 73 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <500 74 regulator-max-microvolt = <5000000>;
75 }; 75 };
76 76
77 ahb { 77 ahb {
78 compatible = "simple-bus"; 78 compatible = "simple-bus";
79 #address-cells = <1>; 79 #address-cells = <1>;
80 #size-cells = <1>; 80 #size-cells = <1>;
81 ranges; 81 ranges;
82 82
83 spi: spi@a9000000 { 83 spi: spi@a9000000 {
84 reg = <0xa9000000 0x10 84 reg = <0xa9000000 0x1000>;
85 }; 85 };
86 86
87 usb0: usb@b0000000 { 87 usb0: usb@b0000000 {
88 compatible = "lsi,zevi 88 compatible = "lsi,zevio-usb";
89 reg = <0xb0000000 0x10 89 reg = <0xb0000000 0x1000>;
90 interrupts = <8>; 90 interrupts = <8>;
91 91
92 usb-phy = <&usb_phy>; 92 usb-phy = <&usb_phy>;
93 vbus-supply = <&vbus_r 93 vbus-supply = <&vbus_reg>;
94 }; 94 };
95 95
96 usb1: usb@b4000000 { 96 usb1: usb@b4000000 {
97 reg = <0xb4000000 0x10 97 reg = <0xb4000000 0x1000>;
98 interrupts = <9>; 98 interrupts = <9>;
99 status = "disabled"; 99 status = "disabled";
100 }; 100 };
101 101
102 lcd: lcd@c0000000 { 102 lcd: lcd@c0000000 {
103 compatible = "arm,pl11 103 compatible = "arm,pl111", "arm,primecell";
104 reg = <0xc0000000 0x10 104 reg = <0xc0000000 0x1000>;
105 interrupts = <21>; 105 interrupts = <21>;
106 106
107 /* 107 /*
108 * We assume the same 108 * We assume the same clock is fed to APB and CLCDCLK.
109 * There is some code 109 * There is some code to scale the clock down by a factor
110 * 48 for the display 110 * 48 for the display so likely the frequency to the
111 * display is 1MHz and 111 * display is 1MHz and the CLCDCLK is 48 MHz.
112 */ 112 */
113 clocks = <&apb_pclk>, 113 clocks = <&apb_pclk>, <&apb_pclk>;
114 clock-names = "clcdclk 114 clock-names = "clcdclk", "apb_pclk";
115 }; 115 };
116 116
117 adc: adc@c4000000 { 117 adc: adc@c4000000 {
118 reg = <0xc4000000 0x10 118 reg = <0xc4000000 0x1000>;
119 interrupts = <11>; 119 interrupts = <11>;
120 }; 120 };
121 121
122 tdes: crypto@c8010000 { 122 tdes: crypto@c8010000 {
123 reg = <0xc8010000 0x10 123 reg = <0xc8010000 0x1000>;
124 }; 124 };
125 125
126 sha256: crypto@cc000000 { 126 sha256: crypto@cc000000 {
127 reg = <0xcc000000 0x10 127 reg = <0xcc000000 0x1000>;
128 }; 128 };
129 129
130 apb@90000000 { 130 apb@90000000 {
131 compatible = "simple-b 131 compatible = "simple-bus";
132 #address-cells = <1>; 132 #address-cells = <1>;
133 #size-cells = <1>; 133 #size-cells = <1>;
134 clock-ranges; 134 clock-ranges;
135 ranges; 135 ranges;
136 136
137 gpio: gpio@90000000 { 137 gpio: gpio@90000000 {
138 compatible = " 138 compatible = "lsi,zevio-gpio";
139 reg = <0x90000 139 reg = <0x90000000 0x1000>;
140 interrupts = < 140 interrupts = <7>;
141 gpio-controlle 141 gpio-controller;
142 #gpio-cells = 142 #gpio-cells = <2>;
143 }; 143 };
144 144
145 fast_timer: timer@9001 145 fast_timer: timer@90010000 {
146 reg = <0x90010 146 reg = <0x90010000 0x1000>;
147 interrupts = < 147 interrupts = <17>;
148 }; 148 };
149 149
150 uart: serial@90020000 150 uart: serial@90020000 {
151 reg = <0x90020 151 reg = <0x90020000 0x1000>;
152 interrupts = < 152 interrupts = <1>;
153 }; 153 };
154 154
155 timer0: timer@900c0000 155 timer0: timer@900c0000 {
156 reg = <0x900c0 156 reg = <0x900c0000 0x1000>;
157 clocks = <&tim 157 clocks = <&timer_clk>, <&timer_clk>,
158 <&tim 158 <&timer_clk>;
159 clock-names = 159 clock-names = "timer0clk", "timer1clk",
160 160 "apb_pclk";
161 }; 161 };
162 162
163 timer1: timer@900d0000 163 timer1: timer@900d0000 {
164 reg = <0x900d0 164 reg = <0x900d0000 0x1000>;
165 interrupts = < 165 interrupts = <19>;
166 clocks = <&tim 166 clocks = <&timer_clk>, <&timer_clk>,
167 <&tim 167 <&timer_clk>;
168 clock-names = 168 clock-names = "timer0clk", "timer1clk",
169 169 "apb_pclk";
170 }; 170 };
171 171
172 watchdog: watchdog@900 172 watchdog: watchdog@90060000 {
173 compatible = " !! 173 compatible = "arm,primecell";
174 reg = <0x90060 174 reg = <0x90060000 0x1000>;
175 interrupts = < 175 interrupts = <3>;
176 clocks = <&apb <<
177 clock-names = <<
178 status = "disa <<
179 }; 176 };
180 177
181 rtc: rtc@90090000 { 178 rtc: rtc@90090000 {
182 reg = <0x90090 179 reg = <0x90090000 0x1000>;
183 interrupts = < 180 interrupts = <4>;
184 }; 181 };
185 182
186 misc: misc@900a0000 { 183 misc: misc@900a0000 {
187 compatible = " 184 compatible = "ti,nspire-misc", "syscon", "simple-mfd";
188 reg = <0x900a0 185 reg = <0x900a0000 0x1000>;
189 186
190 reboot { 187 reboot {
191 compat 188 compatible = "syscon-reboot";
192 offset 189 offset = <0x08>;
193 value 190 value = <0x02>;
194 }; 191 };
195 }; 192 };
196 193
197 pwr: pwr@900b0000 { 194 pwr: pwr@900b0000 {
198 reg = <0x900b0 195 reg = <0x900b0000 0x1000>;
199 interrupts = < 196 interrupts = <15>;
200 }; 197 };
201 198
202 keypad: input@900e0000 199 keypad: input@900e0000 {
203 compatible = " 200 compatible = "ti,nspire-keypad";
204 reg = <0x900e0 201 reg = <0x900e0000 0x1000>;
205 interrupts = < 202 interrupts = <16>;
206 203
207 scan-interval 204 scan-interval = <1000>;
208 row-delay = <2 205 row-delay = <200>;
209 206
210 clocks = <&apb 207 clocks = <&apb_pclk>;
211 }; 208 };
212 209
213 contrast: contrast@900 210 contrast: contrast@900f0000 {
214 reg = <0x900f0 211 reg = <0x900f0000 0x1000>;
215 }; 212 };
216 213
217 led: led@90110000 { 214 led: led@90110000 {
218 reg = <0x90110 215 reg = <0x90110000 0x1000>;
219 }; 216 };
220 }; 217 };
221 }; 218 };
222 }; 219 };
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