1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018 Nuvoton Technology tomer 2 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3 // Copyright 2018 Google, Inc. 3 // Copyright 2018 Google, Inc.
4 4
5 #include <dt-bindings/interrupt-controller/arm 5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-cl 6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-re 7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
8 8
9 / { 9 / {
10 #address-cells = <1>; 10 #address-cells = <1>;
11 #size-cells = <1>; 11 #size-cells = <1>;
12 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
13 13
14 /* external reference clock */ 14 /* external reference clock */
15 clk_refclk: clk_refclk { 15 clk_refclk: clk_refclk {
16 compatible = "fixed-clock"; 16 compatible = "fixed-clock";
17 #clock-cells = <0>; 17 #clock-cells = <0>;
18 clock-frequency = <25000000>; 18 clock-frequency = <25000000>;
19 clock-output-names = "refclk"; 19 clock-output-names = "refclk";
20 }; 20 };
21 21
22 /* external reference clock for cpu. f 22 /* external reference clock for cpu. float in normal operation */
23 clk_sysbypck: clk_sysbypck { 23 clk_sysbypck: clk_sysbypck {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 clock-frequency = <800000000>; 26 clock-frequency = <800000000>;
27 clock-output-names = "sysbypck 27 clock-output-names = "sysbypck";
28 }; 28 };
29 29
30 /* external reference clock for MC. fl 30 /* external reference clock for MC. float in normal operation */
31 clk_mcbypck: clk_mcbypck { 31 clk_mcbypck: clk_mcbypck {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <800000000>; 34 clock-frequency = <800000000>;
35 clock-output-names = "mcbypck" 35 clock-output-names = "mcbypck";
36 }; 36 };
37 37
38 /* external clock signal rg1refck, su 38 /* external clock signal rg1refck, supplied by the phy */
39 clk_rg1refck: clk_rg1refck { 39 clk_rg1refck: clk_rg1refck {
40 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
41 #clock-cells = <0>; 41 #clock-cells = <0>;
42 clock-frequency = <125000000>; 42 clock-frequency = <125000000>;
43 clock-output-names = "clk_rg1r 43 clock-output-names = "clk_rg1refck";
44 }; 44 };
45 45
46 /* external clock signal rg2refck, su 46 /* external clock signal rg2refck, supplied by the phy */
47 clk_rg2refck: clk_rg2refck { 47 clk_rg2refck: clk_rg2refck {
48 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
49 #clock-cells = <0>; 49 #clock-cells = <0>;
50 clock-frequency = <125000000>; 50 clock-frequency = <125000000>;
51 clock-output-names = "clk_rg2r 51 clock-output-names = "clk_rg2refck";
52 }; 52 };
53 53
54 clk_xin: clk_xin { 54 clk_xin: clk_xin {
55 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 clock-frequency = <50000000>; 57 clock-frequency = <50000000>;
58 clock-output-names = "clk_xin" 58 clock-output-names = "clk_xin";
59 }; 59 };
60 60
61 soc { 61 soc {
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <1>; 63 #size-cells = <1>;
64 compatible = "simple-bus"; 64 compatible = "simple-bus";
65 interrupt-parent = <&gic>; 65 interrupt-parent = <&gic>;
66 ranges = <0x0 0xf0000000 0x009 66 ranges = <0x0 0xf0000000 0x00900000>;
67 67
68 scu: scu@3fe000 { 68 scu: scu@3fe000 {
69 compatible = "arm,cort 69 compatible = "arm,cortex-a9-scu";
70 reg = <0x3fe000 0x1000 70 reg = <0x3fe000 0x1000>;
71 }; 71 };
72 72
73 l2: cache-controller@3fc000 { 73 l2: cache-controller@3fc000 {
74 compatible = "arm,pl31 74 compatible = "arm,pl310-cache";
75 reg = <0x3fc000 0x1000 75 reg = <0x3fc000 0x1000>;
76 interrupts = <GIC_SPI 76 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
77 cache-unified; 77 cache-unified;
78 cache-level = <2>; 78 cache-level = <2>;
79 clocks = <&clk NPCM7XX 79 clocks = <&clk NPCM7XX_CLK_AXI>;
80 arm,shared-override; 80 arm,shared-override;
81 }; 81 };
82 82
83 gic: interrupt-controller@3ff0 83 gic: interrupt-controller@3ff000 {
84 compatible = "arm,cort 84 compatible = "arm,cortex-a9-gic";
85 interrupt-controller; 85 interrupt-controller;
86 #interrupt-cells = <3> 86 #interrupt-cells = <3>;
87 reg = <0x3ff000 0x1000 87 reg = <0x3ff000 0x1000>,
88 <0x3fe100 0x10 88 <0x3fe100 0x100>;
89 }; 89 };
90 90
91 gcr: gcr@800000 { 91 gcr: gcr@800000 {
92 compatible = "nuvoton, 92 compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
93 reg = <0x800000 0x1000 93 reg = <0x800000 0x1000>;
94 }; 94 };
95 95
96 rst: rst@801000 { 96 rst: rst@801000 {
97 compatible = "nuvoton, 97 compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
98 reg = <0x801000 0x6C>; 98 reg = <0x801000 0x6C>;
99 }; 99 };
100 }; 100 };
101 101
102 ahb { 102 ahb {
103 #address-cells = <1>; 103 #address-cells = <1>;
104 #size-cells = <1>; 104 #size-cells = <1>;
105 compatible = "simple-bus"; 105 compatible = "simple-bus";
106 interrupt-parent = <&gic>; 106 interrupt-parent = <&gic>;
107 ranges; 107 ranges;
108 108
109 rstc: rstc@f0801000 { 109 rstc: rstc@f0801000 {
110 compatible = "nuvoton, 110 compatible = "nuvoton,npcm750-reset";
111 reg = <0xf0801000 0x70 111 reg = <0xf0801000 0x70>;
112 #reset-cells = <2>; 112 #reset-cells = <2>;
113 nuvoton,sysgcr = <&gcr 113 nuvoton,sysgcr = <&gcr>;
114 }; 114 };
115 115
116 clk: clock-controller@f0801000 116 clk: clock-controller@f0801000 {
117 compatible = "nuvoton, 117 compatible = "nuvoton,npcm750-clk", "syscon";
118 #clock-cells = <1>; 118 #clock-cells = <1>;
119 clock-controller; 119 clock-controller;
120 reg = <0xf0801000 0x10 120 reg = <0xf0801000 0x1000>;
121 clock-names = "refclk" 121 clock-names = "refclk", "sysbypck", "mcbypck";
122 clocks = <&clk_refclk> 122 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
123 }; 123 };
124 124
125 gmac0: eth@f0802000 { 125 gmac0: eth@f0802000 {
126 device_type = "network 126 device_type = "network";
127 compatible = "snps,dwm 127 compatible = "snps,dwmac";
128 reg = <0xf0802000 0x20 128 reg = <0xf0802000 0x2000>;
129 interrupts = <GIC_SPI 129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-names = "mac 130 interrupt-names = "macirq";
131 ethernet = <0>; 131 ethernet = <0>;
132 clocks = <&clk_rg1refc 132 clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
133 clock-names = "stmmace 133 clock-names = "stmmaceth", "clk_gmac";
134 pinctrl-names = "defau 134 pinctrl-names = "default";
135 pinctrl-0 = <&rg1_pins 135 pinctrl-0 = <&rg1_pins
136 &rg1md 136 &rg1mdio_pins>;
137 status = "disabled"; 137 status = "disabled";
138 }; 138 };
139 139
140 ehci1: usb@f0806000 { 140 ehci1: usb@f0806000 {
141 compatible = "nuvoton, 141 compatible = "nuvoton,npcm750-ehci";
142 reg = <0xf0806000 0x10 142 reg = <0xf0806000 0x1000>;
143 interrupts = <GIC_SPI 143 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
144 status = "disabled"; 144 status = "disabled";
145 }; 145 };
146 146
147 fiu0: spi@fb000000 { 147 fiu0: spi@fb000000 {
148 compatible = "nuvoton, 148 compatible = "nuvoton,npcm750-fiu";
149 #address-cells = <1>; 149 #address-cells = <1>;
150 #size-cells = <0>; 150 #size-cells = <0>;
151 reg = <0xfb000000 0x10 151 reg = <0xfb000000 0x1000>;
152 reg-names = "control", 152 reg-names = "control", "memory";
153 clocks = <&clk NPCM7XX 153 clocks = <&clk NPCM7XX_CLK_SPI0>;
154 clock-names = "clk_spi 154 clock-names = "clk_spi0";
155 status = "disabled"; 155 status = "disabled";
156 }; 156 };
157 157
158 fiu3: spi@c0000000 { 158 fiu3: spi@c0000000 {
159 compatible = "nuvoton, 159 compatible = "nuvoton,npcm750-fiu";
160 #address-cells = <1>; 160 #address-cells = <1>;
161 #size-cells = <0>; 161 #size-cells = <0>;
162 reg = <0xc0000000 0x10 162 reg = <0xc0000000 0x1000>;
163 reg-names = "control", 163 reg-names = "control", "memory";
164 clocks = <&clk NPCM7XX 164 clocks = <&clk NPCM7XX_CLK_SPI3>;
165 clock-names = "clk_spi 165 clock-names = "clk_spi3";
166 pinctrl-names = "defau 166 pinctrl-names = "default";
167 pinctrl-0 = <&spi3_pin 167 pinctrl-0 = <&spi3_pins>;
168 status = "disabled"; 168 status = "disabled";
169 }; 169 };
170 170
171 fiux: spi@fb001000 { 171 fiux: spi@fb001000 {
172 compatible = "nuvoton, 172 compatible = "nuvoton,npcm750-fiu";
173 #address-cells = <1>; 173 #address-cells = <1>;
174 #size-cells = <0>; 174 #size-cells = <0>;
175 reg = <0xfb001000 0x10 175 reg = <0xfb001000 0x1000>;
176 reg-names = "control", 176 reg-names = "control", "memory";
177 clocks = <&clk NPCM7XX 177 clocks = <&clk NPCM7XX_CLK_SPIX>;
178 clock-names = "clk_spi 178 clock-names = "clk_spix";
179 status = "disabled"; 179 status = "disabled";
180 }; 180 };
181 181
182 apb { 182 apb {
183 #address-cells = <1>; 183 #address-cells = <1>;
184 #size-cells = <1>; 184 #size-cells = <1>;
185 compatible = "simple-b 185 compatible = "simple-bus";
186 interrupt-parent = <&g 186 interrupt-parent = <&gic>;
187 ranges = <0x0 0xf00000 187 ranges = <0x0 0xf0000000 0x00300000>;
188 188
189 lpc_kcs: lpc_kcs@7000 189 lpc_kcs: lpc_kcs@7000 {
190 compatible = " 190 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
191 reg = <0x7000 191 reg = <0x7000 0x40>;
192 reg-io-width = 192 reg-io-width = <1>;
193 193
194 #address-cells 194 #address-cells = <1>;
195 #size-cells = 195 #size-cells = <1>;
196 ranges = <0x0 196 ranges = <0x0 0x7000 0x40>;
197 197
198 kcs1: kcs1@0 { 198 kcs1: kcs1@0 {
199 compat 199 compatible = "nuvoton,npcm750-kcs-bmc";
200 reg = 200 reg = <0x0 0x40>;
201 interr 201 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
202 kcs_ch 202 kcs_chan = <1>;
203 status 203 status = "disabled";
204 }; 204 };
205 205
206 kcs2: kcs2@0 { 206 kcs2: kcs2@0 {
207 compat 207 compatible = "nuvoton,npcm750-kcs-bmc";
208 reg = 208 reg = <0x0 0x40>;
209 interr 209 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
210 kcs_ch 210 kcs_chan = <2>;
211 status 211 status = "disabled";
212 }; 212 };
213 213
214 kcs3: kcs3@0 { 214 kcs3: kcs3@0 {
215 compat 215 compatible = "nuvoton,npcm750-kcs-bmc";
216 reg = 216 reg = <0x0 0x40>;
217 interr 217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
218 kcs_ch 218 kcs_chan = <3>;
219 status 219 status = "disabled";
220 }; 220 };
221 }; 221 };
222 222
223 peci: peci-controller@ 223 peci: peci-controller@f0100000 {
224 compatible = " 224 compatible = "nuvoton,npcm750-peci";
225 reg = <0xf0100 225 reg = <0xf0100000 0x200>;
226 interrupts = < 226 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clk 227 clocks = <&clk NPCM7XX_CLK_APB3>;
228 cmd-timeout-ms 228 cmd-timeout-ms = <1000>;
229 status = "disa 229 status = "disabled";
230 }; 230 };
231 231
232 spi0: spi@200000 { 232 spi0: spi@200000 {
233 compatible = " 233 compatible = "nuvoton,npcm750-pspi";
234 reg = <0x20000 234 reg = <0x200000 0x1000>;
235 pinctrl-names 235 pinctrl-names = "default";
236 pinctrl-0 = <& 236 pinctrl-0 = <&pspi1_pins>;
237 #address-cells 237 #address-cells = <1>;
238 #size-cells = 238 #size-cells = <0>;
239 interrupts = < 239 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clk 240 clocks = <&clk NPCM7XX_CLK_APB5>;
241 clock-names = 241 clock-names = "clk_apb5";
242 resets = <&rst 242 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
243 status = "disa 243 status = "disabled";
244 }; 244 };
245 245
246 spi1: spi@201000 { 246 spi1: spi@201000 {
247 compatible = " 247 compatible = "nuvoton,npcm750-pspi";
248 reg = <0x20100 248 reg = <0x201000 0x1000>;
249 pinctrl-names 249 pinctrl-names = "default";
250 pinctrl-0 = <& 250 pinctrl-0 = <&pspi2_pins>;
251 #address-cells 251 #address-cells = <1>;
252 #size-cells = 252 #size-cells = <0>;
253 interrupts = < 253 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk 254 clocks = <&clk NPCM7XX_CLK_APB5>;
255 clock-names = 255 clock-names = "clk_apb5";
256 resets = <&rst 256 resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
257 status = "disa 257 status = "disabled";
258 }; 258 };
259 259
260 timer0: timer@8000 { 260 timer0: timer@8000 {
261 compatible = " 261 compatible = "nuvoton,npcm750-timer";
262 interrupts = < 262 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0x8000 263 reg = <0x8000 0x1C>;
264 clocks = <&clk 264 clocks = <&clk NPCM7XX_CLK_TIMER>;
265 }; 265 };
266 266
267 watchdog0: watchdog@80 267 watchdog0: watchdog@801C {
268 compatible = " 268 compatible = "nuvoton,npcm750-wdt";
269 interrupts = < 269 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
270 reg = <0x801C 270 reg = <0x801C 0x4>;
271 status = "disa 271 status = "disabled";
272 clocks = <&clk 272 clocks = <&clk NPCM7XX_CLK_TIMER>;
273 }; 273 };
274 274
275 watchdog1: watchdog@90 275 watchdog1: watchdog@901C {
276 compatible = " 276 compatible = "nuvoton,npcm750-wdt";
277 interrupts = < 277 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
278 reg = <0x901C 278 reg = <0x901C 0x4>;
279 status = "disa 279 status = "disabled";
280 clocks = <&clk 280 clocks = <&clk NPCM7XX_CLK_TIMER>;
281 }; 281 };
282 282
283 watchdog2: watchdog@a0 283 watchdog2: watchdog@a01C {
284 compatible = " 284 compatible = "nuvoton,npcm750-wdt";
285 interrupts = < 285 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
286 reg = <0xa01C 286 reg = <0xa01C 0x4>;
287 status = "disa 287 status = "disabled";
288 clocks = <&clk 288 clocks = <&clk NPCM7XX_CLK_TIMER>;
289 }; 289 };
290 290
291 serial0: serial@1000 { 291 serial0: serial@1000 {
292 compatible = " 292 compatible = "nuvoton,npcm750-uart";
293 reg = <0x1000 293 reg = <0x1000 0x1000>;
294 clocks = <&clk 294 clocks = <&clk NPCM7XX_CLK_UART>;
295 interrupts = < 295 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
296 reg-shift = <2 296 reg-shift = <2>;
297 status = "disa 297 status = "disabled";
298 }; 298 };
299 299
300 serial1: serial@2000 { 300 serial1: serial@2000 {
301 compatible = " 301 compatible = "nuvoton,npcm750-uart";
302 reg = <0x2000 302 reg = <0x2000 0x1000>;
303 clocks = <&clk 303 clocks = <&clk NPCM7XX_CLK_UART>;
304 interrupts = < 304 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
305 reg-shift = <2 305 reg-shift = <2>;
306 status = "disa 306 status = "disabled";
307 }; 307 };
308 308
309 serial2: serial@3000 { 309 serial2: serial@3000 {
310 compatible = " 310 compatible = "nuvoton,npcm750-uart";
311 reg = <0x3000 311 reg = <0x3000 0x1000>;
312 clocks = <&clk 312 clocks = <&clk NPCM7XX_CLK_UART>;
313 interrupts = < 313 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
314 reg-shift = <2 314 reg-shift = <2>;
315 status = "disa 315 status = "disabled";
316 }; 316 };
317 317
318 serial3: serial@4000 { 318 serial3: serial@4000 {
319 compatible = " 319 compatible = "nuvoton,npcm750-uart";
320 reg = <0x4000 320 reg = <0x4000 0x1000>;
321 clocks = <&clk 321 clocks = <&clk NPCM7XX_CLK_UART>;
322 interrupts = < 322 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
323 reg-shift = <2 323 reg-shift = <2>;
324 status = "disa 324 status = "disabled";
325 }; 325 };
326 326
327 rng: rng@b000 { 327 rng: rng@b000 {
328 compatible = " 328 compatible = "nuvoton,npcm750-rng";
329 reg = <0xb000 329 reg = <0xb000 0x8>;
330 status = "disa 330 status = "disabled";
331 }; 331 };
332 332
333 adc: adc@c000 { 333 adc: adc@c000 {
334 compatible = " 334 compatible = "nuvoton,npcm750-adc";
335 reg = <0xc000 335 reg = <0xc000 0x8>;
336 interrupts = < 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clk 337 clocks = <&clk NPCM7XX_CLK_ADC>;
338 resets = <&rst 338 resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
339 status = "disa 339 status = "disabled";
340 }; 340 };
341 341
342 pwm_fan: pwm-fan-contr 342 pwm_fan: pwm-fan-controller@103000 {
343 #address-cells 343 #address-cells = <1>;
344 #size-cells = 344 #size-cells = <0>;
345 compatible = " 345 compatible = "nuvoton,npcm750-pwm-fan";
346 reg = <0x10300 346 reg = <0x103000 0x2000>, <0x180000 0x8000>;
347 reg-names = "p 347 reg-names = "pwm", "fan";
348 clocks = <&clk 348 clocks = <&clk NPCM7XX_CLK_APB3>,
349 <&clk 349 <&clk NPCM7XX_CLK_APB4>;
350 clock-names = 350 clock-names = "pwm","fan";
351 interrupts = < 351 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
352 352 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
353 353 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
354 354 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
355 355 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
356 356 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
357 357 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
358 358 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names 359 pinctrl-names = "default";
360 pinctrl-0 = <& 360 pinctrl-0 = <&pwm0_pins &pwm1_pins
361 361 &pwm2_pins &pwm3_pins
362 362 &pwm4_pins &pwm5_pins
363 363 &pwm6_pins &pwm7_pins
364 364 &fanin0_pins &fanin1_pins
365 365 &fanin2_pins &fanin3_pins
366 366 &fanin4_pins &fanin5_pins
367 367 &fanin6_pins &fanin7_pins
368 368 &fanin8_pins &fanin9_pins
369 369 &fanin10_pins &fanin11_pins
370 370 &fanin12_pins &fanin13_pins
371 371 &fanin14_pins &fanin15_pins>;
372 status = "disa 372 status = "disabled";
373 }; 373 };
374 374
375 i2c0: i2c@80000 { 375 i2c0: i2c@80000 {
376 reg = <0x80000 376 reg = <0x80000 0x1000>;
377 compatible = " 377 compatible = "nuvoton,npcm750-i2c";
378 #address-cells 378 #address-cells = <1>;
379 #size-cells = 379 #size-cells = <0>;
380 clocks = <&clk 380 clocks = <&clk NPCM7XX_CLK_APB2>;
381 interrupts = < 381 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
382 pinctrl-names 382 pinctrl-names = "default";
383 pinctrl-0 = <& 383 pinctrl-0 = <&smb0_pins>;
384 status = "disa 384 status = "disabled";
385 }; 385 };
386 386
387 i2c1: i2c@81000 { 387 i2c1: i2c@81000 {
388 reg = <0x81000 388 reg = <0x81000 0x1000>;
389 compatible = " 389 compatible = "nuvoton,npcm750-i2c";
390 #address-cells 390 #address-cells = <1>;
391 #size-cells = 391 #size-cells = <0>;
392 clocks = <&clk 392 clocks = <&clk NPCM7XX_CLK_APB2>;
393 interrupts = < 393 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
394 pinctrl-names 394 pinctrl-names = "default";
395 pinctrl-0 = <& 395 pinctrl-0 = <&smb1_pins>;
396 status = "disa 396 status = "disabled";
397 }; 397 };
398 398
399 i2c2: i2c@82000 { 399 i2c2: i2c@82000 {
400 reg = <0x82000 400 reg = <0x82000 0x1000>;
401 compatible = " 401 compatible = "nuvoton,npcm750-i2c";
402 #address-cells 402 #address-cells = <1>;
403 #size-cells = 403 #size-cells = <0>;
404 clocks = <&clk 404 clocks = <&clk NPCM7XX_CLK_APB2>;
405 interrupts = < 405 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names 406 pinctrl-names = "default";
407 pinctrl-0 = <& 407 pinctrl-0 = <&smb2_pins>;
408 status = "disa 408 status = "disabled";
409 }; 409 };
410 410
411 i2c3: i2c@83000 { 411 i2c3: i2c@83000 {
412 reg = <0x83000 412 reg = <0x83000 0x1000>;
413 compatible = " 413 compatible = "nuvoton,npcm750-i2c";
414 #address-cells 414 #address-cells = <1>;
415 #size-cells = 415 #size-cells = <0>;
416 clocks = <&clk 416 clocks = <&clk NPCM7XX_CLK_APB2>;
417 interrupts = < 417 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
418 pinctrl-names 418 pinctrl-names = "default";
419 pinctrl-0 = <& 419 pinctrl-0 = <&smb3_pins>;
420 status = "disa 420 status = "disabled";
421 }; 421 };
422 422
423 i2c4: i2c@84000 { 423 i2c4: i2c@84000 {
424 reg = <0x84000 424 reg = <0x84000 0x1000>;
425 compatible = " 425 compatible = "nuvoton,npcm750-i2c";
426 #address-cells 426 #address-cells = <1>;
427 #size-cells = 427 #size-cells = <0>;
428 clocks = <&clk 428 clocks = <&clk NPCM7XX_CLK_APB2>;
429 interrupts = < 429 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
430 pinctrl-names 430 pinctrl-names = "default";
431 pinctrl-0 = <& 431 pinctrl-0 = <&smb4_pins>;
432 status = "disa 432 status = "disabled";
433 }; 433 };
434 434
435 i2c5: i2c@85000 { 435 i2c5: i2c@85000 {
436 reg = <0x85000 436 reg = <0x85000 0x1000>;
437 compatible = " 437 compatible = "nuvoton,npcm750-i2c";
438 #address-cells 438 #address-cells = <1>;
439 #size-cells = 439 #size-cells = <0>;
440 clocks = <&clk 440 clocks = <&clk NPCM7XX_CLK_APB2>;
441 interrupts = < 441 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
442 pinctrl-names 442 pinctrl-names = "default";
443 pinctrl-0 = <& 443 pinctrl-0 = <&smb5_pins>;
444 status = "disa 444 status = "disabled";
445 }; 445 };
446 446
447 i2c6: i2c@86000 { 447 i2c6: i2c@86000 {
448 reg = <0x86000 448 reg = <0x86000 0x1000>;
449 compatible = " 449 compatible = "nuvoton,npcm750-i2c";
450 #address-cells 450 #address-cells = <1>;
451 #size-cells = 451 #size-cells = <0>;
452 clocks = <&clk 452 clocks = <&clk NPCM7XX_CLK_APB2>;
453 interrupts = < 453 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
454 pinctrl-names 454 pinctrl-names = "default";
455 pinctrl-0 = <& 455 pinctrl-0 = <&smb6_pins>;
456 status = "disa 456 status = "disabled";
457 }; 457 };
458 458
459 i2c7: i2c@87000 { 459 i2c7: i2c@87000 {
460 reg = <0x87000 460 reg = <0x87000 0x1000>;
461 compatible = " 461 compatible = "nuvoton,npcm750-i2c";
462 #address-cells 462 #address-cells = <1>;
463 #size-cells = 463 #size-cells = <0>;
464 clocks = <&clk 464 clocks = <&clk NPCM7XX_CLK_APB2>;
465 interrupts = < 465 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
466 pinctrl-names 466 pinctrl-names = "default";
467 pinctrl-0 = <& 467 pinctrl-0 = <&smb7_pins>;
468 status = "disa 468 status = "disabled";
469 }; 469 };
470 470
471 i2c8: i2c@88000 { 471 i2c8: i2c@88000 {
472 reg = <0x88000 472 reg = <0x88000 0x1000>;
473 compatible = " 473 compatible = "nuvoton,npcm750-i2c";
474 #address-cells 474 #address-cells = <1>;
475 #size-cells = 475 #size-cells = <0>;
476 clocks = <&clk 476 clocks = <&clk NPCM7XX_CLK_APB2>;
477 interrupts = < 477 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names 478 pinctrl-names = "default";
479 pinctrl-0 = <& 479 pinctrl-0 = <&smb8_pins>;
480 status = "disa 480 status = "disabled";
481 }; 481 };
482 482
483 i2c9: i2c@89000 { 483 i2c9: i2c@89000 {
484 reg = <0x89000 484 reg = <0x89000 0x1000>;
485 compatible = " 485 compatible = "nuvoton,npcm750-i2c";
486 #address-cells 486 #address-cells = <1>;
487 #size-cells = 487 #size-cells = <0>;
488 clocks = <&clk 488 clocks = <&clk NPCM7XX_CLK_APB2>;
489 interrupts = < 489 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-names 490 pinctrl-names = "default";
491 pinctrl-0 = <& 491 pinctrl-0 = <&smb9_pins>;
492 status = "disa 492 status = "disabled";
493 }; 493 };
494 494
495 i2c10: i2c@8a000 { 495 i2c10: i2c@8a000 {
496 reg = <0x8a000 496 reg = <0x8a000 0x1000>;
497 compatible = " 497 compatible = "nuvoton,npcm750-i2c";
498 #address-cells 498 #address-cells = <1>;
499 #size-cells = 499 #size-cells = <0>;
500 clocks = <&clk 500 clocks = <&clk NPCM7XX_CLK_APB2>;
501 interrupts = < 501 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
502 pinctrl-names 502 pinctrl-names = "default";
503 pinctrl-0 = <& 503 pinctrl-0 = <&smb10_pins>;
504 status = "disa 504 status = "disabled";
505 }; 505 };
506 506
507 i2c11: i2c@8b000 { 507 i2c11: i2c@8b000 {
508 reg = <0x8b000 508 reg = <0x8b000 0x1000>;
509 compatible = " 509 compatible = "nuvoton,npcm750-i2c";
510 #address-cells 510 #address-cells = <1>;
511 #size-cells = 511 #size-cells = <0>;
512 clocks = <&clk 512 clocks = <&clk NPCM7XX_CLK_APB2>;
513 interrupts = < 513 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
514 pinctrl-names 514 pinctrl-names = "default";
515 pinctrl-0 = <& 515 pinctrl-0 = <&smb11_pins>;
516 status = "disa 516 status = "disabled";
517 }; 517 };
518 518
519 i2c12: i2c@8c000 { 519 i2c12: i2c@8c000 {
520 reg = <0x8c000 520 reg = <0x8c000 0x1000>;
521 compatible = " 521 compatible = "nuvoton,npcm750-i2c";
522 #address-cells 522 #address-cells = <1>;
523 #size-cells = 523 #size-cells = <0>;
524 clocks = <&clk 524 clocks = <&clk NPCM7XX_CLK_APB2>;
525 interrupts = < 525 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
526 pinctrl-names 526 pinctrl-names = "default";
527 pinctrl-0 = <& 527 pinctrl-0 = <&smb12_pins>;
528 status = "disa 528 status = "disabled";
529 }; 529 };
530 530
531 i2c13: i2c@8d000 { 531 i2c13: i2c@8d000 {
532 reg = <0x8d000 532 reg = <0x8d000 0x1000>;
533 compatible = " 533 compatible = "nuvoton,npcm750-i2c";
534 #address-cells 534 #address-cells = <1>;
535 #size-cells = 535 #size-cells = <0>;
536 clocks = <&clk 536 clocks = <&clk NPCM7XX_CLK_APB2>;
537 interrupts = < 537 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names 538 pinctrl-names = "default";
539 pinctrl-0 = <& 539 pinctrl-0 = <&smb13_pins>;
540 status = "disa 540 status = "disabled";
541 }; 541 };
542 542
543 i2c14: i2c@8e000 { 543 i2c14: i2c@8e000 {
544 reg = <0x8e000 544 reg = <0x8e000 0x1000>;
545 compatible = " 545 compatible = "nuvoton,npcm750-i2c";
546 #address-cells 546 #address-cells = <1>;
547 #size-cells = 547 #size-cells = <0>;
548 clocks = <&clk 548 clocks = <&clk NPCM7XX_CLK_APB2>;
549 interrupts = < 549 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names 550 pinctrl-names = "default";
551 pinctrl-0 = <& 551 pinctrl-0 = <&smb14_pins>;
552 status = "disa 552 status = "disabled";
553 }; 553 };
554 554
555 i2c15: i2c@8f000 { 555 i2c15: i2c@8f000 {
556 reg = <0x8f000 556 reg = <0x8f000 0x1000>;
557 compatible = " 557 compatible = "nuvoton,npcm750-i2c";
558 #address-cells 558 #address-cells = <1>;
559 #size-cells = 559 #size-cells = <0>;
560 clocks = <&clk 560 clocks = <&clk NPCM7XX_CLK_APB2>;
561 interrupts = < 561 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
562 pinctrl-names 562 pinctrl-names = "default";
563 pinctrl-0 = <& 563 pinctrl-0 = <&smb15_pins>;
564 status = "disa 564 status = "disabled";
565 }; 565 };
566 }; 566 };
567 }; 567 };
568 568
569 pinctrl: pinctrl@f0800000 { 569 pinctrl: pinctrl@f0800000 {
570 #address-cells = <1>; 570 #address-cells = <1>;
571 #size-cells = <1>; 571 #size-cells = <1>;
572 compatible = "nuvoton,npcm750- 572 compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
573 ranges = <0 0xf0010000 0x8000> 573 ranges = <0 0xf0010000 0x8000>;
574 gpio0: gpio@f0010000 { 574 gpio0: gpio@f0010000 {
575 gpio-controller; 575 gpio-controller;
576 #gpio-cells = <2>; 576 #gpio-cells = <2>;
577 reg = <0x0 0x80>; 577 reg = <0x0 0x80>;
578 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
579 gpio-ranges = <&pinctr 579 gpio-ranges = <&pinctrl 0 0 32>;
580 }; 580 };
581 gpio1: gpio@f0011000 { 581 gpio1: gpio@f0011000 {
582 gpio-controller; 582 gpio-controller;
583 #gpio-cells = <2>; 583 #gpio-cells = <2>;
584 reg = <0x1000 0x80>; 584 reg = <0x1000 0x80>;
585 interrupts = <GIC_SPI 585 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
586 gpio-ranges = <&pinctr 586 gpio-ranges = <&pinctrl 0 32 32>;
587 }; 587 };
588 gpio2: gpio@f0012000 { 588 gpio2: gpio@f0012000 {
589 gpio-controller; 589 gpio-controller;
590 #gpio-cells = <2>; 590 #gpio-cells = <2>;
591 reg = <0x2000 0x80>; 591 reg = <0x2000 0x80>;
592 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
593 gpio-ranges = <&pinctr 593 gpio-ranges = <&pinctrl 0 64 32>;
594 }; 594 };
595 gpio3: gpio@f0013000 { 595 gpio3: gpio@f0013000 {
596 gpio-controller; 596 gpio-controller;
597 #gpio-cells = <2>; 597 #gpio-cells = <2>;
598 reg = <0x3000 0x80>; 598 reg = <0x3000 0x80>;
599 interrupts = <GIC_SPI 599 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
600 gpio-ranges = <&pinctr 600 gpio-ranges = <&pinctrl 0 96 32>;
601 }; 601 };
602 gpio4: gpio@f0014000 { 602 gpio4: gpio@f0014000 {
603 gpio-controller; 603 gpio-controller;
604 #gpio-cells = <2>; 604 #gpio-cells = <2>;
605 reg = <0x4000 0x80>; 605 reg = <0x4000 0x80>;
606 interrupts = <GIC_SPI 606 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
607 gpio-ranges = <&pinctr 607 gpio-ranges = <&pinctrl 0 128 32>;
608 }; 608 };
609 gpio5: gpio@f0015000 { 609 gpio5: gpio@f0015000 {
610 gpio-controller; 610 gpio-controller;
611 #gpio-cells = <2>; 611 #gpio-cells = <2>;
612 reg = <0x5000 0x80>; 612 reg = <0x5000 0x80>;
613 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
614 gpio-ranges = <&pinctr 614 gpio-ranges = <&pinctrl 0 160 32>;
615 }; 615 };
616 gpio6: gpio@f0016000 { 616 gpio6: gpio@f0016000 {
617 gpio-controller; 617 gpio-controller;
618 #gpio-cells = <2>; 618 #gpio-cells = <2>;
619 reg = <0x6000 0x80>; 619 reg = <0x6000 0x80>;
620 interrupts = <GIC_SPI 620 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
621 gpio-ranges = <&pinctr 621 gpio-ranges = <&pinctrl 0 192 32>;
622 }; 622 };
623 gpio7: gpio@f0017000 { 623 gpio7: gpio@f0017000 {
624 gpio-controller; 624 gpio-controller;
625 #gpio-cells = <2>; 625 #gpio-cells = <2>;
626 reg = <0x7000 0x80>; 626 reg = <0x7000 0x80>;
627 interrupts = <GIC_SPI 627 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
628 gpio-ranges = <&pinctr 628 gpio-ranges = <&pinctrl 0 224 32>;
629 }; 629 };
630 630
631 iox1_pins: iox1-pins { 631 iox1_pins: iox1-pins {
632 groups = "iox1"; 632 groups = "iox1";
633 function = "iox1"; 633 function = "iox1";
634 }; 634 };
635 iox2_pins: iox2-pins { 635 iox2_pins: iox2-pins {
636 groups = "iox2"; 636 groups = "iox2";
637 function = "iox2"; 637 function = "iox2";
638 }; 638 };
639 smb1d_pins: smb1d-pins { 639 smb1d_pins: smb1d-pins {
640 groups = "smb1d"; 640 groups = "smb1d";
641 function = "smb1d"; 641 function = "smb1d";
642 }; 642 };
643 smb2d_pins: smb2d-pins { 643 smb2d_pins: smb2d-pins {
644 groups = "smb2d"; 644 groups = "smb2d";
645 function = "smb2d"; 645 function = "smb2d";
646 }; 646 };
647 lkgpo1_pins: lkgpo1-pins { 647 lkgpo1_pins: lkgpo1-pins {
648 groups = "lkgpo1"; 648 groups = "lkgpo1";
649 function = "lkgpo1"; 649 function = "lkgpo1";
650 }; 650 };
651 lkgpo2_pins: lkgpo2-pins { 651 lkgpo2_pins: lkgpo2-pins {
652 groups = "lkgpo2"; 652 groups = "lkgpo2";
653 function = "lkgpo2"; 653 function = "lkgpo2";
654 }; 654 };
655 ioxh_pins: ioxh-pins { 655 ioxh_pins: ioxh-pins {
656 groups = "ioxh"; 656 groups = "ioxh";
657 function = "ioxh"; 657 function = "ioxh";
658 }; 658 };
659 gspi_pins: gspi-pins { 659 gspi_pins: gspi-pins {
660 groups = "gspi"; 660 groups = "gspi";
661 function = "gspi"; 661 function = "gspi";
662 }; 662 };
663 smb5b_pins: smb5b-pins { 663 smb5b_pins: smb5b-pins {
664 groups = "smb5b"; 664 groups = "smb5b";
665 function = "smb5b"; 665 function = "smb5b";
666 }; 666 };
667 smb5c_pins: smb5c-pins { 667 smb5c_pins: smb5c-pins {
668 groups = "smb5c"; 668 groups = "smb5c";
669 function = "smb5c"; 669 function = "smb5c";
670 }; 670 };
671 lkgpo0_pins: lkgpo0-pins { 671 lkgpo0_pins: lkgpo0-pins {
672 groups = "lkgpo0"; 672 groups = "lkgpo0";
673 function = "lkgpo0"; 673 function = "lkgpo0";
674 }; 674 };
675 pspi2_pins: pspi2-pins { 675 pspi2_pins: pspi2-pins {
676 groups = "pspi2"; 676 groups = "pspi2";
677 function = "pspi2"; 677 function = "pspi2";
678 }; 678 };
679 smb4den_pins: smb4den-pins { 679 smb4den_pins: smb4den-pins {
680 groups = "smb4den"; 680 groups = "smb4den";
681 function = "smb4den"; 681 function = "smb4den";
682 }; 682 };
683 smb4b_pins: smb4b-pins { 683 smb4b_pins: smb4b-pins {
684 groups = "smb4b"; 684 groups = "smb4b";
685 function = "smb4b"; 685 function = "smb4b";
686 }; 686 };
687 smb4c_pins: smb4c-pins { 687 smb4c_pins: smb4c-pins {
688 groups = "smb4c"; 688 groups = "smb4c";
689 function = "smb4c"; 689 function = "smb4c";
690 }; 690 };
691 smb15_pins: smb15-pins { 691 smb15_pins: smb15-pins {
692 groups = "smb15"; 692 groups = "smb15";
693 function = "smb15"; 693 function = "smb15";
694 }; 694 };
695 smb4d_pins: smb4d-pins { 695 smb4d_pins: smb4d-pins {
696 groups = "smb4d"; 696 groups = "smb4d";
697 function = "smb4d"; 697 function = "smb4d";
698 }; 698 };
699 smb14_pins: smb14-pins { 699 smb14_pins: smb14-pins {
700 groups = "smb14"; 700 groups = "smb14";
701 function = "smb14"; 701 function = "smb14";
702 }; 702 };
703 smb5_pins: smb5-pins { 703 smb5_pins: smb5-pins {
704 groups = "smb5"; 704 groups = "smb5";
705 function = "smb5"; 705 function = "smb5";
706 }; 706 };
707 smb4_pins: smb4-pins { 707 smb4_pins: smb4-pins {
708 groups = "smb4"; 708 groups = "smb4";
709 function = "smb4"; 709 function = "smb4";
710 }; 710 };
711 smb3_pins: smb3-pins { 711 smb3_pins: smb3-pins {
712 groups = "smb3"; 712 groups = "smb3";
713 function = "smb3"; 713 function = "smb3";
714 }; 714 };
715 spi0cs1_pins: spi0cs1-pins { 715 spi0cs1_pins: spi0cs1-pins {
716 groups = "spi0cs1"; 716 groups = "spi0cs1";
717 function = "spi0cs1"; 717 function = "spi0cs1";
718 }; 718 };
719 spi0cs2_pins: spi0cs2-pins { 719 spi0cs2_pins: spi0cs2-pins {
720 groups = "spi0cs2"; 720 groups = "spi0cs2";
721 function = "spi0cs2"; 721 function = "spi0cs2";
722 }; 722 };
723 spi0cs3_pins: spi0cs3-pins { 723 spi0cs3_pins: spi0cs3-pins {
724 groups = "spi0cs3"; 724 groups = "spi0cs3";
725 function = "spi0cs3"; 725 function = "spi0cs3";
726 }; 726 };
727 smb3c_pins: smb3c-pins { 727 smb3c_pins: smb3c-pins {
728 groups = "smb3c"; 728 groups = "smb3c";
729 function = "smb3c"; 729 function = "smb3c";
730 }; 730 };
731 smb3b_pins: smb3b-pins { 731 smb3b_pins: smb3b-pins {
732 groups = "smb3b"; 732 groups = "smb3b";
733 function = "smb3b"; 733 function = "smb3b";
734 }; 734 };
735 bmcuart0a_pins: bmcuart0a-pins 735 bmcuart0a_pins: bmcuart0a-pins {
736 groups = "bmcuart0a"; 736 groups = "bmcuart0a";
737 function = "bmcuart0a" 737 function = "bmcuart0a";
738 }; 738 };
739 uart1_pins: uart1-pins { 739 uart1_pins: uart1-pins {
740 groups = "uart1"; 740 groups = "uart1";
741 function = "uart1"; 741 function = "uart1";
742 }; 742 };
743 jtag2_pins: jtag2-pins { 743 jtag2_pins: jtag2-pins {
744 groups = "jtag2"; 744 groups = "jtag2";
745 function = "jtag2"; 745 function = "jtag2";
746 }; 746 };
747 bmcuart1_pins: bmcuart1-pins { 747 bmcuart1_pins: bmcuart1-pins {
748 groups = "bmcuart1"; 748 groups = "bmcuart1";
749 function = "bmcuart1"; 749 function = "bmcuart1";
750 }; 750 };
751 uart2_pins: uart2-pins { 751 uart2_pins: uart2-pins {
752 groups = "uart2"; 752 groups = "uart2";
753 function = "uart2"; 753 function = "uart2";
754 }; 754 };
755 bmcuart0b_pins: bmcuart0b-pins 755 bmcuart0b_pins: bmcuart0b-pins {
756 groups = "bmcuart0b"; 756 groups = "bmcuart0b";
757 function = "bmcuart0b" 757 function = "bmcuart0b";
758 }; 758 };
759 r1err_pins: r1err-pins { 759 r1err_pins: r1err-pins {
760 groups = "r1err"; 760 groups = "r1err";
761 function = "r1err"; 761 function = "r1err";
762 }; 762 };
763 r1md_pins: r1md-pins { 763 r1md_pins: r1md-pins {
764 groups = "r1md"; 764 groups = "r1md";
765 function = "r1md"; 765 function = "r1md";
766 }; 766 };
767 smb3d_pins: smb3d-pins { 767 smb3d_pins: smb3d-pins {
768 groups = "smb3d"; 768 groups = "smb3d";
769 function = "smb3d"; 769 function = "smb3d";
770 }; 770 };
771 fanin0_pins: fanin0-pins { 771 fanin0_pins: fanin0-pins {
772 groups = "fanin0"; 772 groups = "fanin0";
773 function = "fanin0"; 773 function = "fanin0";
774 }; 774 };
775 fanin1_pins: fanin1-pins { 775 fanin1_pins: fanin1-pins {
776 groups = "fanin1"; 776 groups = "fanin1";
777 function = "fanin1"; 777 function = "fanin1";
778 }; 778 };
779 fanin2_pins: fanin2-pins { 779 fanin2_pins: fanin2-pins {
780 groups = "fanin2"; 780 groups = "fanin2";
781 function = "fanin2"; 781 function = "fanin2";
782 }; 782 };
783 fanin3_pins: fanin3-pins { 783 fanin3_pins: fanin3-pins {
784 groups = "fanin3"; 784 groups = "fanin3";
785 function = "fanin3"; 785 function = "fanin3";
786 }; 786 };
787 fanin4_pins: fanin4-pins { 787 fanin4_pins: fanin4-pins {
788 groups = "fanin4"; 788 groups = "fanin4";
789 function = "fanin4"; 789 function = "fanin4";
790 }; 790 };
791 fanin5_pins: fanin5-pins { 791 fanin5_pins: fanin5-pins {
792 groups = "fanin5"; 792 groups = "fanin5";
793 function = "fanin5"; 793 function = "fanin5";
794 }; 794 };
795 fanin6_pins: fanin6-pins { 795 fanin6_pins: fanin6-pins {
796 groups = "fanin6"; 796 groups = "fanin6";
797 function = "fanin6"; 797 function = "fanin6";
798 }; 798 };
799 fanin7_pins: fanin7-pins { 799 fanin7_pins: fanin7-pins {
800 groups = "fanin7"; 800 groups = "fanin7";
801 function = "fanin7"; 801 function = "fanin7";
802 }; 802 };
803 fanin8_pins: fanin8-pins { 803 fanin8_pins: fanin8-pins {
804 groups = "fanin8"; 804 groups = "fanin8";
805 function = "fanin8"; 805 function = "fanin8";
806 }; 806 };
807 fanin9_pins: fanin9-pins { 807 fanin9_pins: fanin9-pins {
808 groups = "fanin9"; 808 groups = "fanin9";
809 function = "fanin9"; 809 function = "fanin9";
810 }; 810 };
811 fanin10_pins: fanin10-pins { 811 fanin10_pins: fanin10-pins {
812 groups = "fanin10"; 812 groups = "fanin10";
813 function = "fanin10"; 813 function = "fanin10";
814 }; 814 };
815 fanin11_pins: fanin11-pins { 815 fanin11_pins: fanin11-pins {
816 groups = "fanin11"; 816 groups = "fanin11";
817 function = "fanin11"; 817 function = "fanin11";
818 }; 818 };
819 fanin12_pins: fanin12-pins { 819 fanin12_pins: fanin12-pins {
820 groups = "fanin12"; 820 groups = "fanin12";
821 function = "fanin12"; 821 function = "fanin12";
822 }; 822 };
823 fanin13_pins: fanin13-pins { 823 fanin13_pins: fanin13-pins {
824 groups = "fanin13"; 824 groups = "fanin13";
825 function = "fanin13"; 825 function = "fanin13";
826 }; 826 };
827 fanin14_pins: fanin14-pins { 827 fanin14_pins: fanin14-pins {
828 groups = "fanin14"; 828 groups = "fanin14";
829 function = "fanin14"; 829 function = "fanin14";
830 }; 830 };
831 fanin15_pins: fanin15-pins { 831 fanin15_pins: fanin15-pins {
832 groups = "fanin15"; 832 groups = "fanin15";
833 function = "fanin15"; 833 function = "fanin15";
834 }; 834 };
835 pwm0_pins: pwm0-pins { 835 pwm0_pins: pwm0-pins {
836 groups = "pwm0"; 836 groups = "pwm0";
837 function = "pwm0"; 837 function = "pwm0";
838 }; 838 };
839 pwm1_pins: pwm1-pins { 839 pwm1_pins: pwm1-pins {
840 groups = "pwm1"; 840 groups = "pwm1";
841 function = "pwm1"; 841 function = "pwm1";
842 }; 842 };
843 pwm2_pins: pwm2-pins { 843 pwm2_pins: pwm2-pins {
844 groups = "pwm2"; 844 groups = "pwm2";
845 function = "pwm2"; 845 function = "pwm2";
846 }; 846 };
847 pwm3_pins: pwm3-pins { 847 pwm3_pins: pwm3-pins {
848 groups = "pwm3"; 848 groups = "pwm3";
849 function = "pwm3"; 849 function = "pwm3";
850 }; 850 };
851 r2_pins: r2-pins { 851 r2_pins: r2-pins {
852 groups = "r2"; 852 groups = "r2";
853 function = "r2"; 853 function = "r2";
854 }; 854 };
855 r2err_pins: r2err-pins { 855 r2err_pins: r2err-pins {
856 groups = "r2err"; 856 groups = "r2err";
857 function = "r2err"; 857 function = "r2err";
858 }; 858 };
859 r2md_pins: r2md-pins { 859 r2md_pins: r2md-pins {
860 groups = "r2md"; 860 groups = "r2md";
861 function = "r2md"; 861 function = "r2md";
862 }; 862 };
863 ga20kbc_pins: ga20kbc-pins { 863 ga20kbc_pins: ga20kbc-pins {
864 groups = "ga20kbc"; 864 groups = "ga20kbc";
865 function = "ga20kbc"; 865 function = "ga20kbc";
866 }; 866 };
867 smb5d_pins: smb5d-pins { 867 smb5d_pins: smb5d-pins {
868 groups = "smb5d"; 868 groups = "smb5d";
869 function = "smb5d"; 869 function = "smb5d";
870 }; 870 };
871 lpc_pins: lpc-pins { 871 lpc_pins: lpc-pins {
872 groups = "lpc"; 872 groups = "lpc";
873 function = "lpc"; 873 function = "lpc";
874 }; 874 };
875 espi_pins: espi-pins { 875 espi_pins: espi-pins {
876 groups = "espi"; 876 groups = "espi";
877 function = "espi"; 877 function = "espi";
878 }; 878 };
879 rg1_pins: rg1-pins { 879 rg1_pins: rg1-pins {
880 groups = "rg1"; 880 groups = "rg1";
881 function = "rg1"; 881 function = "rg1";
882 }; 882 };
883 rg1mdio_pins: rg1mdio-pins { 883 rg1mdio_pins: rg1mdio-pins {
884 groups = "rg1mdio"; 884 groups = "rg1mdio";
885 function = "rg1mdio"; 885 function = "rg1mdio";
886 }; 886 };
887 rg2_pins: rg2-pins { 887 rg2_pins: rg2-pins {
888 groups = "rg2"; 888 groups = "rg2";
889 function = "rg2"; 889 function = "rg2";
890 }; 890 };
891 ddr_pins: ddr-pins { 891 ddr_pins: ddr-pins {
892 groups = "ddr"; 892 groups = "ddr";
893 function = "ddr"; 893 function = "ddr";
894 }; 894 };
895 smb0_pins: smb0-pins { 895 smb0_pins: smb0-pins {
896 groups = "smb0"; 896 groups = "smb0";
897 function = "smb0"; 897 function = "smb0";
898 }; 898 };
899 smb1_pins: smb1-pins { 899 smb1_pins: smb1-pins {
900 groups = "smb1"; 900 groups = "smb1";
901 function = "smb1"; 901 function = "smb1";
902 }; 902 };
903 smb2_pins: smb2-pins { 903 smb2_pins: smb2-pins {
904 groups = "smb2"; 904 groups = "smb2";
905 function = "smb2"; 905 function = "smb2";
906 }; 906 };
907 smb2c_pins: smb2c-pins { 907 smb2c_pins: smb2c-pins {
908 groups = "smb2c"; 908 groups = "smb2c";
909 function = "smb2c"; 909 function = "smb2c";
910 }; 910 };
911 smb2b_pins: smb2b-pins { 911 smb2b_pins: smb2b-pins {
912 groups = "smb2b"; 912 groups = "smb2b";
913 function = "smb2b"; 913 function = "smb2b";
914 }; 914 };
915 smb1c_pins: smb1c-pins { 915 smb1c_pins: smb1c-pins {
916 groups = "smb1c"; 916 groups = "smb1c";
917 function = "smb1c"; 917 function = "smb1c";
918 }; 918 };
919 smb1b_pins: smb1b-pins { 919 smb1b_pins: smb1b-pins {
920 groups = "smb1b"; 920 groups = "smb1b";
921 function = "smb1b"; 921 function = "smb1b";
922 }; 922 };
923 smb8_pins: smb8-pins { 923 smb8_pins: smb8-pins {
924 groups = "smb8"; 924 groups = "smb8";
925 function = "smb8"; 925 function = "smb8";
926 }; 926 };
927 smb9_pins: smb9-pins { 927 smb9_pins: smb9-pins {
928 groups = "smb9"; 928 groups = "smb9";
929 function = "smb9"; 929 function = "smb9";
930 }; 930 };
931 smb10_pins: smb10-pins { 931 smb10_pins: smb10-pins {
932 groups = "smb10"; 932 groups = "smb10";
933 function = "smb10"; 933 function = "smb10";
934 }; 934 };
935 smb11_pins: smb11-pins { 935 smb11_pins: smb11-pins {
936 groups = "smb11"; 936 groups = "smb11";
937 function = "smb11"; 937 function = "smb11";
938 }; 938 };
939 sd1_pins: sd1-pins { 939 sd1_pins: sd1-pins {
940 groups = "sd1"; 940 groups = "sd1";
941 function = "sd1"; 941 function = "sd1";
942 }; 942 };
943 sd1pwr_pins: sd1pwr-pins { 943 sd1pwr_pins: sd1pwr-pins {
944 groups = "sd1pwr"; 944 groups = "sd1pwr";
945 function = "sd1pwr"; 945 function = "sd1pwr";
946 }; 946 };
947 pwm4_pins: pwm4-pins { 947 pwm4_pins: pwm4-pins {
948 groups = "pwm4"; 948 groups = "pwm4";
949 function = "pwm4"; 949 function = "pwm4";
950 }; 950 };
951 pwm5_pins: pwm5-pins { 951 pwm5_pins: pwm5-pins {
952 groups = "pwm5"; 952 groups = "pwm5";
953 function = "pwm5"; 953 function = "pwm5";
954 }; 954 };
955 pwm6_pins: pwm6-pins { 955 pwm6_pins: pwm6-pins {
956 groups = "pwm6"; 956 groups = "pwm6";
957 function = "pwm6"; 957 function = "pwm6";
958 }; 958 };
959 pwm7_pins: pwm7-pins { 959 pwm7_pins: pwm7-pins {
960 groups = "pwm7"; 960 groups = "pwm7";
961 function = "pwm7"; 961 function = "pwm7";
962 }; 962 };
963 mmc8_pins: mmc8-pins { 963 mmc8_pins: mmc8-pins {
964 groups = "mmc8"; 964 groups = "mmc8";
965 function = "mmc8"; 965 function = "mmc8";
966 }; 966 };
967 mmc_pins: mmc-pins { 967 mmc_pins: mmc-pins {
968 groups = "mmc"; 968 groups = "mmc";
969 function = "mmc"; 969 function = "mmc";
970 }; 970 };
971 mmcwp_pins: mmcwp-pins { 971 mmcwp_pins: mmcwp-pins {
972 groups = "mmcwp"; 972 groups = "mmcwp";
973 function = "mmcwp"; 973 function = "mmcwp";
974 }; 974 };
975 mmccd_pins: mmccd-pins { 975 mmccd_pins: mmccd-pins {
976 groups = "mmccd"; 976 groups = "mmccd";
977 function = "mmccd"; 977 function = "mmccd";
978 }; 978 };
979 mmcrst_pins: mmcrst-pins { 979 mmcrst_pins: mmcrst-pins {
980 groups = "mmcrst"; 980 groups = "mmcrst";
981 function = "mmcrst"; 981 function = "mmcrst";
982 }; 982 };
983 clkout_pins: clkout-pins { 983 clkout_pins: clkout-pins {
984 groups = "clkout"; 984 groups = "clkout";
985 function = "clkout"; 985 function = "clkout";
986 }; 986 };
987 serirq_pins: serirq-pins { 987 serirq_pins: serirq-pins {
988 groups = "serirq"; 988 groups = "serirq";
989 function = "serirq"; 989 function = "serirq";
990 }; 990 };
991 lpcclk_pins: lpcclk-pins { 991 lpcclk_pins: lpcclk-pins {
992 groups = "lpcclk"; 992 groups = "lpcclk";
993 function = "lpcclk"; 993 function = "lpcclk";
994 }; 994 };
995 scipme_pins: scipme-pins { 995 scipme_pins: scipme-pins {
996 groups = "scipme"; 996 groups = "scipme";
997 function = "scipme"; 997 function = "scipme";
998 }; 998 };
999 sci_pins: sci-pins { 999 sci_pins: sci-pins {
1000 groups = "sci"; 1000 groups = "sci";
1001 function = "sci"; 1001 function = "sci";
1002 }; 1002 };
1003 smb6_pins: smb6-pins { 1003 smb6_pins: smb6-pins {
1004 groups = "smb6"; 1004 groups = "smb6";
1005 function = "smb6"; 1005 function = "smb6";
1006 }; 1006 };
1007 smb7_pins: smb7-pins { 1007 smb7_pins: smb7-pins {
1008 groups = "smb7"; 1008 groups = "smb7";
1009 function = "smb7"; 1009 function = "smb7";
1010 }; 1010 };
1011 pspi1_pins: pspi1-pins { 1011 pspi1_pins: pspi1-pins {
1012 groups = "pspi1"; 1012 groups = "pspi1";
1013 function = "pspi1"; 1013 function = "pspi1";
1014 }; 1014 };
1015 faninx_pins: faninx-pins { 1015 faninx_pins: faninx-pins {
1016 groups = "faninx"; 1016 groups = "faninx";
1017 function = "faninx"; 1017 function = "faninx";
1018 }; 1018 };
1019 r1_pins: r1-pins { 1019 r1_pins: r1-pins {
1020 groups = "r1"; 1020 groups = "r1";
1021 function = "r1"; 1021 function = "r1";
1022 }; 1022 };
1023 spi3_pins: spi3-pins { 1023 spi3_pins: spi3-pins {
1024 groups = "spi3"; 1024 groups = "spi3";
1025 function = "spi3"; 1025 function = "spi3";
1026 }; 1026 };
1027 spi3cs1_pins: spi3cs1-pins { 1027 spi3cs1_pins: spi3cs1-pins {
1028 groups = "spi3cs1"; 1028 groups = "spi3cs1";
1029 function = "spi3cs1"; 1029 function = "spi3cs1";
1030 }; 1030 };
1031 spi3quad_pins: spi3quad-pins 1031 spi3quad_pins: spi3quad-pins {
1032 groups = "spi3quad"; 1032 groups = "spi3quad";
1033 function = "spi3quad" 1033 function = "spi3quad";
1034 }; 1034 };
1035 spi3cs2_pins: spi3cs2-pins { 1035 spi3cs2_pins: spi3cs2-pins {
1036 groups = "spi3cs2"; 1036 groups = "spi3cs2";
1037 function = "spi3cs2"; 1037 function = "spi3cs2";
1038 }; 1038 };
1039 spi3cs3_pins: spi3cs3-pins { 1039 spi3cs3_pins: spi3cs3-pins {
1040 groups = "spi3cs3"; 1040 groups = "spi3cs3";
1041 function = "spi3cs3"; 1041 function = "spi3cs3";
1042 }; 1042 };
1043 nprd_smi_pins: nprd-smi-pins 1043 nprd_smi_pins: nprd-smi-pins {
1044 groups = "nprd_smi"; 1044 groups = "nprd_smi";
1045 function = "nprd_smi" 1045 function = "nprd_smi";
1046 }; 1046 };
1047 smb0b_pins: smb0b-pins { 1047 smb0b_pins: smb0b-pins {
1048 groups = "smb0b"; 1048 groups = "smb0b";
1049 function = "smb0b"; 1049 function = "smb0b";
1050 }; 1050 };
1051 smb0c_pins: smb0c-pins { 1051 smb0c_pins: smb0c-pins {
1052 groups = "smb0c"; 1052 groups = "smb0c";
1053 function = "smb0c"; 1053 function = "smb0c";
1054 }; 1054 };
1055 smb0den_pins: smb0den-pins { 1055 smb0den_pins: smb0den-pins {
1056 groups = "smb0den"; 1056 groups = "smb0den";
1057 function = "smb0den"; 1057 function = "smb0den";
1058 }; 1058 };
1059 smb0d_pins: smb0d-pins { 1059 smb0d_pins: smb0d-pins {
1060 groups = "smb0d"; 1060 groups = "smb0d";
1061 function = "smb0d"; 1061 function = "smb0d";
1062 }; 1062 };
1063 ddc_pins: ddc-pins { 1063 ddc_pins: ddc-pins {
1064 groups = "ddc"; 1064 groups = "ddc";
1065 function = "ddc"; 1065 function = "ddc";
1066 }; 1066 };
1067 rg2mdio_pins: rg2mdio-pins { 1067 rg2mdio_pins: rg2mdio-pins {
1068 groups = "rg2mdio"; 1068 groups = "rg2mdio";
1069 function = "rg2mdio"; 1069 function = "rg2mdio";
1070 }; 1070 };
1071 wdog1_pins: wdog1-pins { 1071 wdog1_pins: wdog1-pins {
1072 groups = "wdog1"; 1072 groups = "wdog1";
1073 function = "wdog1"; 1073 function = "wdog1";
1074 }; 1074 };
1075 wdog2_pins: wdog2-pins { 1075 wdog2_pins: wdog2-pins {
1076 groups = "wdog2"; 1076 groups = "wdog2";
1077 function = "wdog2"; 1077 function = "wdog2";
1078 }; 1078 };
1079 smb12_pins: smb12-pins { 1079 smb12_pins: smb12-pins {
1080 groups = "smb12"; 1080 groups = "smb12";
1081 function = "smb12"; 1081 function = "smb12";
1082 }; 1082 };
1083 smb13_pins: smb13-pins { 1083 smb13_pins: smb13-pins {
1084 groups = "smb13"; 1084 groups = "smb13";
1085 function = "smb13"; 1085 function = "smb13";
1086 }; 1086 };
1087 spix_pins: spix-pins { 1087 spix_pins: spix-pins {
1088 groups = "spix"; 1088 groups = "spix";
1089 function = "spix"; 1089 function = "spix";
1090 }; 1090 };
1091 spixcs1_pins: spixcs1-pins { 1091 spixcs1_pins: spixcs1-pins {
1092 groups = "spixcs1"; 1092 groups = "spixcs1";
1093 function = "spixcs1"; 1093 function = "spixcs1";
1094 }; 1094 };
1095 clkreq_pins: clkreq-pins { 1095 clkreq_pins: clkreq-pins {
1096 groups = "clkreq"; 1096 groups = "clkreq";
1097 function = "clkreq"; 1097 function = "clkreq";
1098 }; 1098 };
1099 hgpio0_pins: hgpio0-pins { 1099 hgpio0_pins: hgpio0-pins {
1100 groups = "hgpio0"; 1100 groups = "hgpio0";
1101 function = "hgpio0"; 1101 function = "hgpio0";
1102 }; 1102 };
1103 hgpio1_pins: hgpio1-pins { 1103 hgpio1_pins: hgpio1-pins {
1104 groups = "hgpio1"; 1104 groups = "hgpio1";
1105 function = "hgpio1"; 1105 function = "hgpio1";
1106 }; 1106 };
1107 hgpio2_pins: hgpio2-pins { 1107 hgpio2_pins: hgpio2-pins {
1108 groups = "hgpio2"; 1108 groups = "hgpio2";
1109 function = "hgpio2"; 1109 function = "hgpio2";
1110 }; 1110 };
1111 hgpio3_pins: hgpio3-pins { 1111 hgpio3_pins: hgpio3-pins {
1112 groups = "hgpio3"; 1112 groups = "hgpio3";
1113 function = "hgpio3"; 1113 function = "hgpio3";
1114 }; 1114 };
1115 hgpio4_pins: hgpio4-pins { 1115 hgpio4_pins: hgpio4-pins {
1116 groups = "hgpio4"; 1116 groups = "hgpio4";
1117 function = "hgpio4"; 1117 function = "hgpio4";
1118 }; 1118 };
1119 hgpio5_pins: hgpio5-pins { 1119 hgpio5_pins: hgpio5-pins {
1120 groups = "hgpio5"; 1120 groups = "hgpio5";
1121 function = "hgpio5"; 1121 function = "hgpio5";
1122 }; 1122 };
1123 hgpio6_pins: hgpio6-pins { 1123 hgpio6_pins: hgpio6-pins {
1124 groups = "hgpio6"; 1124 groups = "hgpio6";
1125 function = "hgpio6"; 1125 function = "hgpio6";
1126 }; 1126 };
1127 hgpio7_pins: hgpio7-pins { 1127 hgpio7_pins: hgpio7-pins {
1128 groups = "hgpio7"; 1128 groups = "hgpio7";
1129 function = "hgpio7"; 1129 function = "hgpio7";
1130 }; 1130 };
1131 }; 1131 };
1132 }; 1132 };
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