1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019 Quanta Computer lnc. Fra 2 // Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com
3 3
4 /dts-v1/; 4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi" 5 #include "nuvoton-npcm730.dtsi"
6 #include "nuvoton-npcm730-gsj-gpio.dtsi" 6 #include "nuvoton-npcm730-gsj-gpio.dtsi"
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 9
10 / { 10 / {
11 model = "Quanta GSJ Board (Device Tree 11 model = "Quanta GSJ Board (Device Tree v12)";
12 compatible = "nuvoton,npcm750"; 12 compatible = "nuvoton,npcm750";
13 13
14 aliases { 14 aliases {
15 ethernet1 = &gmac0; 15 ethernet1 = &gmac0;
16 serial3 = &serial3; 16 serial3 = &serial3;
17 i2c1 = &i2c1; 17 i2c1 = &i2c1;
18 i2c2 = &i2c2; 18 i2c2 = &i2c2;
19 i2c3 = &i2c3; 19 i2c3 = &i2c3;
20 i2c4 = &i2c4; 20 i2c4 = &i2c4;
21 i2c8 = &i2c8; 21 i2c8 = &i2c8;
22 i2c9 = &i2c9; 22 i2c9 = &i2c9;
23 i2c10 = &i2c10; 23 i2c10 = &i2c10;
24 i2c11 = &i2c11; 24 i2c11 = &i2c11;
25 i2c12 = &i2c12; 25 i2c12 = &i2c12;
26 i2c15 = &i2c15; 26 i2c15 = &i2c15;
27 fiu0 = &fiu0; 27 fiu0 = &fiu0;
28 }; 28 };
29 29
30 chosen { 30 chosen {
31 stdout-path = &serial3; 31 stdout-path = &serial3;
32 }; 32 };
33 33
34 memory { 34 memory {
35 reg = <0 0x40000000>; 35 reg = <0 0x40000000>;
36 }; 36 };
37 37
38 leds { 38 leds {
39 compatible = "gpio-leds"; 39 compatible = "gpio-leds";
40 40
41 led-bmc-live { 41 led-bmc-live {
42 gpios = <&gpio4 15 GPI 42 gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
43 linux,default-trigger 43 linux,default-trigger = "heartbeat";
44 }; 44 };
45 45
46 LED_U2_0_LOCATE { 46 LED_U2_0_LOCATE {
47 gpios = <&gpio0 0 GPIO 47 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
48 default-state = "off"; 48 default-state = "off";
49 }; 49 };
50 50
51 LED_U2_1_LOCATE { 51 LED_U2_1_LOCATE {
52 gpios = <&gpio0 1 GPIO 52 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
53 default-state = "off"; 53 default-state = "off";
54 }; 54 };
55 55
56 LED_U2_2_LOCATE { 56 LED_U2_2_LOCATE {
57 gpios = <&gpio0 2 GPIO 57 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
58 default-state = "off"; 58 default-state = "off";
59 }; 59 };
60 60
61 LED_U2_3_LOCATE { 61 LED_U2_3_LOCATE {
62 gpios = <&gpio0 3 GPIO 62 gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
63 default-state = "off"; 63 default-state = "off";
64 }; 64 };
65 65
66 LED_U2_4_LOCATE { 66 LED_U2_4_LOCATE {
67 gpios = <&gpio0 10 GPI 67 gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
68 default-state = "off"; 68 default-state = "off";
69 }; 69 };
70 70
71 LED_U2_5_LOCATE { 71 LED_U2_5_LOCATE {
72 gpios = <&gpio0 11 GPI 72 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
73 default-state = "off"; 73 default-state = "off";
74 }; 74 };
75 75
76 LED_BMC_TRAY_PWRGD { 76 LED_BMC_TRAY_PWRGD {
77 gpios = <&gpio0 19 GPI 77 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
78 default-state = "off"; 78 default-state = "off";
79 }; 79 };
80 80
81 LED_U2_7_FAULT { 81 LED_U2_7_FAULT {
82 gpios = <&gpio6 8 GPIO 82 gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
83 default-state = "off"; 83 default-state = "off";
84 }; 84 };
85 85
86 LED_U2_6_LOCATE { 86 LED_U2_6_LOCATE {
87 gpios = <&gpio0 24 GPI 87 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
88 default-state = "off"; 88 default-state = "off";
89 }; 89 };
90 90
91 LED_U2_7_LOCATE { 91 LED_U2_7_LOCATE {
92 gpios = <&gpio0 25 GPI 92 gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
93 default-state = "off"; 93 default-state = "off";
94 }; 94 };
95 95
96 LED_U2_0_FAULT { 96 LED_U2_0_FAULT {
97 gpios = <&gpio2 20 GPI 97 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
98 default-state = "off"; 98 default-state = "off";
99 }; 99 };
100 100
101 LED_U2_1_FAULT { 101 LED_U2_1_FAULT {
102 gpios = <&gpio2 21 GPI 102 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
103 default-state = "off"; 103 default-state = "off";
104 }; 104 };
105 105
106 LED_U2_2_FAULT { 106 LED_U2_2_FAULT {
107 gpios = <&gpio2 22 GPI 107 gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
108 default-state = "off"; 108 default-state = "off";
109 }; 109 };
110 110
111 LED_U2_3_FAULT { 111 LED_U2_3_FAULT {
112 gpios = <&gpio2 23 GPI 112 gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
113 default-state = "off"; 113 default-state = "off";
114 }; 114 };
115 115
116 LED_U2_4_FAULT { 116 LED_U2_4_FAULT {
117 gpios = <&gpio2 24 GPI 117 gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>;
118 default-state = "off"; 118 default-state = "off";
119 }; 119 };
120 120
121 LED_U2_5_FAULT { 121 LED_U2_5_FAULT {
122 gpios = <&gpio2 25 GPI 122 gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
123 default-state = "off"; 123 default-state = "off";
124 }; 124 };
125 125
126 LED_U2_6_FAULT { 126 LED_U2_6_FAULT {
127 gpios = <&gpio2 26 GPI 127 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
128 default-state = "off"; 128 default-state = "off";
129 }; 129 };
130 }; 130 };
131 }; 131 };
132 132
133 &fiu0 { 133 &fiu0 {
134 pinctrl-names = "default"; 134 pinctrl-names = "default";
135 pinctrl-0 = <&spi0cs1_pins>; 135 pinctrl-0 = <&spi0cs1_pins>;
136 status = "okay"; 136 status = "okay";
137 137
138 flash@0 { 138 flash@0 {
139 compatible = "jedec,spi-nor"; 139 compatible = "jedec,spi-nor";
140 #address-cells = <1>; 140 #address-cells = <1>;
141 #size-cells = <1>; 141 #size-cells = <1>;
142 reg = <0>; 142 reg = <0>;
143 spi-rx-bus-width = <2>; 143 spi-rx-bus-width = <2>;
144 144
145 partitions { 145 partitions {
146 compatible = "fixed-pa 146 compatible = "fixed-partitions";
147 #address-cells = <1>; 147 #address-cells = <1>;
148 #size-cells = <1>; 148 #size-cells = <1>;
149 bmc@0 { !! 149 bmc@0{
150 label = "bmc"; 150 label = "bmc";
151 reg = <0x00000 151 reg = <0x000000 0x2000000>;
152 }; 152 };
153 u-boot@0 { 153 u-boot@0 {
154 label = "u-boo 154 label = "u-boot";
155 reg = <0x00000 155 reg = <0x0000000 0x80000>;
156 read-only; 156 read-only;
157 }; 157 };
158 u-boot-env@100000 { !! 158 u-boot-env@100000{
159 label = "u-boo 159 label = "u-boot-env";
160 reg = <0x00100 160 reg = <0x00100000 0x40000>;
161 }; 161 };
162 kernel@200000 { 162 kernel@200000 {
163 label = "kerne 163 label = "kernel";
164 reg = <0x02000 164 reg = <0x0200000 0x600000>;
165 }; 165 };
166 rofs@800000 { 166 rofs@800000 {
167 label = "rofs" 167 label = "rofs";
168 reg = <0x80000 168 reg = <0x800000 0x1400000>;
169 }; 169 };
170 rwfs@1c00000 { 170 rwfs@1c00000 {
171 label = "rwfs" 171 label = "rwfs";
172 reg = <0x1c000 172 reg = <0x1c00000 0x300000>;
173 }; 173 };
174 reserved@1f00000 { 174 reserved@1f00000 {
175 label = "reser 175 label = "reserved";
176 reg = <0x1f000 176 reg = <0x1f00000 0x100000>;
177 }; 177 };
178 }; 178 };
179 }; 179 };
180 }; 180 };
181 181
182 &gmac0 { 182 &gmac0 {
183 phy-mode = "rgmii-id"; 183 phy-mode = "rgmii-id";
184 status = "okay"; 184 status = "okay";
185 }; 185 };
186 186
187 &ehci1 { 187 &ehci1 {
188 status = "okay"; 188 status = "okay";
189 }; 189 };
190 190
191 &watchdog1 { 191 &watchdog1 {
192 status = "okay"; 192 status = "okay";
193 }; 193 };
194 194
195 &rng { 195 &rng {
196 status = "okay"; 196 status = "okay";
197 }; 197 };
198 198
199 &serial0 { 199 &serial0 {
200 status = "okay"; 200 status = "okay";
201 }; 201 };
202 202
203 &serial1 { 203 &serial1 {
204 status = "okay"; 204 status = "okay";
205 }; 205 };
206 206
207 &serial2 { 207 &serial2 {
208 status = "okay"; 208 status = "okay";
209 }; 209 };
210 210
211 &serial3 { 211 &serial3 {
212 status = "okay"; 212 status = "okay";
213 }; 213 };
214 214
215 &adc { 215 &adc {
216 status = "okay"; 216 status = "okay";
217 }; 217 };
218 218
219 &i2c1 { 219 &i2c1 {
220 status = "okay"; 220 status = "okay";
221 221
222 lm75@5c { 222 lm75@5c {
223 compatible = "maxim,max31725"; 223 compatible = "maxim,max31725";
224 reg = <0x5c>; 224 reg = <0x5c>;
225 status = "okay"; 225 status = "okay";
226 }; 226 };
227 }; 227 };
228 228
229 &i2c2 { 229 &i2c2 {
230 status = "okay"; 230 status = "okay";
231 231
232 lm75@5c { 232 lm75@5c {
233 compatible = "maxim,max31725"; 233 compatible = "maxim,max31725";
234 reg = <0x5c>; 234 reg = <0x5c>;
235 status = "okay"; 235 status = "okay";
236 }; 236 };
237 }; 237 };
238 238
239 &i2c3 { 239 &i2c3 {
240 status = "okay"; 240 status = "okay";
241 241
242 lm75@5c { 242 lm75@5c {
243 compatible = "maxim,max31725"; 243 compatible = "maxim,max31725";
244 reg = <0x5c>; 244 reg = <0x5c>;
245 }; 245 };
246 }; 246 };
247 247
248 &i2c4 { 248 &i2c4 {
249 status = "okay"; 249 status = "okay";
250 250
251 lm75@5c { 251 lm75@5c {
252 compatible = "maxim,max31725"; 252 compatible = "maxim,max31725";
253 reg = <0x5c>; 253 reg = <0x5c>;
254 }; 254 };
255 }; 255 };
256 256
257 &i2c8 { 257 &i2c8 {
258 status = "okay"; 258 status = "okay";
259 }; 259 };
260 260
261 &i2c9 { 261 &i2c9 {
262 status = "okay"; 262 status = "okay";
263 263
264 eeprom@55 { 264 eeprom@55 {
265 compatible = "atmel,24c64"; 265 compatible = "atmel,24c64";
266 reg = <0x55>; 266 reg = <0x55>;
267 }; 267 };
268 }; 268 };
269 269
270 &i2c10 { 270 &i2c10 {
271 status = "okay"; 271 status = "okay";
272 272
273 eeprom@55 { 273 eeprom@55 {
274 compatible = "atmel,24c64"; 274 compatible = "atmel,24c64";
275 reg = <0x55>; 275 reg = <0x55>;
276 }; 276 };
277 }; 277 };
278 278
279 &i2c11 { 279 &i2c11 {
280 status = "okay"; 280 status = "okay";
281 281
282 /* P12V Quarter Brick DC/DC Power Modu 282 /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */
283 power-brick@36 { 283 power-brick@36 {
284 compatible = "delta,dps800"; 284 compatible = "delta,dps800";
285 reg = <0x36>; 285 reg = <0x36>;
286 }; 286 };
287 287
288 hotswap@15 { 288 hotswap@15 {
289 compatible = "ti,lm5066i"; 289 compatible = "ti,lm5066i";
290 reg = <0x15>; 290 reg = <0x15>;
291 }; 291 };
292 }; 292 };
293 293
294 &i2c12 { 294 &i2c12 {
295 status = "okay"; 295 status = "okay";
296 296
297 ucd90160@6b { 297 ucd90160@6b {
298 compatible = "ti,ucd90160"; 298 compatible = "ti,ucd90160";
299 reg = <0x6b>; 299 reg = <0x6b>;
300 }; 300 };
301 }; 301 };
302 302
303 &i2c15 { 303 &i2c15 {
304 status = "okay"; 304 status = "okay";
305 305
306 i2c-mux@75 { !! 306 i2c-switch@75 {
307 compatible = "nxp,pca9548"; 307 compatible = "nxp,pca9548";
308 #address-cells = <1>; 308 #address-cells = <1>;
309 #size-cells = <0>; 309 #size-cells = <0>;
310 reg = <0x75>; 310 reg = <0x75>;
311 i2c-mux-idle-disconnect; 311 i2c-mux-idle-disconnect;
312 312
313 i2c_u20: i2c@0 { 313 i2c_u20: i2c@0 {
314 #address-cells = <1>; 314 #address-cells = <1>;
315 #size-cells = <0>; 315 #size-cells = <0>;
316 reg = <0>; 316 reg = <0>;
317 }; 317 };
318 318
319 i2c_u21: i2c@1 { 319 i2c_u21: i2c@1 {
320 #address-cells = <1>; 320 #address-cells = <1>;
321 #size-cells = <0>; 321 #size-cells = <0>;
322 reg = <1>; 322 reg = <1>;
323 }; 323 };
324 324
325 i2c_u22: i2c@2 { 325 i2c_u22: i2c@2 {
326 #address-cells = <1>; 326 #address-cells = <1>;
327 #size-cells = <0>; 327 #size-cells = <0>;
328 reg = <2>; 328 reg = <2>;
329 }; 329 };
330 330
331 i2c_u23: i2c@3 { 331 i2c_u23: i2c@3 {
332 #address-cells = <1>; 332 #address-cells = <1>;
333 #size-cells = <0>; 333 #size-cells = <0>;
334 reg = <3>; 334 reg = <3>;
335 }; 335 };
336 336
337 i2c_u24: i2c@4 { 337 i2c_u24: i2c@4 {
338 #address-cells = <1>; 338 #address-cells = <1>;
339 #size-cells = <0>; 339 #size-cells = <0>;
340 reg = <4>; 340 reg = <4>;
341 }; 341 };
342 342
343 i2c_u25: i2c@5 { 343 i2c_u25: i2c@5 {
344 #address-cells = <1>; 344 #address-cells = <1>;
345 #size-cells = <0>; 345 #size-cells = <0>;
346 reg = <5>; 346 reg = <5>;
347 }; 347 };
348 348
349 i2c_u26: i2c@6 { 349 i2c_u26: i2c@6 {
350 #address-cells = <1>; 350 #address-cells = <1>;
351 #size-cells = <0>; 351 #size-cells = <0>;
352 reg = <6>; 352 reg = <6>;
353 }; 353 };
354 354
355 i2c_u27: i2c@7 { 355 i2c_u27: i2c@7 {
356 #address-cells = <1>; 356 #address-cells = <1>;
357 #size-cells = <0>; 357 #size-cells = <0>;
358 reg = <7>; 358 reg = <7>;
359 }; 359 };
360 }; 360 };
361 }; 361 };
362 362
363 &pwm_fan { 363 &pwm_fan {
364 pinctrl-names = "default"; 364 pinctrl-names = "default";
365 pinctrl-0 = <&pwm0_pins &pwm1_pins &pw 365 pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins
366 &fanin0_pins &fanin1_p 366 &fanin0_pins &fanin1_pins
367 &fanin2_pins &fanin3_p 367 &fanin2_pins &fanin3_pins
368 &fanin4_pins &fanin5_p 368 &fanin4_pins &fanin5_pins>;
369 status = "okay"; 369 status = "okay";
370 370
371 fan@0 { 371 fan@0 {
372 reg = <0x00>; 372 reg = <0x00>;
373 fan-tach-ch = /bits/ 8 <0x00 0 373 fan-tach-ch = /bits/ 8 <0x00 0x01>;
374 cooling-levels = <127 255>; 374 cooling-levels = <127 255>;
375 }; 375 };
376 376
377 fan@1 { 377 fan@1 {
378 reg = <0x01>; 378 reg = <0x01>;
379 fan-tach-ch = /bits/ 8 <0x02 0 379 fan-tach-ch = /bits/ 8 <0x02 0x03>;
380 cooling-levels = /bits/ 8 <127 380 cooling-levels = /bits/ 8 <127 255>;
381 }; 381 };
382 382
383 fan@2 { 383 fan@2 {
384 reg = <0x02>; 384 reg = <0x02>;
385 fan-tach-ch = /bits/ 8 <0x04 0 385 fan-tach-ch = /bits/ 8 <0x04 0x05>;
386 cooling-levels = /bits/ 8 <127 386 cooling-levels = /bits/ 8 <127 255>;
387 }; 387 };
388 }; 388 };
389 389
390 &pinctrl { 390 &pinctrl {
391 pinctrl-names = "default"; 391 pinctrl-names = "default";
392 pinctrl-0 = < 392 pinctrl-0 = <
393 /* GPI pins*/ 393 /* GPI pins*/
394 &gpio8_pins 394 &gpio8_pins
395 &gpio9_pins 395 &gpio9_pins
396 &gpio12_pins 396 &gpio12_pins
397 &gpio13_pins 397 &gpio13_pins
398 &gpio14_pins 398 &gpio14_pins
399 &gpio60_pins 399 &gpio60_pins
400 &gpio83_pins 400 &gpio83_pins
401 &gpio91_pins 401 &gpio91_pins
402 &gpio92_pins 402 &gpio92_pins
403 &gpio95_pins 403 &gpio95_pins
404 &gpio136_pins 404 &gpio136_pins
405 &gpio137_pins 405 &gpio137_pins
406 &gpio141_pins 406 &gpio141_pins
407 &gpio144_pins 407 &gpio144_pins
408 &gpio145_pins 408 &gpio145_pins
409 &gpio146_pins 409 &gpio146_pins
410 &gpio147_pins 410 &gpio147_pins
411 &gpio148_pins 411 &gpio148_pins
412 &gpio149_pins 412 &gpio149_pins
413 &gpio150_pins 413 &gpio150_pins
414 &gpio151_pins 414 &gpio151_pins
415 &gpio152_pins 415 &gpio152_pins
416 &gpio153_pins 416 &gpio153_pins
417 &gpio154_pins 417 &gpio154_pins
418 &gpio155_pins 418 &gpio155_pins
419 &gpio156_pins 419 &gpio156_pins
420 &gpio157_pins 420 &gpio157_pins
421 &gpio158_pins 421 &gpio158_pins
422 &gpio159_pins 422 &gpio159_pins
423 &gpio161_pins 423 &gpio161_pins
424 &gpio162_pins 424 &gpio162_pins
425 &gpio163_pins 425 &gpio163_pins
426 &gpio164_pins 426 &gpio164_pins
427 &gpio165_pins 427 &gpio165_pins
428 &gpio166_pins 428 &gpio166_pins
429 &gpio167_pins 429 &gpio167_pins
430 &gpio168_pins 430 &gpio168_pins
431 &gpio169_pins 431 &gpio169_pins
432 &gpio170_pins 432 &gpio170_pins
433 &gpio177_pins 433 &gpio177_pins
434 &gpio191_pins 434 &gpio191_pins
435 &gpio192_pins 435 &gpio192_pins
436 &gpio203_pins 436 &gpio203_pins
437 /* GPO pins*/ 437 /* GPO pins*/
438 &gpio0pp_pins 438 &gpio0pp_pins
439 &gpio1pp_pins 439 &gpio1pp_pins
440 &gpio2pp_pins 440 &gpio2pp_pins
441 &gpio3pp_pins 441 &gpio3pp_pins
442 &gpio4pp_pins 442 &gpio4pp_pins
443 &gpio5pp_pins 443 &gpio5pp_pins
444 &gpio6pp_pins 444 &gpio6pp_pins
445 &gpio7pp_pins 445 &gpio7pp_pins
446 &gpio10pp_pins 446 &gpio10pp_pins
447 &gpio11pp_pins 447 &gpio11pp_pins
448 &gpio15od_pins 448 &gpio15od_pins
449 &gpio17pp_pins 449 &gpio17pp_pins
450 &gpio18pp_pins 450 &gpio18pp_pins
451 &gpio19pp_pins 451 &gpio19pp_pins
452 &gpio24pp_pins 452 &gpio24pp_pins
453 &gpio25pp_pins 453 &gpio25pp_pins
454 &gpio37od_pins 454 &gpio37od_pins
455 &gpio59pp_pins 455 &gpio59pp_pins
456 &gpio72od_pins 456 &gpio72od_pins
457 &gpio73od_pins 457 &gpio73od_pins
458 &gpio74od_pins 458 &gpio74od_pins
459 &gpio75od_pins 459 &gpio75od_pins
460 &gpio76od_pins 460 &gpio76od_pins
461 &gpio77od_pins 461 &gpio77od_pins
462 &gpio78od_pins 462 &gpio78od_pins
463 &gpio79od_pins 463 &gpio79od_pins
464 &gpio84pp_pins 464 &gpio84pp_pins
465 &gpio85pp_pins 465 &gpio85pp_pins
466 &gpio86pp_pins 466 &gpio86pp_pins
467 &gpio87pp_pins 467 &gpio87pp_pins
468 &gpio88pp_pins 468 &gpio88pp_pins
469 &gpio89pp_pins 469 &gpio89pp_pins
470 &gpio90pp_pins 470 &gpio90pp_pins
471 &gpio93pp_pins 471 &gpio93pp_pins
472 &gpio94pp_pins 472 &gpio94pp_pins
473 &gpio125pp_pins 473 &gpio125pp_pins
474 &gpio126od_pins 474 &gpio126od_pins
475 &gpio127od_pins 475 &gpio127od_pins
476 &gpio142od_pins 476 &gpio142od_pins
477 &gpio143ol_pins 477 &gpio143ol_pins
478 &gpio175od_pins 478 &gpio175od_pins
479 &gpio176od_pins 479 &gpio176od_pins
480 &gpio190od_pins 480 &gpio190od_pins
481 &gpio194pp_pins 481 &gpio194pp_pins
482 &gpio195od_pins 482 &gpio195od_pins
483 &gpio196od_pins 483 &gpio196od_pins
484 &gpio197od_pins 484 &gpio197od_pins
485 &gpio198od_pins 485 &gpio198od_pins
486 &gpio199od_pins 486 &gpio199od_pins
487 &gpio200pp_pins 487 &gpio200pp_pins
488 &gpio202od_pins 488 &gpio202od_pins
489 >; 489 >;
490 }; 490 };
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