1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/input/input.h>
5 #include "tegra114.dtsi" 5 #include "tegra114.dtsi"
6 6
7 / { 7 / {
8 model = "NVIDIA SHIELD"; 8 model = "NVIDIA SHIELD";
9 compatible = "nvidia,roth", "nvidia,te 9 compatible = "nvidia,roth", "nvidia,tegra114";
10 10
11 chosen { 11 chosen {
12 /* SHIELD's bootloader's argum 12 /* SHIELD's bootloader's arguments need to be overridden */
13 bootargs = "console=ttyS0,1152 13 bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
14 /* SHIELD's bootloader will pl 14 /* SHIELD's bootloader will place initrd at this address */
15 linux,initrd-start = <0x820000 15 linux,initrd-start = <0x82000000>;
16 linux,initrd-end = <0x82800000 16 linux,initrd-end = <0x82800000>;
17 }; 17 };
18 18
19 aliases { 19 aliases {
20 serial0 = &uartd; 20 serial0 = &uartd;
21 }; 21 };
22 22
23 firmware { 23 firmware {
24 trusted-foundations { 24 trusted-foundations {
25 compatible = "tlm,trus 25 compatible = "tlm,trusted-foundations";
26 tlm,version-major = <2 26 tlm,version-major = <2>;
27 tlm,version-minor = <8 27 tlm,version-minor = <8>;
28 }; 28 };
29 }; 29 };
30 30
31 memory@80000000 { 31 memory@80000000 {
32 /* memory >= 0x79600000 is res 32 /* memory >= 0x79600000 is reserved for firmware usage */
33 reg = <0x80000000 0x79600000>; 33 reg = <0x80000000 0x79600000>;
34 }; 34 };
35 35
36 host1x@50000000 { 36 host1x@50000000 {
37 dsi@54300000 { 37 dsi@54300000 {
38 status = "okay"; 38 status = "okay";
39 39
40 avdd-dsi-csi-supply = 40 avdd-dsi-csi-supply = <&vdd_1v2_ap>;
41 41
42 panel@0 { 42 panel@0 {
43 compatible = " 43 compatible = "lg,lh500wx1-sd03";
44 reg = <0>; 44 reg = <0>;
45 45
46 power-supply = 46 power-supply = <&vdd_lcd>;
47 backlight = <& 47 backlight = <&backlight>;
48 }; 48 };
49 }; 49 };
50 }; 50 };
51 51
52 pinmux@70000868 { 52 pinmux@70000868 {
53 pinctrl-names = "default"; 53 pinctrl-names = "default";
54 pinctrl-0 = <&state_default>; 54 pinctrl-0 = <&state_default>;
55 55
56 state_default: pinmux { 56 state_default: pinmux {
57 clk1_out_pw4 { 57 clk1_out_pw4 {
58 nvidia,pins = 58 nvidia,pins = "clk1_out_pw4";
59 nvidia,functio 59 nvidia,function = "extperiph1";
60 nvidia,pull = 60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristat 61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 nvidia,enable- 62 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63 }; 63 };
64 dap1_din_pn1 { 64 dap1_din_pn1 {
65 nvidia,pins = 65 nvidia,pins = "dap1_din_pn1";
66 nvidia,functio 66 nvidia,function = "i2s0";
67 nvidia,pull = 67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristat 68 nvidia,tristate = <TEGRA_PIN_ENABLE>;
69 nvidia,enable- 69 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
70 }; 70 };
71 dap1_dout_pn2 { 71 dap1_dout_pn2 {
72 nvidia,pins = 72 nvidia,pins = "dap1_dout_pn2",
73 73 "dap1_fs_pn0",
74 74 "dap1_sclk_pn3";
75 nvidia,functio 75 nvidia,function = "i2s0";
76 nvidia,pull = 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristat 77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 nvidia,enable- 78 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
79 }; 79 };
80 dap2_din_pa4 { 80 dap2_din_pa4 {
81 nvidia,pins = 81 nvidia,pins = "dap2_din_pa4";
82 nvidia,functio 82 nvidia,function = "i2s1";
83 nvidia,pull = 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristat 84 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 nvidia,enable- 85 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86 }; 86 };
87 dap2_dout_pa5 { 87 dap2_dout_pa5 {
88 nvidia,pins = 88 nvidia,pins = "dap2_dout_pa5",
89 89 "dap2_fs_pa2",
90 90 "dap2_sclk_pa3";
91 nvidia,functio 91 nvidia,function = "i2s1";
92 nvidia,pull = 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristat 93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,enable- 94 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
95 }; 95 };
96 dap4_din_pp5 { 96 dap4_din_pp5 {
97 nvidia,pins = 97 nvidia,pins = "dap4_din_pp5",
98 98 "dap4_dout_pp6",
99 99 "dap4_fs_pp4",
100 100 "dap4_sclk_pp7";
101 nvidia,functio 101 nvidia,function = "i2s3";
102 nvidia,pull = 102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristat 103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,enable- 104 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
105 }; 105 };
106 dvfs_pwm_px0 { 106 dvfs_pwm_px0 {
107 nvidia,pins = 107 nvidia,pins = "dvfs_pwm_px0",
108 108 "dvfs_clk_px2";
109 nvidia,functio 109 nvidia,function = "cldvfs";
110 nvidia,pull = 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristat 111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 nvidia,enable- 112 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
113 }; 113 };
114 ulpi_clk_py0 { 114 ulpi_clk_py0 {
115 nvidia,pins = 115 nvidia,pins = "ulpi_clk_py0",
116 116 "ulpi_data0_po1",
117 117 "ulpi_data1_po2",
118 118 "ulpi_data2_po3",
119 119 "ulpi_data3_po4",
120 120 "ulpi_data4_po5",
121 121 "ulpi_data5_po6",
122 122 "ulpi_data6_po7",
123 123 "ulpi_data7_po0";
124 nvidia,functio 124 nvidia,function = "ulpi";
125 nvidia,pull = 125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristat 126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 nvidia,enable- 127 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128 }; 128 };
129 ulpi_dir_py1 { 129 ulpi_dir_py1 {
130 nvidia,pins = 130 nvidia,pins = "ulpi_dir_py1",
131 131 "ulpi_nxt_py2";
132 nvidia,functio 132 nvidia,function = "ulpi";
133 nvidia,pull = 133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
134 nvidia,tristat 134 nvidia,tristate = <TEGRA_PIN_ENABLE>;
135 nvidia,enable- 135 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
136 }; 136 };
137 ulpi_stp_py3 { 137 ulpi_stp_py3 {
138 nvidia,pins = 138 nvidia,pins = "ulpi_stp_py3";
139 nvidia,functio 139 nvidia,function = "ulpi";
140 nvidia,pull = 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristat 141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable- 142 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
143 }; 143 };
144 cam_i2c_scl_pbb1 { 144 cam_i2c_scl_pbb1 {
145 nvidia,pins = 145 nvidia,pins = "cam_i2c_scl_pbb1",
146 146 "cam_i2c_sda_pbb2";
147 nvidia,functio 147 nvidia,function = "i2c3";
148 nvidia,pull = 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristat 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 nvidia,enable- 150 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
151 nvidia,lock = 151 nvidia,lock = <TEGRA_PIN_DISABLE>;
152 nvidia,open-dr 152 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
153 }; 153 };
154 cam_mclk_pcc0 { 154 cam_mclk_pcc0 {
155 nvidia,pins = 155 nvidia,pins = "cam_mclk_pcc0",
156 156 "pbb0";
157 nvidia,functio 157 nvidia,function = "vi_alt3";
158 nvidia,pull = 158 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159 nvidia,tristat 159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 nvidia,enable- 160 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
161 nvidia,lock = 161 nvidia,lock = <TEGRA_PIN_DISABLE>;
162 }; 162 };
163 pbb4 { 163 pbb4 {
164 nvidia,pins = 164 nvidia,pins = "pbb4";
165 nvidia,functio 165 nvidia,function = "vgp4";
166 nvidia,pull = 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristat 167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable- 168 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169 nvidia,lock = 169 nvidia,lock = <TEGRA_PIN_DISABLE>;
170 }; 170 };
171 gen2_i2c_scl_pt5 { 171 gen2_i2c_scl_pt5 {
172 nvidia,pins = 172 nvidia,pins = "gen2_i2c_scl_pt5",
173 173 "gen2_i2c_sda_pt6";
174 nvidia,functio 174 nvidia,function = "i2c2";
175 nvidia,pull = 175 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176 nvidia,tristat 176 nvidia,tristate = <TEGRA_PIN_DISABLE>;
177 nvidia,enable- 177 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178 nvidia,lock = 178 nvidia,lock = <TEGRA_PIN_DISABLE>;
179 nvidia,open-dr 179 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
180 }; 180 };
181 gmi_a16_pj7 { 181 gmi_a16_pj7 {
182 nvidia,pins = 182 nvidia,pins = "gmi_a16_pj7",
183 183 "gmi_a19_pk7";
184 nvidia,functio 184 nvidia,function = "uartd";
185 nvidia,pull = 185 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186 nvidia,tristat 186 nvidia,tristate = <TEGRA_PIN_DISABLE>;
187 nvidia,enable- 187 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188 }; 188 };
189 gmi_a17_pb0 { 189 gmi_a17_pb0 {
190 nvidia,pins = 190 nvidia,pins = "gmi_a17_pb0",
191 191 "gmi_a18_pb1";
192 nvidia,functio 192 nvidia,function = "uartd";
193 nvidia,pull = 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 nvidia,tristat 194 nvidia,tristate = <TEGRA_PIN_ENABLE>;
195 nvidia,enable- 195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
196 }; 196 };
197 gmi_ad5_pg5 { 197 gmi_ad5_pg5 {
198 nvidia,pins = 198 nvidia,pins = "gmi_ad5_pg5",
199 199 "gmi_wr_n_pi0";
200 nvidia,functio 200 nvidia,function = "spi4";
201 nvidia,pull = 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristat 202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 nvidia,enable- 203 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
204 }; 204 };
205 gmi_ad6_pg6 { 205 gmi_ad6_pg6 {
206 nvidia,pins = 206 nvidia,pins = "gmi_ad6_pg6",
207 207 "gmi_ad7_pg7";
208 nvidia,functio 208 nvidia,function = "spi4";
209 nvidia,pull = 209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristat 210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 nvidia,enable- 211 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
212 }; 212 };
213 gmi_ad12_ph4 { 213 gmi_ad12_ph4 {
214 nvidia,pins = 214 nvidia,pins = "gmi_ad12_ph4";
215 nvidia,functio 215 nvidia,function = "rsvd4";
216 nvidia,pull = 216 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
217 nvidia,tristat 217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 nvidia,enable- 218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219 }; 219 };
220 gmi_cs6_n_pi13 { 220 gmi_cs6_n_pi13 {
221 nvidia,pins = 221 nvidia,pins = "gmi_cs6_n_pi3";
222 nvidia,functio 222 nvidia,function = "nand";
223 nvidia,pull = 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristat 224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 nvidia,enable- 225 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226 }; 226 };
227 gmi_ad9_ph1 { 227 gmi_ad9_ph1 {
228 nvidia,pins = 228 nvidia,pins = "gmi_ad9_ph1";
229 nvidia,functio 229 nvidia,function = "pwm1";
230 nvidia,pull = 230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231 nvidia,tristat 231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 nvidia,enable- 232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233 }; 233 };
234 gmi_cs1_n_pj2 { 234 gmi_cs1_n_pj2 {
235 nvidia,pins = 235 nvidia,pins = "gmi_cs1_n_pj2",
236 236 "gmi_oe_n_pi1";
237 nvidia,functio 237 nvidia,function = "soc";
238 nvidia,pull = 238 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239 nvidia,tristat 239 nvidia,tristate = <TEGRA_PIN_ENABLE>;
240 nvidia,enable- 240 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241 }; 241 };
242 gmi_rst_n_pi4 { 242 gmi_rst_n_pi4 {
243 nvidia,pins = 243 nvidia,pins = "gmi_rst_n_pi4";
244 nvidia,functio 244 nvidia,function = "gmi";
245 nvidia,pull = 245 nvidia,pull = <TEGRA_PIN_PULL_UP>;
246 nvidia,tristat 246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable- 247 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 }; 248 };
249 gmi_iordy_pi5 { 249 gmi_iordy_pi5 {
250 nvidia,pins = 250 nvidia,pins = "gmi_iordy_pi5";
251 nvidia,functio 251 nvidia,function = "gmi";
252 nvidia,pull = 252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristat 253 nvidia,tristate = <TEGRA_PIN_ENABLE>;
254 nvidia,enable- 254 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 }; 255 };
256 clk2_out_pw5 { 256 clk2_out_pw5 {
257 nvidia,pins = 257 nvidia,pins = "clk2_out_pw5";
258 nvidia,functio 258 nvidia,function = "extperiph2";
259 nvidia,pull = 259 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260 nvidia,tristat 260 nvidia,tristate = <TEGRA_PIN_DISABLE>;
261 nvidia,enable- 261 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262 }; 262 };
263 sdmmc1_clk_pz0 { 263 sdmmc1_clk_pz0 {
264 nvidia,pins = 264 nvidia,pins = "sdmmc1_clk_pz0";
265 nvidia,functio 265 nvidia,function = "sdmmc1";
266 nvidia,pull = 266 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267 nvidia,tristat 267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
268 nvidia,enable- 268 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269 }; 269 };
270 sdmmc1_cmd_pz1 { 270 sdmmc1_cmd_pz1 {
271 nvidia,pins = 271 nvidia,pins = "sdmmc1_cmd_pz1",
272 272 "sdmmc1_dat0_py7",
273 273 "sdmmc1_dat1_py6",
274 274 "sdmmc1_dat2_py5",
275 275 "sdmmc1_dat3_py4";
276 nvidia,functio 276 nvidia,function = "sdmmc1";
277 nvidia,pull = 277 nvidia,pull = <TEGRA_PIN_PULL_UP>;
278 nvidia,tristat 278 nvidia,tristate = <TEGRA_PIN_DISABLE>;
279 nvidia,enable- 279 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280 }; 280 };
281 sdmmc3_clk_pa6 { 281 sdmmc3_clk_pa6 {
282 nvidia,pins = 282 nvidia,pins = "sdmmc3_clk_pa6";
283 nvidia,functio 283 nvidia,function = "sdmmc3";
284 nvidia,pull = 284 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
285 nvidia,tristat 285 nvidia,tristate = <TEGRA_PIN_DISABLE>;
286 nvidia,enable- 286 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
287 }; 287 };
288 sdmmc3_cmd_pa7 { 288 sdmmc3_cmd_pa7 {
289 nvidia,pins = 289 nvidia,pins = "sdmmc3_cmd_pa7",
290 290 "sdmmc3_dat0_pb7",
291 291 "sdmmc3_dat1_pb6",
292 292 "sdmmc3_dat2_pb5",
293 293 "sdmmc3_dat3_pb4",
294 294 "sdmmc3_cd_n_pv2",
295 295 "sdmmc3_clk_lb_out_pee4",
296 296 "sdmmc3_clk_lb_in_pee5";
297 nvidia,functio 297 nvidia,function = "sdmmc3";
298 nvidia,pull = 298 nvidia,pull = <TEGRA_PIN_PULL_UP>;
299 nvidia,tristat 299 nvidia,tristate = <TEGRA_PIN_DISABLE>;
300 nvidia,enable- 300 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
301 }; 301 };
302 kb_col4_pq4 { 302 kb_col4_pq4 {
303 nvidia,pins = 303 nvidia,pins = "kb_col4_pq4";
304 nvidia,functio 304 nvidia,function = "sdmmc3";
305 nvidia,pull = 305 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
306 nvidia,tristat 306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
307 nvidia,enable- 307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 }; 308 };
309 sdmmc4_clk_pcc4 { 309 sdmmc4_clk_pcc4 {
310 nvidia,pins = 310 nvidia,pins = "sdmmc4_clk_pcc4";
311 nvidia,functio 311 nvidia,function = "sdmmc4";
312 nvidia,pull = 312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313 nvidia,tristat 313 nvidia,tristate = <TEGRA_PIN_DISABLE>;
314 nvidia,enable- 314 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315 }; 315 };
316 sdmmc4_cmd_pt7 { 316 sdmmc4_cmd_pt7 {
317 nvidia,pins = 317 nvidia,pins = "sdmmc4_cmd_pt7",
318 318 "sdmmc4_dat0_paa0",
319 319 "sdmmc4_dat1_paa1",
320 320 "sdmmc4_dat2_paa2",
321 321 "sdmmc4_dat3_paa3",
322 322 "sdmmc4_dat4_paa4",
323 323 "sdmmc4_dat5_paa5",
324 324 "sdmmc4_dat6_paa6",
325 325 "sdmmc4_dat7_paa7";
326 nvidia,functio 326 nvidia,function = "sdmmc4";
327 nvidia,pull = 327 nvidia,pull = <TEGRA_PIN_PULL_UP>;
328 nvidia,tristat 328 nvidia,tristate = <TEGRA_PIN_DISABLE>;
329 nvidia,enable- 329 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
330 }; 330 };
331 clk_32k_out_pa0 { 331 clk_32k_out_pa0 {
332 nvidia,pins = 332 nvidia,pins = "clk_32k_out_pa0";
333 nvidia,functio 333 nvidia,function = "blink";
334 nvidia,pull = 334 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
335 nvidia,tristat 335 nvidia,tristate = <TEGRA_PIN_DISABLE>;
336 nvidia,enable- 336 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
337 }; 337 };
338 kb_col0_pq0 { 338 kb_col0_pq0 {
339 nvidia,pins = 339 nvidia,pins = "kb_col0_pq0",
340 340 "kb_col1_pq1",
341 341 "kb_col2_pq2",
342 342 "kb_row0_pr0",
343 343 "kb_row1_pr1",
344 344 "kb_row2_pr2",
345 345 "kb_row8_ps0";
346 nvidia,functio 346 nvidia,function = "kbc";
347 nvidia,pull = 347 nvidia,pull = <TEGRA_PIN_PULL_UP>;
348 nvidia,tristat 348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 nvidia,enable- 349 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350 }; 350 };
351 kb_row7_pr7 { 351 kb_row7_pr7 {
352 nvidia,pins = 352 nvidia,pins = "kb_row7_pr7";
353 nvidia,functio 353 nvidia,function = "rsvd2";
354 nvidia,pull = 354 nvidia,pull = <TEGRA_PIN_PULL_UP>;
355 nvidia,tristat 355 nvidia,tristate = <TEGRA_PIN_DISABLE>;
356 nvidia,enable- 356 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
357 }; 357 };
358 kb_row10_ps2 { 358 kb_row10_ps2 {
359 nvidia,pins = 359 nvidia,pins = "kb_row10_ps2";
360 nvidia,functio 360 nvidia,function = "uarta";
361 nvidia,pull = 361 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362 nvidia,tristat 362 nvidia,tristate = <TEGRA_PIN_ENABLE>;
363 nvidia,enable- 363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364 }; 364 };
365 kb_row9_ps1 { 365 kb_row9_ps1 {
366 nvidia,pins = 366 nvidia,pins = "kb_row9_ps1";
367 nvidia,functio 367 nvidia,function = "uarta";
368 nvidia,pull = 368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369 nvidia,tristat 369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
370 nvidia,enable- 370 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
371 }; 371 };
372 pwr_i2c_scl_pz6 { 372 pwr_i2c_scl_pz6 {
373 nvidia,pins = 373 nvidia,pins = "pwr_i2c_scl_pz6",
374 374 "pwr_i2c_sda_pz7";
375 nvidia,functio 375 nvidia,function = "i2cpwr";
376 nvidia,pull = 376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristat 377 nvidia,tristate = <TEGRA_PIN_DISABLE>;
378 nvidia,enable- 378 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379 nvidia,lock = 379 nvidia,lock = <TEGRA_PIN_DISABLE>;
380 nvidia,open-dr 380 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381 }; 381 };
382 sys_clk_req_pz5 { 382 sys_clk_req_pz5 {
383 nvidia,pins = 383 nvidia,pins = "sys_clk_req_pz5";
384 nvidia,functio 384 nvidia,function = "sysclk";
385 nvidia,pull = 385 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
386 nvidia,tristat 386 nvidia,tristate = <TEGRA_PIN_DISABLE>;
387 nvidia,enable- 387 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
388 }; 388 };
389 core_pwr_req { 389 core_pwr_req {
390 nvidia,pins = 390 nvidia,pins = "core_pwr_req";
391 nvidia,functio 391 nvidia,function = "pwron";
392 nvidia,pull = 392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristat 393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 nvidia,enable- 394 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
395 }; 395 };
396 cpu_pwr_req { 396 cpu_pwr_req {
397 nvidia,pins = 397 nvidia,pins = "cpu_pwr_req";
398 nvidia,functio 398 nvidia,function = "cpu";
399 nvidia,pull = 399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristat 400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 nvidia,enable- 401 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402 }; 402 };
403 pwr_int_n { 403 pwr_int_n {
404 nvidia,pins = 404 nvidia,pins = "pwr_int_n";
405 nvidia,functio 405 nvidia,function = "pmi";
406 nvidia,pull = 406 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407 nvidia,tristat 407 nvidia,tristate = <TEGRA_PIN_ENABLE>;
408 nvidia,enable- 408 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409 }; 409 };
410 reset_out_n { 410 reset_out_n {
411 nvidia,pins = 411 nvidia,pins = "reset_out_n";
412 nvidia,functio 412 nvidia,function = "reset_out_n";
413 nvidia,pull = 413 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristat 414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable- 415 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
416 }; 416 };
417 clk3_out_pee0 { 417 clk3_out_pee0 {
418 nvidia,pins = 418 nvidia,pins = "clk3_out_pee0";
419 nvidia,functio 419 nvidia,function = "extperiph3";
420 nvidia,pull = 420 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristat 421 nvidia,tristate = <TEGRA_PIN_DISABLE>;
422 nvidia,enable- 422 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
423 }; 423 };
424 gen1_i2c_scl_pc4 { 424 gen1_i2c_scl_pc4 {
425 nvidia,pins = 425 nvidia,pins = "gen1_i2c_scl_pc4",
426 426 "gen1_i2c_sda_pc5";
427 nvidia,functio 427 nvidia,function = "i2c1";
428 nvidia,pull = 428 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristat 429 nvidia,tristate = <TEGRA_PIN_DISABLE>;
430 nvidia,enable- 430 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
431 nvidia,lock = 431 nvidia,lock = <TEGRA_PIN_DISABLE>;
432 nvidia,open-dr 432 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
433 }; 433 };
434 uart2_cts_n_pj5 { 434 uart2_cts_n_pj5 {
435 nvidia,pins = 435 nvidia,pins = "uart2_cts_n_pj5";
436 nvidia,functio 436 nvidia,function = "uartb";
437 nvidia,pull = 437 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438 nvidia,tristat 438 nvidia,tristate = <TEGRA_PIN_ENABLE>;
439 nvidia,enable- 439 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
440 }; 440 };
441 uart2_rts_n_pj6 { 441 uart2_rts_n_pj6 {
442 nvidia,pins = 442 nvidia,pins = "uart2_rts_n_pj6";
443 nvidia,functio 443 nvidia,function = "uartb";
444 nvidia,pull = 444 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445 nvidia,tristat 445 nvidia,tristate = <TEGRA_PIN_DISABLE>;
446 nvidia,enable- 446 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
447 }; 447 };
448 uart2_rxd_pc3 { 448 uart2_rxd_pc3 {
449 nvidia,pins = 449 nvidia,pins = "uart2_rxd_pc3";
450 nvidia,functio 450 nvidia,function = "irda";
451 nvidia,pull = 451 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
452 nvidia,tristat 452 nvidia,tristate = <TEGRA_PIN_ENABLE>;
453 nvidia,enable- 453 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
454 }; 454 };
455 uart2_txd_pc2 { 455 uart2_txd_pc2 {
456 nvidia,pins = 456 nvidia,pins = "uart2_txd_pc2";
457 nvidia,functio 457 nvidia,function = "irda";
458 nvidia,pull = 458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459 nvidia,tristat 459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
460 nvidia,enable- 460 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
461 }; 461 };
462 uart3_cts_n_pa1 { 462 uart3_cts_n_pa1 {
463 nvidia,pins = 463 nvidia,pins = "uart3_cts_n_pa1",
464 464 "uart3_rxd_pw7";
465 nvidia,functio 465 nvidia,function = "uartc";
466 nvidia,pull = 466 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467 nvidia,tristat 467 nvidia,tristate = <TEGRA_PIN_ENABLE>;
468 nvidia,enable- 468 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469 }; 469 };
470 uart3_rts_n_pc0 { 470 uart3_rts_n_pc0 {
471 nvidia,pins = 471 nvidia,pins = "uart3_rts_n_pc0",
472 472 "uart3_txd_pw6";
473 nvidia,functio 473 nvidia,function = "uartc";
474 nvidia,pull = 474 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
475 nvidia,tristat 475 nvidia,tristate = <TEGRA_PIN_DISABLE>;
476 nvidia,enable- 476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477 }; 477 };
478 owr { 478 owr {
479 nvidia,pins = 479 nvidia,pins = "owr";
480 nvidia,functio 480 nvidia,function = "owr";
481 nvidia,pull = 481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482 nvidia,tristat 482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 nvidia,enable- 483 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484 }; 484 };
485 hdmi_cec_pee3 { 485 hdmi_cec_pee3 {
486 nvidia,pins = 486 nvidia,pins = "hdmi_cec_pee3";
487 nvidia,functio 487 nvidia,function = "cec";
488 nvidia,pull = 488 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
489 nvidia,tristat 489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
490 nvidia,enable- 490 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491 nvidia,lock = 491 nvidia,lock = <TEGRA_PIN_DISABLE>;
492 nvidia,open-dr 492 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
493 }; 493 };
494 ddc_scl_pv4 { 494 ddc_scl_pv4 {
495 nvidia,pins = 495 nvidia,pins = "ddc_scl_pv4",
496 496 "ddc_sda_pv5";
497 nvidia,functio 497 nvidia,function = "i2c4";
498 nvidia,pull = 498 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
499 nvidia,tristat 499 nvidia,tristate = <TEGRA_PIN_DISABLE>;
500 nvidia,enable- 500 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
501 nvidia,lock = 501 nvidia,lock = <TEGRA_PIN_DISABLE>;
502 nvidia,rcv-sel 502 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
503 }; 503 };
504 spdif_in_pk6 { 504 spdif_in_pk6 {
505 nvidia,pins = 505 nvidia,pins = "spdif_in_pk6";
506 nvidia,functio 506 nvidia,function = "usb";
507 nvidia,pull = 507 nvidia,pull = <TEGRA_PIN_PULL_UP>;
508 nvidia,tristat 508 nvidia,tristate = <TEGRA_PIN_DISABLE>;
509 nvidia,enable- 509 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510 nvidia,lock = 510 nvidia,lock = <TEGRA_PIN_DISABLE>;
511 }; 511 };
512 usb_vbus_en0_pn4 { 512 usb_vbus_en0_pn4 {
513 nvidia,pins = 513 nvidia,pins = "usb_vbus_en0_pn4";
514 nvidia,functio 514 nvidia,function = "usb";
515 nvidia,pull = 515 nvidia,pull = <TEGRA_PIN_PULL_UP>;
516 nvidia,tristat 516 nvidia,tristate = <TEGRA_PIN_DISABLE>;
517 nvidia,enable- 517 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
518 nvidia,lock = 518 nvidia,lock = <TEGRA_PIN_DISABLE>;
519 nvidia,open-dr 519 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
520 }; 520 };
521 gpio_x6_aud_px6 { 521 gpio_x6_aud_px6 {
522 nvidia,pins = 522 nvidia,pins = "gpio_x6_aud_px6";
523 nvidia,functio 523 nvidia,function = "spi6";
524 nvidia,pull = 524 nvidia,pull = <TEGRA_PIN_PULL_UP>;
525 nvidia,tristat 525 nvidia,tristate = <TEGRA_PIN_ENABLE>;
526 nvidia,enable- 526 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
527 }; 527 };
528 gpio_x1_aud_px1 { 528 gpio_x1_aud_px1 {
529 nvidia,pins = 529 nvidia,pins = "gpio_x1_aud_px1";
530 nvidia,functio 530 nvidia,function = "rsvd2";
531 nvidia,pull = 531 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
532 nvidia,tristat 532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
533 nvidia,enable- 533 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
534 }; 534 };
535 gpio_x7_aud_px7 { 535 gpio_x7_aud_px7 {
536 nvidia,pins = 536 nvidia,pins = "gpio_x7_aud_px7";
537 nvidia,functio 537 nvidia,function = "rsvd1";
538 nvidia,pull = 538 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
539 nvidia,tristat 539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
540 nvidia,enable- 540 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
541 }; 541 };
542 gmi_adv_n_pk0 { 542 gmi_adv_n_pk0 {
543 nvidia,pins = 543 nvidia,pins = "gmi_adv_n_pk0";
544 nvidia,functio 544 nvidia,function = "gmi";
545 nvidia,pull = 545 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546 nvidia,tristat 546 nvidia,tristate = <TEGRA_PIN_ENABLE>;
547 nvidia,enable- 547 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
548 }; 548 };
549 gmi_cs0_n_pj0 { 549 gmi_cs0_n_pj0 {
550 nvidia,pins = 550 nvidia,pins = "gmi_cs0_n_pj0";
551 nvidia,functio 551 nvidia,function = "gmi";
552 nvidia,pull = 552 nvidia,pull = <TEGRA_PIN_PULL_UP>;
553 nvidia,tristat 553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable- 554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555 }; 555 };
556 pu3 { 556 pu3 {
557 nvidia,pins = 557 nvidia,pins = "pu3";
558 nvidia,functio 558 nvidia,function = "pwm0";
559 nvidia,pull = 559 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
560 nvidia,tristat 560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
561 nvidia,enable- 561 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
562 }; 562 };
563 gpio_x4_aud_px4 { 563 gpio_x4_aud_px4 {
564 nvidia,pins = 564 nvidia,pins = "gpio_x4_aud_px4",
565 565 "gpio_x5_aud_px5";
566 nvidia,functio 566 nvidia,function = "rsvd1";
567 nvidia,pull = 567 nvidia,pull = <TEGRA_PIN_PULL_UP>;
568 nvidia,tristat 568 nvidia,tristate = <TEGRA_PIN_DISABLE>;
569 nvidia,enable- 569 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570 }; 570 };
571 gpio_x3_aud_px3 { 571 gpio_x3_aud_px3 {
572 nvidia,pins = 572 nvidia,pins = "gpio_x3_aud_px3";
573 nvidia,functio 573 nvidia,function = "rsvd4";
574 nvidia,pull = 574 nvidia,pull = <TEGRA_PIN_PULL_UP>;
575 nvidia,tristat 575 nvidia,tristate = <TEGRA_PIN_DISABLE>;
576 nvidia,enable- 576 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577 }; 577 };
578 gpio_w2_aud_pw2 { 578 gpio_w2_aud_pw2 {
579 nvidia,pins = 579 nvidia,pins = "gpio_w2_aud_pw2";
580 nvidia,functio 580 nvidia,function = "rsvd2";
581 nvidia,pull = 581 nvidia,pull = <TEGRA_PIN_PULL_UP>;
582 nvidia,tristat 582 nvidia,tristate = <TEGRA_PIN_DISABLE>;
583 nvidia,enable- 583 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
584 }; 584 };
585 gpio_w3_aud_pw3 { 585 gpio_w3_aud_pw3 {
586 nvidia,pins = 586 nvidia,pins = "gpio_w3_aud_pw3";
587 nvidia,functio 587 nvidia,function = "spi6";
588 nvidia,pull = 588 nvidia,pull = <TEGRA_PIN_PULL_UP>;
589 nvidia,tristat 589 nvidia,tristate = <TEGRA_PIN_DISABLE>;
590 nvidia,enable- 590 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
591 }; 591 };
592 dap3_fs_pp0 { 592 dap3_fs_pp0 {
593 nvidia,pins = 593 nvidia,pins = "dap3_fs_pp0",
594 594 "dap3_din_pp1",
595 595 "dap3_dout_pp2",
596 596 "dap3_sclk_pp3";
597 nvidia,functio 597 nvidia,function = "i2s2";
598 nvidia,pull = 598 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
599 nvidia,tristat 599 nvidia,tristate = <TEGRA_PIN_DISABLE>;
600 nvidia,enable- 600 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
601 }; 601 };
602 pv0 { 602 pv0 {
603 nvidia,pins = 603 nvidia,pins = "pv0";
604 nvidia,functio 604 nvidia,function = "rsvd4";
605 nvidia,pull = 605 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606 nvidia,tristat 606 nvidia,tristate = <TEGRA_PIN_DISABLE>;
607 nvidia,enable- 607 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
608 }; 608 };
609 pv1 { 609 pv1 {
610 nvidia,pins = 610 nvidia,pins = "pv1";
611 nvidia,functio 611 nvidia,function = "rsvd1";
612 nvidia,pull = 612 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613 nvidia,tristat 613 nvidia,tristate = <TEGRA_PIN_DISABLE>;
614 nvidia,enable- 614 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615 }; 615 };
616 pbb3 { 616 pbb3 {
617 nvidia,pins = 617 nvidia,pins = "pbb3",
618 618 "pbb5",
619 619 "pbb6",
620 620 "pbb7";
621 nvidia,functio 621 nvidia,function = "rsvd4";
622 nvidia,pull = 622 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
623 nvidia,tristat 623 nvidia,tristate = <TEGRA_PIN_DISABLE>;
624 nvidia,enable- 624 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
625 }; 625 };
626 pcc1 { 626 pcc1 {
627 nvidia,pins = 627 nvidia,pins = "pcc1",
628 628 "pcc2";
629 nvidia,functio 629 nvidia,function = "rsvd4";
630 nvidia,pull = 630 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
631 nvidia,tristat 631 nvidia,tristate = <TEGRA_PIN_DISABLE>;
632 nvidia,enable- 632 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
633 }; 633 };
634 gmi_ad0_pg0 { 634 gmi_ad0_pg0 {
635 nvidia,pins = 635 nvidia,pins = "gmi_ad0_pg0",
636 636 "gmi_ad1_pg1";
637 nvidia,functio 637 nvidia,function = "gmi";
638 nvidia,pull = 638 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
639 nvidia,tristat 639 nvidia,tristate = <TEGRA_PIN_DISABLE>;
640 nvidia,enable- 640 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
641 }; 641 };
642 gmi_ad10_ph2 { 642 gmi_ad10_ph2 {
643 nvidia,pins = 643 nvidia,pins = "gmi_ad10_ph2",
644 644 "gmi_ad12_ph4",
645 645 "gmi_ad15_ph7",
646 646 "gmi_cs3_n_pk4";
647 nvidia,functio 647 nvidia,function = "gmi";
648 nvidia,pull = 648 nvidia,pull = <TEGRA_PIN_PULL_UP>;
649 nvidia,tristat 649 nvidia,tristate = <TEGRA_PIN_DISABLE>;
650 nvidia,enable- 650 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651 }; 651 };
652 gmi_ad11_ph3 { 652 gmi_ad11_ph3 {
653 nvidia,pins = 653 nvidia,pins = "gmi_ad11_ph3",
654 654 "gmi_ad13_ph5",
655 655 "gmi_ad8_ph0",
656 656 "gmi_clk_pk1",
657 657 "gmi_cs2_n_pk3";
658 nvidia,functio 658 nvidia,function = "gmi";
659 nvidia,pull = 659 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
660 nvidia,tristat 660 nvidia,tristate = <TEGRA_PIN_DISABLE>;
661 nvidia,enable- 661 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
662 }; 662 };
663 gmi_ad14_ph6 { 663 gmi_ad14_ph6 {
664 nvidia,pins = 664 nvidia,pins = "gmi_ad14_ph6",
665 665 "gmi_cs0_n_pj0",
666 666 "gmi_cs4_n_pk2",
667 667 "gmi_cs7_n_pi6",
668 668 "gmi_dqs_p_pj3",
669 669 "gmi_wp_n_pc7";
670 nvidia,functio 670 nvidia,function = "gmi";
671 nvidia,pull = 671 nvidia,pull = <TEGRA_PIN_PULL_UP>;
672 nvidia,tristat 672 nvidia,tristate = <TEGRA_PIN_DISABLE>;
673 nvidia,enable- 673 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
674 }; 674 };
675 gmi_ad2_pg2 { 675 gmi_ad2_pg2 {
676 nvidia,pins = 676 nvidia,pins = "gmi_ad2_pg2",
677 677 "gmi_ad3_pg3";
678 nvidia,functio 678 nvidia,function = "gmi";
679 nvidia,pull = 679 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
680 nvidia,tristat 680 nvidia,tristate = <TEGRA_PIN_DISABLE>;
681 nvidia,enable- 681 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
682 }; 682 };
683 sdmmc1_wp_n_pv3 { 683 sdmmc1_wp_n_pv3 {
684 nvidia,pins = 684 nvidia,pins = "sdmmc1_wp_n_pv3";
685 nvidia,functio 685 nvidia,function = "spi4";
686 nvidia,pull = 686 nvidia,pull = <TEGRA_PIN_PULL_UP>;
687 nvidia,tristat 687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
688 nvidia,enable- 688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689 }; 689 };
690 clk2_req_pcc5 { 690 clk2_req_pcc5 {
691 nvidia,pins = 691 nvidia,pins = "clk2_req_pcc5";
692 nvidia,functio 692 nvidia,function = "rsvd4";
693 nvidia,pull = 693 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
694 nvidia,tristat 694 nvidia,tristate = <TEGRA_PIN_DISABLE>;
695 nvidia,enable- 695 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
696 }; 696 };
697 kb_col3_pq3 { 697 kb_col3_pq3 {
698 nvidia,pins = 698 nvidia,pins = "kb_col3_pq3";
699 nvidia,functio 699 nvidia,function = "pwm2";
700 nvidia,pull = 700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701 nvidia,tristat 701 nvidia,tristate = <TEGRA_PIN_DISABLE>;
702 nvidia,enable- 702 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703 }; 703 };
704 kb_col5_pq5 { 704 kb_col5_pq5 {
705 nvidia,pins = 705 nvidia,pins = "kb_col5_pq5";
706 nvidia,functio 706 nvidia,function = "kbc";
707 nvidia,pull = 707 nvidia,pull = <TEGRA_PIN_PULL_UP>;
708 nvidia,tristat 708 nvidia,tristate = <TEGRA_PIN_DISABLE>;
709 nvidia,enable- 709 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710 }; 710 };
711 kb_col6_pq6 { 711 kb_col6_pq6 {
712 nvidia,pins = 712 nvidia,pins = "kb_col6_pq6",
713 713 "kb_col7_pq7";
714 nvidia,functio 714 nvidia,function = "kbc";
715 nvidia,pull = 715 nvidia,pull = <TEGRA_PIN_PULL_UP>;
716 nvidia,tristat 716 nvidia,tristate = <TEGRA_PIN_DISABLE>;
717 nvidia,enable- 717 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
718 }; 718 };
719 kb_row3_pr3 { 719 kb_row3_pr3 {
720 nvidia,pins = 720 nvidia,pins = "kb_row3_pr3",
721 721 "kb_row4_pr4",
722 722 "kb_row6_pr6";
723 nvidia,functio 723 nvidia,function = "kbc";
724 nvidia,pull = 724 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
725 nvidia,tristat 725 nvidia,tristate = <TEGRA_PIN_DISABLE>;
726 nvidia,enable- 726 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
727 }; 727 };
728 clk3_req_pee1 { 728 clk3_req_pee1 {
729 nvidia,pins = 729 nvidia,pins = "clk3_req_pee1";
730 nvidia,functio 730 nvidia,function = "rsvd4";
731 nvidia,pull = 731 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
732 nvidia,tristat 732 nvidia,tristate = <TEGRA_PIN_DISABLE>;
733 nvidia,enable- 733 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
734 }; 734 };
735 pu2 { 735 pu2 {
736 nvidia,pins = 736 nvidia,pins = "pu2";
737 nvidia,functio 737 nvidia,function = "rsvd1";
738 nvidia,pull = 738 nvidia,pull = <TEGRA_PIN_PULL_UP>;
739 nvidia,tristat 739 nvidia,tristate = <TEGRA_PIN_DISABLE>;
740 nvidia,enable- 740 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741 }; 741 };
742 hdmi_int_pn7 { 742 hdmi_int_pn7 {
743 nvidia,pins = 743 nvidia,pins = "hdmi_int_pn7";
744 nvidia,functio 744 nvidia,function = "rsvd1";
745 nvidia,pull = 745 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
746 nvidia,tristat 746 nvidia,tristate = <TEGRA_PIN_DISABLE>;
747 nvidia,enable- 747 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
748 }; 748 };
749 749
750 drive_sdio1 { 750 drive_sdio1 {
751 nvidia,pins = 751 nvidia,pins = "drive_sdio1";
752 nvidia,high-sp 752 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
753 nvidia,schmitt 753 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
754 nvidia,pull-do 754 nvidia,pull-down-strength = <36>;
755 nvidia,pull-up 755 nvidia,pull-up-strength = <20>;
756 nvidia,slew-ra 756 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
757 nvidia,slew-ra 757 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
758 }; 758 };
759 drive_sdio3 { 759 drive_sdio3 {
760 nvidia,pins = 760 nvidia,pins = "drive_sdio3";
761 nvidia,high-sp 761 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
762 nvidia,schmitt 762 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
763 nvidia,pull-do 763 nvidia,pull-down-strength = <36>;
764 nvidia,pull-up 764 nvidia,pull-up-strength = <20>;
765 nvidia,slew-ra 765 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
766 nvidia,slew-ra 766 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
767 }; 767 };
768 drive_gma { 768 drive_gma {
769 nvidia,pins = 769 nvidia,pins = "drive_gma";
770 nvidia,high-sp 770 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
771 nvidia,schmitt 771 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
772 nvidia,pull-do 772 nvidia,pull-down-strength = <2>;
773 nvidia,pull-up 773 nvidia,pull-up-strength = <2>;
774 nvidia,slew-ra 774 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
775 nvidia,slew-ra 775 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
776 }; 776 };
777 }; 777 };
778 }; 778 };
779 779
780 /* Usable on reworked devices only */ 780 /* Usable on reworked devices only */
781 serial@70006300 { 781 serial@70006300 {
782 /delete-property/ dmas; 782 /delete-property/ dmas;
783 /delete-property/ dma-names; 783 /delete-property/ dma-names;
784 status = "okay"; 784 status = "okay";
785 }; 785 };
786 786
787 pwm@7000a000 { 787 pwm@7000a000 {
788 status = "okay"; 788 status = "okay";
789 }; 789 };
790 790
791 i2c@7000d000 { 791 i2c@7000d000 {
792 status = "okay"; 792 status = "okay";
793 clock-frequency = <400000>; 793 clock-frequency = <400000>;
794 794
795 regulator@43 { 795 regulator@43 {
796 compatible = "ti,tps51 796 compatible = "ti,tps51632";
797 reg = <0x43>; 797 reg = <0x43>;
798 regulator-name = "vdd- 798 regulator-name = "vdd-cpu";
799 regulator-min-microvol 799 regulator-min-microvolt = <500000>;
800 regulator-max-microvol 800 regulator-max-microvolt = <1520000>;
801 regulator-always-on; 801 regulator-always-on;
802 regulator-boot-on; 802 regulator-boot-on;
803 }; 803 };
804 804
805 palmas: pmic@58 { 805 palmas: pmic@58 {
806 compatible = "ti,tps65 806 compatible = "ti,tps65913", "ti,palmas";
807 reg = <0x58>; 807 reg = <0x58>;
808 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
809 809
810 #interrupt-cells = <2> 810 #interrupt-cells = <2>;
811 interrupt-controller; 811 interrupt-controller;
812 812
813 ti,system-power-contro 813 ti,system-power-controller;
814 814
815 palmas_gpio: gpio { 815 palmas_gpio: gpio {
816 compatible = " 816 compatible = "ti,palmas-gpio";
817 gpio-controlle 817 gpio-controller;
818 #gpio-cells = 818 #gpio-cells = <2>;
819 }; 819 };
820 820
821 pmic { 821 pmic {
822 compatible = " 822 compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
823 823
824 regulators { 824 regulators {
825 smps12 825 smps12 {
826 826 regulator-name = "vdd-ddr";
827 827 regulator-min-microvolt = <1200000>;
828 828 regulator-max-microvolt = <1500000>;
829 829 regulator-always-on;
830 830 regulator-boot-on;
831 }; 831 };
832 832
833 vdd_1v 833 vdd_1v8: smps3 {
834 834 regulator-name = "vdd-1v8";
835 835 regulator-min-microvolt = <1800000>;
836 836 regulator-max-microvolt = <1800000>;
837 837 regulator-boot-on;
838 }; 838 };
839 839
840 smps45 840 smps457 {
841 841 regulator-name = "vdd-soc";
842 842 regulator-min-microvolt = <900000>;
843 843 regulator-max-microvolt = <1400000>;
844 844 regulator-always-on;
845 845 regulator-boot-on;
846 }; 846 };
847 847
848 smps8 848 smps8 {
849 849 regulator-name = "avdd-pll-1v05";
850 850 regulator-min-microvolt = <1050000>;
851 851 regulator-max-microvolt = <1050000>;
852 852 regulator-always-on;
853 853 regulator-boot-on;
854 }; 854 };
855 855
856 smps9 856 smps9 {
857 857 regulator-name = "vdd-2v85-emmc";
858 858 regulator-min-microvolt = <2800000>;
859 859 regulator-max-microvolt = <2800000>;
860 860 regulator-always-on;
861 }; 861 };
862 862
863 smps10 863 smps10_out1 {
864 864 regulator-name = "vdd-fan";
865 865 regulator-min-microvolt = <5000000>;
866 866 regulator-max-microvolt = <5000000>;
867 867 regulator-always-on;
868 868 regulator-boot-on;
869 }; 869 };
870 870
871 smps10 871 smps10_out2 {
872 872 regulator-name = "vdd-5v0-sys";
873 873 regulator-min-microvolt = <5000000>;
874 874 regulator-max-microvolt = <5000000>;
875 875 regulator-always-on;
876 876 regulator-boot-on;
877 }; 877 };
878 878
879 ldo2 { 879 ldo2 {
880 880 regulator-name = "vdd-2v8-display";
881 881 regulator-min-microvolt = <2800000>;
882 882 regulator-max-microvolt = <2800000>;
883 883 regulator-always-on;
884 884 regulator-boot-on;
885 }; 885 };
886 886
887 vdd_1v 887 vdd_1v2_ap: ldo3 {
888 888 regulator-name = "avdd-1v2";
889 889 regulator-min-microvolt = <1200000>;
890 890 regulator-max-microvolt = <1200000>;
891 891 regulator-always-on;
892 892 regulator-boot-on;
893 }; 893 };
894 894
895 ldo4 { 895 ldo4 {
896 896 regulator-name = "vpp-fuse";
897 897 regulator-min-microvolt = <1800000>;
898 898 regulator-max-microvolt = <1800000>;
899 }; 899 };
900 900
901 ldo5 { 901 ldo5 {
902 902 regulator-name = "avdd-hdmi-pll";
903 903 regulator-min-microvolt = <1200000>;
904 904 regulator-max-microvolt = <1200000>;
905 }; 905 };
906 906
907 ldo6 { 907 ldo6 {
908 908 regulator-name = "vdd-sensor-2v8";
909 909 regulator-min-microvolt = <2850000>;
910 910 regulator-max-microvolt = <2850000>;
911 }; 911 };
912 912
913 ldo8 { 913 ldo8 {
914 914 regulator-name = "vdd-rtc";
915 915 regulator-min-microvolt = <1100000>;
916 916 regulator-max-microvolt = <1100000>;
917 917 regulator-always-on;
918 918 regulator-boot-on;
919 919 ti,enable-ldo8-tracking;
920 }; 920 };
921 921
922 vddio_ 922 vddio_sdmmc3: ldo9 {
923 923 regulator-name = "vddio-sdmmc3";
924 924 regulator-min-microvolt = <1800000>;
925 925 regulator-max-microvolt = <3300000>;
926 }; 926 };
927 927
928 ldousb 928 ldousb {
929 929 regulator-name = "avdd-usb-hdmi";
930 930 regulator-min-microvolt = <3300000>;
931 931 regulator-max-microvolt = <3300000>;
932 932 regulator-always-on;
933 933 regulator-boot-on;
934 }; 934 };
935 935
936 vdd_3v 936 vdd_3v3_sys: regen1 {
937 937 regulator-name = "rail-3v3";
938 938 regulator-max-microvolt = <3300000>;
939 939 regulator-always-on;
940 940 regulator-boot-on;
941 }; 941 };
942 942
943 regen2 943 regen2 {
944 944 regulator-name = "rail-5v0";
945 945 regulator-max-microvolt = <5000000>;
946 946 regulator-always-on;
947 947 regulator-boot-on;
948 }; 948 };
949 949
950 }; 950 };
951 }; 951 };
952 952
953 rtc { 953 rtc {
954 compatible = " 954 compatible = "ti,palmas-rtc";
955 interrupt-pare 955 interrupt-parent = <&palmas>;
956 interrupts = < 956 interrupts = <8 0>;
957 }; 957 };
958 958
959 }; 959 };
960 }; 960 };
961 961
962 pmc@7000e400 { 962 pmc@7000e400 {
963 nvidia,invert-interrupt; 963 nvidia,invert-interrupt;
964 }; 964 };
965 965
966 /* SD card */ 966 /* SD card */
967 mmc@78000400 { 967 mmc@78000400 {
968 status = "okay"; 968 status = "okay";
969 bus-width = <4>; 969 bus-width = <4>;
970 vqmmc-supply = <&vddio_sdmmc3> 970 vqmmc-supply = <&vddio_sdmmc3>;
971 cd-gpios = <&gpio TEGRA_GPIO(V 971 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
972 power-gpios = <&gpio TEGRA_GPI 972 power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
973 }; 973 };
974 974
975 /* eMMC */ 975 /* eMMC */
976 mmc@78000600 { 976 mmc@78000600 {
977 status = "okay"; 977 status = "okay";
978 bus-width = <8>; 978 bus-width = <8>;
979 non-removable; 979 non-removable;
980 }; 980 };
981 981
982 /* External USB port (must be powered) 982 /* External USB port (must be powered) */
983 usb@7d000000 { 983 usb@7d000000 {
984 status = "okay"; 984 status = "okay";
985 }; 985 };
986 986
987 usb-phy@7d000000 { 987 usb-phy@7d000000 {
988 status = "okay"; 988 status = "okay";
989 nvidia,xcvr-setup = <7>; 989 nvidia,xcvr-setup = <7>;
990 nvidia,xcvr-lsfslew = <2>; 990 nvidia,xcvr-lsfslew = <2>;
991 nvidia,xcvr-lsrslew = <2>; 991 nvidia,xcvr-lsrslew = <2>;
992 interrupts = <GIC_SPI 20 IRQ_T 992 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
993 /* Should be changed to "otg" 993 /* Should be changed to "otg" once we have vbus_supply */
994 /* As of now, USB devices need 994 /* As of now, USB devices need to be powered externally */
995 dr_mode = "host"; 995 dr_mode = "host";
996 }; 996 };
997 997
998 /* SHIELD controller */ 998 /* SHIELD controller */
999 usb@7d008000 { 999 usb@7d008000 {
1000 status = "okay"; 1000 status = "okay";
1001 }; 1001 };
1002 1002
1003 usb-phy@7d008000 { 1003 usb-phy@7d008000 {
1004 status = "okay"; 1004 status = "okay";
1005 nvidia,xcvr-setup = <7>; 1005 nvidia,xcvr-setup = <7>;
1006 nvidia,xcvr-lsfslew = <2>; 1006 nvidia,xcvr-lsfslew = <2>;
1007 nvidia,xcvr-lsrslew = <2>; 1007 nvidia,xcvr-lsrslew = <2>;
1008 }; 1008 };
1009 1009
1010 backlight: backlight { 1010 backlight: backlight {
1011 compatible = "pwm-backlight"; 1011 compatible = "pwm-backlight";
1012 pwms = <&pwm 1 40000>; 1012 pwms = <&pwm 1 40000>;
1013 1013
1014 brightness-levels = <0 4 8 16 1014 brightness-levels = <0 4 8 16 32 64 128 255>;
1015 default-brightness-level = <6 1015 default-brightness-level = <6>;
1016 1016
1017 power-supply = <&lcd_bl_en>; 1017 power-supply = <&lcd_bl_en>;
1018 enable-gpios = <&gpio TEGRA_G 1018 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1019 }; 1019 };
1020 1020
1021 clk32k_in: clock-32k { 1021 clk32k_in: clock-32k {
1022 compatible = "fixed-clock"; 1022 compatible = "fixed-clock";
1023 clock-frequency = <32768>; 1023 clock-frequency = <32768>;
1024 #clock-cells = <0>; 1024 #clock-cells = <0>;
1025 }; 1025 };
1026 1026
1027 gpio-keys { 1027 gpio-keys {
1028 compatible = "gpio-keys"; 1028 compatible = "gpio-keys";
1029 1029
1030 key-back { 1030 key-back {
1031 label = "Back"; 1031 label = "Back";
1032 gpios = <&gpio TEGRA_ 1032 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1033 linux,code = <KEY_BAC 1033 linux,code = <KEY_BACK>;
1034 }; 1034 };
1035 1035
1036 key-home { 1036 key-home {
1037 label = "Home"; 1037 label = "Home";
1038 gpios = <&gpio TEGRA_ 1038 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1039 linux,code = <KEY_HOM 1039 linux,code = <KEY_HOME>;
1040 }; 1040 };
1041 1041
1042 key-power { 1042 key-power {
1043 label = "Power"; 1043 label = "Power";
1044 gpios = <&gpio TEGRA_ 1044 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1045 linux,code = <KEY_POW 1045 linux,code = <KEY_POWER>;
1046 wakeup-source; 1046 wakeup-source;
1047 }; 1047 };
1048 }; 1048 };
1049 1049
1050 lcd_bl_en: regulator-lcden { 1050 lcd_bl_en: regulator-lcden {
1051 compatible = "regulator-fixed 1051 compatible = "regulator-fixed";
1052 regulator-name = "lcd_bl_en"; 1052 regulator-name = "lcd_bl_en";
1053 regulator-min-microvolt = <50 1053 regulator-min-microvolt = <5000000>;
1054 regulator-max-microvolt = <50 1054 regulator-max-microvolt = <5000000>;
1055 regulator-boot-on; 1055 regulator-boot-on;
1056 }; 1056 };
1057 1057
1058 vdd_lcd: regulator-lcd { 1058 vdd_lcd: regulator-lcd {
1059 compatible = "regulator-fixed 1059 compatible = "regulator-fixed";
1060 regulator-name = "vdd_lcd_1v8 1060 regulator-name = "vdd_lcd_1v8";
1061 regulator-min-microvolt = <18 1061 regulator-min-microvolt = <1800000>;
1062 regulator-max-microvolt = <18 1062 regulator-max-microvolt = <1800000>;
1063 vin-supply = <&vdd_1v8>; 1063 vin-supply = <&vdd_1v8>;
1064 enable-active-high; 1064 enable-active-high;
1065 gpio = <&gpio TEGRA_GPIO(U, 4 1065 gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
1066 regulator-boot-on; 1066 regulator-boot-on;
1067 }; 1067 };
1068 1068
1069 regulator-1v8ts { 1069 regulator-1v8ts {
1070 compatible = "regulator-fixed 1070 compatible = "regulator-fixed";
1071 regulator-name = "vdd_1v8_ts" 1071 regulator-name = "vdd_1v8_ts";
1072 regulator-min-microvolt = <18 1072 regulator-min-microvolt = <1800000>;
1073 regulator-max-microvolt = <18 1073 regulator-max-microvolt = <1800000>;
1074 gpio = <&gpio TEGRA_GPIO(K, 3 1074 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
1075 regulator-boot-on; 1075 regulator-boot-on;
1076 }; 1076 };
1077 1077
1078 regulator-3v3ts { 1078 regulator-3v3ts {
1079 compatible = "regulator-fixed 1079 compatible = "regulator-fixed";
1080 regulator-name = "vdd_3v3_ts" 1080 regulator-name = "vdd_3v3_ts";
1081 regulator-min-microvolt = <33 1081 regulator-min-microvolt = <3300000>;
1082 regulator-max-microvolt = <33 1082 regulator-max-microvolt = <3300000>;
1083 enable-active-high; 1083 enable-active-high;
1084 gpio = <&gpio TEGRA_GPIO(H, 5 1084 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1085 regulator-boot-on; 1085 regulator-boot-on;
1086 }; 1086 };
1087 1087
1088 regulator-1v8com { 1088 regulator-1v8com {
1089 compatible = "regulator-fixed 1089 compatible = "regulator-fixed";
1090 regulator-name = "vdd_1v8_com 1090 regulator-name = "vdd_1v8_com";
1091 regulator-min-microvolt = <18 1091 regulator-min-microvolt = <1800000>;
1092 regulator-max-microvolt = <18 1092 regulator-max-microvolt = <1800000>;
1093 vin-supply = <&vdd_1v8>; 1093 vin-supply = <&vdd_1v8>;
1094 enable-active-high; 1094 enable-active-high;
1095 gpio = <&gpio TEGRA_GPIO(X, 1 1095 gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
1096 regulator-boot-on; 1096 regulator-boot-on;
1097 }; 1097 };
1098 1098
1099 regulator-3v3com { 1099 regulator-3v3com {
1100 compatible = "regulator-fixed 1100 compatible = "regulator-fixed";
1101 regulator-name = "vdd_3v3_com 1101 regulator-name = "vdd_3v3_com";
1102 regulator-min-microvolt = <33 1102 regulator-min-microvolt = <3300000>;
1103 regulator-max-microvolt = <33 1103 regulator-max-microvolt = <3300000>;
1104 vin-supply = <&vdd_3v3_sys>; 1104 vin-supply = <&vdd_3v3_sys>;
1105 enable-active-high; 1105 enable-active-high;
1106 gpio = <&gpio TEGRA_GPIO(X, 7 1106 gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1107 regulator-always-on; 1107 regulator-always-on;
1108 regulator-boot-on; 1108 regulator-boot-on;
1109 }; 1109 };
1110 }; 1110 };
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