1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi" 2 #include "tegra20.dtsi"
3 3
4 /* 4 /*
5 * Toradex Colibri T20 Module Device Tree 5 * Toradex Colibri T20 Module Device Tree
6 * Compatible for Revisions Colibri T20 256MB 6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512 7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A 8 * Colibri T20 512MB IT V1.2A
9 */ 9 */
10 / { 10 / {
11 memory@0 { 11 memory@0 {
12 /* 12 /*
13 * Set memory to 256 MB to be 13 * Set memory to 256 MB to be safe as this could be used on
14 * 256 or 512 MB module. It is 14 * 256 or 512 MB module. It is expected from bootloader
15 * to fix this up for 512 MB v 15 * to fix this up for 512 MB version.
16 */ 16 */
17 reg = <0x00000000 0x10000000>; 17 reg = <0x00000000 0x10000000>;
18 }; 18 };
19 19
20 host1x@50000000 { 20 host1x@50000000 {
21 hdmi@54280000 { 21 hdmi@54280000 {
22 nvidia,ddc-i2c-bus = < 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio = 23 nvidia,hpd-gpio =
24 <&gpio TEGRA_G 24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
25 pll-supply = <®_1v8 25 pll-supply = <®_1v8_avdd_hdmi_pll>;
26 vdd-supply = <®_3v3 26 vdd-supply = <®_3v3_avdd_hdmi>;
27 }; 27 };
28 }; 28 };
29 29
30 gpio@6000d000 { 30 gpio@6000d000 {
31 lan-reset-n-hog { 31 lan-reset-n-hog {
32 gpio-hog; 32 gpio-hog;
33 gpios = <TEGRA_GPIO(V, 33 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
34 output-high; 34 output-high;
35 line-name = "LAN_RESET 35 line-name = "LAN_RESET#";
36 }; 36 };
37 37
38 /* Tri-stating GMI_WR_N on SOD 38 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
39 npwe-hog { 39 npwe-hog {
40 gpio-hog; 40 gpio-hog;
41 gpios = <TEGRA_GPIO(T, 41 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
42 output-high; 42 output-high;
43 line-name = "Tri-state 43 line-name = "Tri-state nPWE";
44 }; 44 };
45 45
46 /* Not tri-stating GMI_WR_N on 46 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
47 rdnwr-hog { 47 rdnwr-hog {
48 gpio-hog; 48 gpio-hog;
49 gpios = <TEGRA_GPIO(T, 49 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
50 output-low; 50 output-low;
51 line-name = "Not tri-s 51 line-name = "Not tri-state RDnWR";
52 }; 52 };
53 }; 53 };
54 54
55 pinmux@70000014 { 55 pinmux@70000014 {
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
57 pinctrl-0 = <&state_default>; 57 pinctrl-0 = <&state_default>;
58 58
59 state_default: pinmux { 59 state_default: pinmux {
60 /* Analogue Audio AC97 60 /* Analogue Audio AC97 to WM9712 (On-module) */
61 audio-refclk { 61 audio-refclk {
62 nvidia,pins = 62 nvidia,pins = "cdev1";
63 nvidia,functio 63 nvidia,function = "plla_out";
64 nvidia,pull = 64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristat 65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 }; 66 };
67 dap3 { 67 dap3 {
68 nvidia,pins = 68 nvidia,pins = "dap3";
69 nvidia,functio 69 nvidia,function = "dap3";
70 nvidia,pull = 70 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
71 nvidia,tristat 71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 }; 72 };
73 73
74 /* 74 /*
75 * AC97_RESET, ULPI_RE 75 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
76 * (All on-module), SO 76 * (All on-module), SODIMM Pin 45 Wakeup
77 */ 77 */
78 gpio-uac { 78 gpio-uac {
79 nvidia,pins = 79 nvidia,pins = "uac";
80 nvidia,functio 80 nvidia,function = "rsvd2";
81 nvidia,pull = 81 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
82 nvidia,tristat 82 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 }; 83 };
84 84
85 /* 85 /*
86 * Buffer Enables for 86 * Buffer Enables for nPWE and RDnWR (On-module,
87 * see GPIO hogging fu 87 * see GPIO hogging further down below)
88 */ 88 */
89 gpio-pta { 89 gpio-pta {
90 nvidia,pins = 90 nvidia,pins = "pta";
91 nvidia,functio 91 nvidia,function = "rsvd4";
92 nvidia,pull = 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristat 93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 }; 94 };
95 95
96 /* 96 /*
97 * CLK_32K_OUT, CORE_P 97 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
98 * SYS_CLK_REQ (All on 98 * SYS_CLK_REQ (All on-module)
99 */ 99 */
100 pmc { 100 pmc {
101 nvidia,pins = 101 nvidia,pins = "pmc";
102 nvidia,functio 102 nvidia,function = "pwr_on";
103 nvidia,tristat 103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 }; 104 };
105 105
106 /* 106 /*
107 * Colibri Address/Dat 107 * Colibri Address/Data Bus (GMI)
108 * Note: spid and spie 108 * Note: spid and spie optionally used for SPI1
109 */ 109 */
110 gmi { 110 gmi {
111 nvidia,pins = 111 nvidia,pins = "atc", "atd", "ate", "dap1",
112 112 "dap2", "dap4", "gmd", "gpu",
113 113 "irrx", "irtx", "spia", "spib",
114 114 "spic", "spid", "spie", "uca",
115 115 "ucb";
116 nvidia,functio 116 nvidia,function = "gmi";
117 nvidia,pull = 117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristat 118 nvidia,tristate = <TEGRA_PIN_ENABLE>;
119 }; 119 };
120 /* Further pins may be 120 /* Further pins may be used as GPIOs */
121 gmi-gpio1 { 121 gmi-gpio1 {
122 nvidia,pins = 122 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
123 nvidia,functio 123 nvidia,function = "hdmi";
124 nvidia,tristat 124 nvidia,tristate = <TEGRA_PIN_ENABLE>;
125 }; 125 };
126 gmi-gpio2 { 126 gmi-gpio2 {
127 nvidia,pins = 127 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
128 nvidia,functio 128 nvidia,function = "rsvd4";
129 nvidia,tristat 129 nvidia,tristate = <TEGRA_PIN_ENABLE>;
130 }; 130 };
131 131
132 /* Colibri BL_ON */ 132 /* Colibri BL_ON */
133 bl-on { 133 bl-on {
134 nvidia,pins = 134 nvidia,pins = "dta";
135 nvidia,functio 135 nvidia,function = "rsvd1";
136 nvidia,pull = 136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristat 137 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 }; 138 };
139 139
140 /* Colibri Backlight P 140 /* Colibri Backlight PWM<A>, PWM<B> */
141 sdc { 141 sdc {
142 nvidia,pins = 142 nvidia,pins = "sdc";
143 nvidia,functio 143 nvidia,function = "pwm";
144 nvidia,tristat 144 nvidia,tristate = <TEGRA_PIN_ENABLE>;
145 }; 145 };
146 146
147 /* Colibri DDC */ 147 /* Colibri DDC */
148 ddc { 148 ddc {
149 nvidia,pins = 149 nvidia,pins = "ddc";
150 nvidia,functio 150 nvidia,function = "i2c2";
151 nvidia,pull = 151 nvidia,pull = <TEGRA_PIN_PULL_UP>;
152 nvidia,tristat 152 nvidia,tristate = <TEGRA_PIN_ENABLE>;
153 }; 153 };
154 154
155 /* 155 /*
156 * Colibri EXT_IO* 156 * Colibri EXT_IO*
157 * Note: dtf optionall 157 * Note: dtf optionally used for I2C3
158 */ 158 */
159 ext-io { 159 ext-io {
160 nvidia,pins = 160 nvidia,pins = "dtf", "spdi";
161 nvidia,functio 161 nvidia,function = "rsvd2";
162 nvidia,pull = 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163 nvidia,tristat 163 nvidia,tristate = <TEGRA_PIN_ENABLE>;
164 }; 164 };
165 165
166 /* 166 /*
167 * Colibri Ethernet (O 167 * Colibri Ethernet (On-module)
168 * ULPI EHCI instance 168 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
169 */ 169 */
170 ulpi { 170 ulpi {
171 nvidia,pins = 171 nvidia,pins = "uaa", "uab", "uda";
172 nvidia,functio 172 nvidia,function = "ulpi";
173 nvidia,pull = 173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristat 174 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 }; 175 };
176 ulpi-refclk { 176 ulpi-refclk {
177 nvidia,pins = 177 nvidia,pins = "cdev2";
178 nvidia,functio 178 nvidia,function = "pllp_out4";
179 nvidia,pull = 179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristat 180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 }; 181 };
182 182
183 /* Colibri HOTPLUG_DET 183 /* Colibri HOTPLUG_DETECT (HDMI) */
184 hotplug-detect { 184 hotplug-detect {
185 nvidia,pins = 185 nvidia,pins = "hdint";
186 nvidia,functio 186 nvidia,function = "hdmi";
187 nvidia,tristat 187 nvidia,tristate = <TEGRA_PIN_ENABLE>;
188 }; 188 };
189 189
190 /* Colibri I2C */ 190 /* Colibri I2C */
191 i2c { 191 i2c {
192 nvidia,pins = 192 nvidia,pins = "rm";
193 nvidia,functio 193 nvidia,function = "i2c1";
194 nvidia,pull = 194 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristat 195 nvidia,tristate = <TEGRA_PIN_ENABLE>;
196 }; 196 };
197 197
198 /* 198 /*
199 * Colibri L_BIAS, LCD 199 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
200 * today's display nee 200 * today's display need DE, disable LCD_M1
201 */ 201 */
202 lm1 { 202 lm1 {
203 nvidia,pins = 203 nvidia,pins = "lm1";
204 nvidia,functio 204 nvidia,function = "rsvd3";
205 nvidia,tristat 205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
206 }; 206 };
207 207
208 /* Colibri LCD (L_* re 208 /* Colibri LCD (L_* resp. LDD<*>) */
209 lcd { 209 lcd {
210 nvidia,pins = 210 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
211 211 "ld4", "ld5", "ld6", "ld7",
212 212 "ld8", "ld9", "ld10", "ld11",
213 213 "ld12", "ld13", "ld14", "ld15",
214 214 "ld16", "ld17", "lhs", "lsc0",
215 215 "lspi", "lvs";
216 nvidia,functio 216 nvidia,function = "displaya";
217 nvidia,tristat 217 nvidia,tristate = <TEGRA_PIN_ENABLE>;
218 }; 218 };
219 /* Colibri LCD (Option 219 /* Colibri LCD (Optional 24 BPP Support) */
220 lcd-24 { 220 lcd-24 {
221 nvidia,pins = 221 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
222 222 "lpp", "lvp1";
223 nvidia,functio 223 nvidia,function = "displaya";
224 nvidia,tristat 224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 }; 225 };
226 226
227 /* Colibri MMC */ 227 /* Colibri MMC */
228 mmc { 228 mmc {
229 nvidia,pins = 229 nvidia,pins = "atb", "gma";
230 nvidia,functio 230 nvidia,function = "sdio4";
231 nvidia,pull = 231 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristat 232 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 }; 233 };
234 234
235 /* Colibri MMCCD */ 235 /* Colibri MMCCD */
236 mmccd { 236 mmccd {
237 nvidia,pins = 237 nvidia,pins = "gmb";
238 nvidia,functio 238 nvidia,function = "gmi_int";
239 nvidia,pull = 239 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
240 nvidia,tristat 240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
241 }; 241 };
242 242
243 /* Colibri MMC (Option 243 /* Colibri MMC (Optional 8-bit) */
244 mmc-8bit { 244 mmc-8bit {
245 nvidia,pins = 245 nvidia,pins = "gme";
246 nvidia,functio 246 nvidia,function = "sdio4";
247 nvidia,pull = 247 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
248 nvidia,tristat 248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
249 }; 249 };
250 250
251 /* 251 /*
252 * Colibri Parallel Ca 252 * Colibri Parallel Camera (Optional)
253 * pins multiplexed wi 253 * pins multiplexed with others and therefore disabled
254 * Note: dta used for 254 * Note: dta used for BL_ON by default
255 */ 255 */
256 cif-mclk { 256 cif-mclk {
257 nvidia,pins = 257 nvidia,pins = "csus";
258 nvidia,functio 258 nvidia,function = "vi_sensor_clk";
259 nvidia,pull = 259 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260 nvidia,tristat 260 nvidia,tristate = <TEGRA_PIN_ENABLE>;
261 }; 261 };
262 cif { 262 cif {
263 nvidia,pins = 263 nvidia,pins = "dtb", "dtc", "dtd";
264 nvidia,functio 264 nvidia,function = "vi";
265 nvidia,pull = 265 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
266 nvidia,tristat 266 nvidia,tristate = <TEGRA_PIN_ENABLE>;
267 }; 267 };
268 268
269 /* Colibri PWM<C>, PWM 269 /* Colibri PWM<C>, PWM<D> */
270 sdb_sdd { 270 sdb_sdd {
271 nvidia,pins = 271 nvidia,pins = "sdb", "sdd";
272 nvidia,functio 272 nvidia,function = "pwm";
273 nvidia,tristat 273 nvidia,tristate = <TEGRA_PIN_ENABLE>;
274 }; 274 };
275 275
276 /* Colibri SSP */ 276 /* Colibri SSP */
277 ssp { 277 ssp {
278 nvidia,pins = 278 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
279 nvidia,functio 279 nvidia,function = "spi4";
280 nvidia,pull = 280 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
281 nvidia,tristat 281 nvidia,tristate = <TEGRA_PIN_ENABLE>;
282 }; 282 };
283 283
284 /* Colibri UART-A */ 284 /* Colibri UART-A */
285 uart-a { 285 uart-a {
286 nvidia,pins = 286 nvidia,pins = "sdio1";
287 nvidia,functio 287 nvidia,function = "uarta";
288 nvidia,pull = 288 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
289 nvidia,tristat 289 nvidia,tristate = <TEGRA_PIN_ENABLE>;
290 }; 290 };
291 uart-a-dsr { 291 uart-a-dsr {
292 nvidia,pins = 292 nvidia,pins = "lpw1";
293 nvidia,functio 293 nvidia,function = "rsvd3";
294 nvidia,tristat 294 nvidia,tristate = <TEGRA_PIN_ENABLE>;
295 }; 295 };
296 uart-a-dcd { 296 uart-a-dcd {
297 nvidia,pins = 297 nvidia,pins = "lpw2";
298 nvidia,functio 298 nvidia,function = "hdmi";
299 nvidia,tristat 299 nvidia,tristate = <TEGRA_PIN_ENABLE>;
300 }; 300 };
301 301
302 /* Colibri UART-B */ 302 /* Colibri UART-B */
303 uart-b { 303 uart-b {
304 nvidia,pins = 304 nvidia,pins = "gmc";
305 nvidia,functio 305 nvidia,function = "uartd";
306 nvidia,pull = 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
307 nvidia,tristat 307 nvidia,tristate = <TEGRA_PIN_ENABLE>;
308 }; 308 };
309 309
310 /* Colibri UART-C */ 310 /* Colibri UART-C */
311 uart-c { 311 uart-c {
312 nvidia,pins = 312 nvidia,pins = "uad";
313 nvidia,functio 313 nvidia,function = "irda";
314 nvidia,pull = 314 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
315 nvidia,tristat 315 nvidia,tristate = <TEGRA_PIN_ENABLE>;
316 }; 316 };
317 317
318 /* Colibri USB_CDET */ 318 /* Colibri USB_CDET */
319 usb-cdet { 319 usb-cdet {
320 nvidia,pins = 320 nvidia,pins = "spdo";
321 nvidia,functio 321 nvidia,function = "rsvd2";
322 nvidia,pull = 322 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristat 323 nvidia,tristate = <TEGRA_PIN_ENABLE>;
324 }; 324 };
325 325
326 /* Colibri USBH_OC */ 326 /* Colibri USBH_OC */
327 usbh-oc { 327 usbh-oc {
328 nvidia,pins = 328 nvidia,pins = "spih";
329 nvidia,functio 329 nvidia,function = "spi2_alt";
330 nvidia,pull = 330 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristat 331 nvidia,tristate = <TEGRA_PIN_ENABLE>;
332 }; 332 };
333 333
334 /* Colibri USBH_PEN */ 334 /* Colibri USBH_PEN */
335 usbh-pen { 335 usbh-pen {
336 nvidia,pins = 336 nvidia,pins = "spig";
337 nvidia,functio 337 nvidia,function = "spi2_alt";
338 nvidia,pull = 338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristat 339 nvidia,tristate = <TEGRA_PIN_ENABLE>;
340 }; 340 };
341 341
342 /* Colibri VGA not sup 342 /* Colibri VGA not supported */
343 vga { 343 vga {
344 nvidia,pins = 344 nvidia,pins = "crtp";
345 nvidia,functio 345 nvidia,function = "crt";
346 nvidia,pull = 346 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
347 nvidia,tristat 347 nvidia,tristate = <TEGRA_PIN_ENABLE>;
348 }; 348 };
349 349
350 /* I2C3 (Optional) */ 350 /* I2C3 (Optional) */
351 i2c3 { 351 i2c3 {
352 nvidia,pins = 352 nvidia,pins = "dtf";
353 nvidia,functio 353 nvidia,function = "i2c3";
354 nvidia,pull = 354 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
355 nvidia,tristat 355 nvidia,tristate = <TEGRA_PIN_ENABLE>;
356 }; 356 };
357 357
358 /* JTAG_RTCK */ 358 /* JTAG_RTCK */
359 jtag-rtck { 359 jtag-rtck {
360 nvidia,pins = 360 nvidia,pins = "gpu7";
361 nvidia,functio 361 nvidia,function = "rtck";
362 nvidia,pull = 362 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
363 nvidia,tristat 363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
364 }; 364 };
365 365
366 /* 366 /*
367 * LAN_RESET, LAN_EXT_ 367 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
368 * (All On-module) 368 * (All On-module)
369 */ 369 */
370 gpio-gpv { 370 gpio-gpv {
371 nvidia,pins = 371 nvidia,pins = "gpv";
372 nvidia,functio 372 nvidia,function = "rsvd2";
373 nvidia,pull = 373 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374 nvidia,tristat 374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 }; 375 };
376 376
377 /* 377 /*
378 * LAN_V_BUS, VDD_FAUL 378 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
379 * (All On-module); Co 379 * (All On-module); Colibri CAN_INT
380 */ 380 */
381 gpio-dte { 381 gpio-dte {
382 nvidia,pins = 382 nvidia,pins = "dte";
383 nvidia,functio 383 nvidia,function = "rsvd1";
384 nvidia,pull = 384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristat 385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
386 }; 386 };
387 387
388 /* NAND (On-module) */ 388 /* NAND (On-module) */
389 nand { 389 nand {
390 nvidia,pins = 390 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
391 391 "kbce", "kbcf";
392 nvidia,functio 392 nvidia,function = "nand";
393 nvidia,pull = 393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristat 394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 }; 395 };
396 396
397 /* Onewire (Optional) 397 /* Onewire (Optional) */
398 owr { 398 owr {
399 nvidia,pins = 399 nvidia,pins = "owc";
400 nvidia,functio 400 nvidia,function = "owr";
401 nvidia,pull = 401 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
402 nvidia,tristat 402 nvidia,tristate = <TEGRA_PIN_ENABLE>;
403 }; 403 };
404 404
405 /* Power I2C (On-modul 405 /* Power I2C (On-module) */
406 i2cp { 406 i2cp {
407 nvidia,pins = 407 nvidia,pins = "i2cp";
408 nvidia,functio 408 nvidia,function = "i2cp";
409 nvidia,pull = 409 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
410 nvidia,tristat 410 nvidia,tristate = <TEGRA_PIN_DISABLE>;
411 }; 411 };
412 412
413 /* RESET_OUT */ 413 /* RESET_OUT */
414 reset-out { 414 reset-out {
415 nvidia,pins = 415 nvidia,pins = "ata";
416 nvidia,functio 416 nvidia,function = "gmi";
417 nvidia,pull = 417 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
418 nvidia,tristat 418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 }; 419 };
420 420
421 /* 421 /*
422 * SPI1 (Optional) 422 * SPI1 (Optional)
423 * Note: spid and spie 423 * Note: spid and spie used for Colibri Address/Data
424 * Bus (GMI) 424 * Bus (GMI)
425 */ 425 */
426 spi1 { 426 spi1 {
427 nvidia,pins = 427 nvidia,pins = "spid", "spie", "spif";
428 nvidia,functio 428 nvidia,function = "spi1";
429 nvidia,pull = 429 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
430 nvidia,tristat 430 nvidia,tristate = <TEGRA_PIN_ENABLE>;
431 }; 431 };
432 432
433 /* 433 /*
434 * THERMD_ALERT# (On-m 434 * THERMD_ALERT# (On-module), unlatched I2C address pin
435 * of LM95245 temperat 435 * of LM95245 temperature sensor therefore requires
436 * disabling for now 436 * disabling for now
437 */ 437 */
438 lvp0 { 438 lvp0 {
439 nvidia,pins = 439 nvidia,pins = "lvp0";
440 nvidia,functio 440 nvidia,function = "rsvd3";
441 nvidia,tristat 441 nvidia,tristate = <TEGRA_PIN_ENABLE>;
442 }; 442 };
443 }; 443 };
444 }; 444 };
445 445
446 tegra_ac97: ac97@70002000 { 446 tegra_ac97: ac97@70002000 {
447 status = "okay"; 447 status = "okay";
448 nvidia,codec-reset-gpios = 448 nvidia,codec-reset-gpios =
449 <&gpio TEGRA_GPIO(V, 0 449 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
450 nvidia,codec-sync-gpios = 450 nvidia,codec-sync-gpios =
451 <&gpio TEGRA_GPIO(P, 0 451 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
452 }; 452 };
453 453
454 serial@70006040 { 454 serial@70006040 {
455 compatible = "nvidia,tegra20-h 455 compatible = "nvidia,tegra20-hsuart";
456 reset-names = "serial"; 456 reset-names = "serial";
457 /delete-property/ reg-shift; 457 /delete-property/ reg-shift;
458 }; 458 };
459 459
460 serial@70006300 { 460 serial@70006300 {
461 compatible = "nvidia,tegra20-h 461 compatible = "nvidia,tegra20-hsuart";
462 reset-names = "serial"; 462 reset-names = "serial";
463 /delete-property/ reg-shift; 463 /delete-property/ reg-shift;
464 }; 464 };
465 465
466 nand-controller@70008000 { 466 nand-controller@70008000 {
467 status = "okay"; 467 status = "okay";
468 468
469 nand@0 { 469 nand@0 {
470 reg = <0>; 470 reg = <0>;
471 #address-cells = <1>; 471 #address-cells = <1>;
472 #size-cells = <1>; 472 #size-cells = <1>;
473 nand-bus-width = <8>; 473 nand-bus-width = <8>;
474 nand-on-flash-bbt; 474 nand-on-flash-bbt;
475 nand-ecc-algo = "bch"; 475 nand-ecc-algo = "bch";
476 nand-is-boot-medium; 476 nand-is-boot-medium;
477 nand-ecc-maximize; 477 nand-ecc-maximize;
478 wp-gpios = <&gpio TEGR 478 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
479 }; 479 };
480 }; 480 };
481 481
482 /* 482 /*
483 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 483 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
484 * board) 484 * board)
485 */ 485 */
486 i2c@7000c000 { 486 i2c@7000c000 {
487 clock-frequency = <400000>; 487 clock-frequency = <400000>;
488 }; 488 };
489 489
490 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. d 490 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
491 hdmi_ddc: i2c@7000c400 { 491 hdmi_ddc: i2c@7000c400 {
492 clock-frequency = <10000>; 492 clock-frequency = <10000>;
493 }; 493 };
494 494
495 /* GEN2_I2C: unused */ 495 /* GEN2_I2C: unused */
496 496
497 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPI 497 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
498 498
499 /* PWR_I2C: power I2C to PMIC and temp 499 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
500 i2c@7000d000 { 500 i2c@7000d000 {
501 status = "okay"; 501 status = "okay";
502 clock-frequency = <100000>; 502 clock-frequency = <100000>;
503 503
504 pmic@34 { 504 pmic@34 {
505 compatible = "ti,tps65 505 compatible = "ti,tps6586x";
506 reg = <0x34>; 506 reg = <0x34>;
507 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
508 ti,system-power-contro 508 ti,system-power-controller;
509 #gpio-cells = <2>; 509 #gpio-cells = <2>;
510 gpio-controller; 510 gpio-controller;
511 sys-supply = <®_mod 511 sys-supply = <®_module_3v3>;
512 vin-sm0-supply = <® 512 vin-sm0-supply = <®_3v3_vsys>;
513 vin-sm1-supply = <® 513 vin-sm1-supply = <®_3v3_vsys>;
514 vin-sm2-supply = <® 514 vin-sm2-supply = <®_3v3_vsys>;
515 vinldo01-supply = <&re 515 vinldo01-supply = <®_1v8_vdd_ddr2>;
516 vinldo23-supply = <&re 516 vinldo23-supply = <®_module_3v3>;
517 vinldo4-supply = <® 517 vinldo4-supply = <®_module_3v3>;
518 vinldo678-supply = <&r 518 vinldo678-supply = <®_module_3v3>;
519 vinldo9-supply = <® 519 vinldo9-supply = <®_module_3v3>;
520 520
521 regulators { 521 regulators {
522 reg_3v3_vsys: 522 reg_3v3_vsys: sys {
523 regula 523 regulator-name = "VSYS_3.3V";
524 regula 524 regulator-always-on;
525 }; 525 };
526 526
527 vdd_core: sm0 527 vdd_core: sm0 {
528 regula 528 regulator-name = "VDD_CORE_1.2V";
529 regula 529 regulator-min-microvolt = <1200000>;
530 regula 530 regulator-max-microvolt = <1200000>;
531 regula 531 regulator-always-on;
532 }; 532 };
533 533
534 sm1 { 534 sm1 {
535 regula 535 regulator-name = "VDD_CPU_1.0V";
536 regula 536 regulator-min-microvolt = <1000000>;
537 regula 537 regulator-max-microvolt = <1000000>;
538 regula 538 regulator-always-on;
539 }; 539 };
540 540
541 reg_1v8_vdd_dd 541 reg_1v8_vdd_ddr2: sm2 {
542 regula 542 regulator-name = "VDD_DDR2_1.8V";
543 regula 543 regulator-min-microvolt = <1800000>;
544 regula 544 regulator-max-microvolt = <1800000>;
545 regula 545 regulator-always-on;
546 }; 546 };
547 547
548 /* LDO0 is not 548 /* LDO0 is not connected to anything */
549 549
550 /* 550 /*
551 * +3.3V_ENABL 551 * +3.3V_ENABLE_N switching via FET:
552 * AVDD_AUDIO_ 552 * AVDD_AUDIO_S and +3.3V
553 * see also +3 553 * see also +3.3V fixed supply
554 */ 554 */
555 ldo1 { 555 ldo1 {
556 regula 556 regulator-name = "AVDD_PLL_1.1V";
557 regula 557 regulator-min-microvolt = <1100000>;
558 regula 558 regulator-max-microvolt = <1100000>;
559 regula 559 regulator-always-on;
560 }; 560 };
561 561
562 ldo2 { 562 ldo2 {
563 regula 563 regulator-name = "VDD_RTC_1.2V";
564 regula 564 regulator-min-microvolt = <1200000>;
565 regula 565 regulator-max-microvolt = <1200000>;
566 }; 566 };
567 567
568 /* LDO3 is not 568 /* LDO3 is not connected to anything */
569 569
570 ldo4 { 570 ldo4 {
571 regula 571 regulator-name = "VDDIO_SYS_1.8V";
572 regula 572 regulator-min-microvolt = <1800000>;
573 regula 573 regulator-max-microvolt = <1800000>;
574 regula 574 regulator-always-on;
575 }; 575 };
576 576
577 /* Switched vi 577 /* Switched via FET from regular +3.3V */
578 ldo5 { 578 ldo5 {
579 regula 579 regulator-name = "+3.3V_USB";
580 regula 580 regulator-min-microvolt = <3300000>;
581 regula 581 regulator-max-microvolt = <3300000>;
582 regula 582 regulator-always-on;
583 }; 583 };
584 584
585 ldo6 { 585 ldo6 {
586 regula 586 regulator-name = "AVDD_VDAC_2.85V";
587 regula 587 regulator-min-microvolt = <2850000>;
588 regula 588 regulator-max-microvolt = <2850000>;
589 }; 589 };
590 590
591 reg_3v3_avdd_h 591 reg_3v3_avdd_hdmi: ldo7 {
592 regula 592 regulator-name = "AVDD_HDMI_3.3V";
593 regula 593 regulator-min-microvolt = <3300000>;
594 regula 594 regulator-max-microvolt = <3300000>;
595 }; 595 };
596 596
597 reg_1v8_avdd_h 597 reg_1v8_avdd_hdmi_pll: ldo8 {
598 regula 598 regulator-name = "AVDD_HDMI_PLL_1.8V";
599 regula 599 regulator-min-microvolt = <1800000>;
600 regula 600 regulator-max-microvolt = <1800000>;
601 }; 601 };
602 602
603 ldo9 { 603 ldo9 {
604 regula 604 regulator-name = "VDDIO_RX_DDR_2.85V";
605 regula 605 regulator-min-microvolt = <2850000>;
606 regula 606 regulator-max-microvolt = <2850000>;
607 regula 607 regulator-always-on;
608 }; 608 };
609 609
610 ldo_rtc { 610 ldo_rtc {
611 regula 611 regulator-name = "VCC_BATT";
612 regula 612 regulator-min-microvolt = <3300000>;
613 regula 613 regulator-max-microvolt = <3300000>;
614 regula 614 regulator-always-on;
615 }; 615 };
616 }; 616 };
617 }; 617 };
618 618
619 /* LM95245 temperature sensor 619 /* LM95245 temperature sensor */
620 temp-sensor@4c { 620 temp-sensor@4c {
621 compatible = "national 621 compatible = "national,lm95245";
622 reg = <0x4c>; 622 reg = <0x4c>;
623 }; 623 };
624 }; 624 };
625 625
626 pmc@7000e400 { 626 pmc@7000e400 {
627 nvidia,suspend-mode = <1>; 627 nvidia,suspend-mode = <1>;
628 nvidia,cpu-pwr-good-time = <50 628 nvidia,cpu-pwr-good-time = <5000>;
629 nvidia,cpu-pwr-off-time = <500 629 nvidia,cpu-pwr-off-time = <5000>;
630 nvidia,core-pwr-good-time = <3 630 nvidia,core-pwr-good-time = <3845 3845>;
631 nvidia,core-pwr-off-time = <38 631 nvidia,core-pwr-off-time = <3875>;
632 nvidia,sys-clock-req-active-hi 632 nvidia,sys-clock-req-active-high;
633 core-supply = <&vdd_core>; 633 core-supply = <&vdd_core>;
634 634
635 /* Set SLEEP MODE bit in SUPPL 635 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
636 i2c-thermtrip { 636 i2c-thermtrip {
637 nvidia,i2c-controller- 637 nvidia,i2c-controller-id = <3>;
638 nvidia,bus-addr = <0x3 638 nvidia,bus-addr = <0x34>;
639 nvidia,reg-addr = <0x1 639 nvidia,reg-addr = <0x14>;
640 nvidia,reg-data = <0x8 640 nvidia,reg-data = <0x8>;
641 }; 641 };
642 }; 642 };
643 643
644 memory-controller@7000f400 { 644 memory-controller@7000f400 {
645 emc-table@83250 { 645 emc-table@83250 {
646 reg = <83250>; 646 reg = <83250>;
647 compatible = "nvidia,t 647 compatible = "nvidia,tegra20-emc-table";
648 clock-frequency = <832 648 clock-frequency = <83250>;
649 nvidia,emc-registers = 649 nvidia,emc-registers = <0x00000005 0x00000011
650 0x00000004 0x0 650 0x00000004 0x00000002 0x00000004 0x00000004
651 0x00000001 0x0 651 0x00000001 0x0000000a 0x00000002 0x00000002
652 0x00000001 0x0 652 0x00000001 0x00000001 0x00000003 0x00000004
653 0x00000003 0x0 653 0x00000003 0x00000009 0x0000000c 0x0000025f
654 0x00000000 0x0 654 0x00000000 0x00000003 0x00000003 0x00000002
655 0x00000002 0x0 655 0x00000002 0x00000001 0x00000008 0x000000c8
656 0x00000003 0x0 656 0x00000003 0x00000005 0x00000003 0x0000000c
657 0x00000002 0x0 657 0x00000002 0x00000000 0x00000000 0x00000002
658 0x00000000 0x0 658 0x00000000 0x00000000 0x00000083 0x00520006
659 0x00000010 0x0 659 0x00000010 0x00000008 0x00000000 0x00000000
660 0x00000000 0x0 660 0x00000000 0x00000000 0x00000000 0x00000000>;
661 }; 661 };
662 emc-table@133200 { 662 emc-table@133200 {
663 reg = <133200>; 663 reg = <133200>;
664 compatible = "nvidia,t 664 compatible = "nvidia,tegra20-emc-table";
665 clock-frequency = <133 665 clock-frequency = <133200>;
666 nvidia,emc-registers = 666 nvidia,emc-registers = <0x00000008 0x00000019
667 0x00000006 0x0 667 0x00000006 0x00000002 0x00000004 0x00000004
668 0x00000001 0x0 668 0x00000001 0x0000000a 0x00000002 0x00000002
669 0x00000002 0x0 669 0x00000002 0x00000001 0x00000003 0x00000004
670 0x00000003 0x0 670 0x00000003 0x00000009 0x0000000c 0x0000039f
671 0x00000000 0x0 671 0x00000000 0x00000003 0x00000003 0x00000002
672 0x00000002 0x0 672 0x00000002 0x00000001 0x00000008 0x000000c8
673 0x00000003 0x0 673 0x00000003 0x00000007 0x00000003 0x0000000c
674 0x00000002 0x0 674 0x00000002 0x00000000 0x00000000 0x00000002
675 0x00000000 0x0 675 0x00000000 0x00000000 0x00000083 0x00510006
676 0x00000010 0x0 676 0x00000010 0x00000008 0x00000000 0x00000000
677 0x00000000 0x0 677 0x00000000 0x00000000 0x00000000 0x00000000>;
678 }; 678 };
679 emc-table@166500 { 679 emc-table@166500 {
680 reg = <166500>; 680 reg = <166500>;
681 compatible = "nvidia,t 681 compatible = "nvidia,tegra20-emc-table";
682 clock-frequency = <166 682 clock-frequency = <166500>;
683 nvidia,emc-registers = 683 nvidia,emc-registers = <0x0000000a 0x00000021
684 0x00000008 0x0 684 0x00000008 0x00000003 0x00000004 0x00000004
685 0x00000002 0x0 685 0x00000002 0x0000000a 0x00000003 0x00000003
686 0x00000002 0x0 686 0x00000002 0x00000001 0x00000003 0x00000004
687 0x00000003 0x0 687 0x00000003 0x00000009 0x0000000c 0x000004df
688 0x00000000 0x0 688 0x00000000 0x00000003 0x00000003 0x00000003
689 0x00000003 0x0 689 0x00000003 0x00000001 0x00000009 0x000000c8
690 0x00000003 0x0 690 0x00000003 0x00000009 0x00000004 0x0000000c
691 0x00000002 0x0 691 0x00000002 0x00000000 0x00000000 0x00000002
692 0x00000000 0x0 692 0x00000000 0x00000000 0x00000083 0x004f0006
693 0x00000010 0x0 693 0x00000010 0x00000008 0x00000000 0x00000000
694 0x00000000 0x0 694 0x00000000 0x00000000 0x00000000 0x00000000>;
695 }; 695 };
696 emc-table@333000 { 696 emc-table@333000 {
697 reg = <333000>; 697 reg = <333000>;
698 compatible = "nvidia,t 698 compatible = "nvidia,tegra20-emc-table";
699 clock-frequency = <333 699 clock-frequency = <333000>;
700 nvidia,emc-registers = 700 nvidia,emc-registers = <0x00000014 0x00000041
701 0x0000000f 0x0 701 0x0000000f 0x00000005 0x00000004 0x00000005
702 0x00000003 0x0 702 0x00000003 0x0000000a 0x00000005 0x00000005
703 0x00000004 0x0 703 0x00000004 0x00000001 0x00000003 0x00000004
704 0x00000003 0x0 704 0x00000003 0x00000009 0x0000000c 0x000009ff
705 0x00000000 0x0 705 0x00000000 0x00000003 0x00000003 0x00000005
706 0x00000005 0x0 706 0x00000005 0x00000001 0x0000000e 0x000000c8
707 0x00000003 0x0 707 0x00000003 0x00000011 0x00000006 0x0000000c
708 0x00000002 0x0 708 0x00000002 0x00000000 0x00000000 0x00000002
709 0x00000000 0x0 709 0x00000000 0x00000000 0x00000083 0x00380006
710 0x00000010 0x0 710 0x00000010 0x00000008 0x00000000 0x00000000
711 0x00000000 0x0 711 0x00000000 0x00000000 0x00000000 0x00000000>;
712 }; 712 };
713 }; 713 };
714 714
715 /* EHCI instance 1: ULPI PHY -> AX8877 715 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
716 usb@c5004000 { 716 usb@c5004000 {
717 status = "okay"; 717 status = "okay";
718 #address-cells = <1>; 718 #address-cells = <1>;
719 #size-cells = <0>; 719 #size-cells = <0>;
720 720
721 ethernet@1 { 721 ethernet@1 {
722 compatible = "usbb95,7 722 compatible = "usbb95,772b";
723 reg = <1>; 723 reg = <1>;
724 local-mac-address = [0 724 local-mac-address = [00 00 00 00 00 00];
725 }; 725 };
726 }; 726 };
727 727
728 usb-phy@c5004000 { 728 usb-phy@c5004000 {
729 status = "okay"; 729 status = "okay";
730 nvidia,phy-reset-gpio = 730 nvidia,phy-reset-gpio =
731 <&gpio TEGRA_GPIO(V, 1 731 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
732 vbus-supply = <®_lan_v_bus> 732 vbus-supply = <®_lan_v_bus>;
733 }; 733 };
734 734
735 clk32k_in: clock-xtal3 { 735 clk32k_in: clock-xtal3 {
736 compatible = "fixed-clock"; 736 compatible = "fixed-clock";
737 #clock-cells = <0>; 737 #clock-cells = <0>;
738 clock-frequency = <32768>; 738 clock-frequency = <32768>;
739 }; 739 };
740 740
741 opp-table-emc { 741 opp-table-emc {
742 /delete-node/ opp-760000000; 742 /delete-node/ opp-760000000;
743 }; 743 };
744 744
745 reg_lan_v_bus: regulator-lan-v-bus { 745 reg_lan_v_bus: regulator-lan-v-bus {
746 compatible = "regulator-fixed" 746 compatible = "regulator-fixed";
747 regulator-name = "LAN_V_BUS"; 747 regulator-name = "LAN_V_BUS";
748 regulator-min-microvolt = <500 748 regulator-min-microvolt = <5000000>;
749 regulator-max-microvolt = <500 749 regulator-max-microvolt = <5000000>;
750 enable-active-high; 750 enable-active-high;
751 gpio = <&gpio TEGRA_GPIO(BB, 1 751 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
752 }; 752 };
753 753
754 reg_module_3v3: regulator-module-3v3 { 754 reg_module_3v3: regulator-module-3v3 {
755 compatible = "regulator-fixed" 755 compatible = "regulator-fixed";
756 regulator-name = "+V3.3"; 756 regulator-name = "+V3.3";
757 regulator-min-microvolt = <330 757 regulator-min-microvolt = <3300000>;
758 regulator-max-microvolt = <330 758 regulator-max-microvolt = <3300000>;
759 regulator-always-on; 759 regulator-always-on;
760 }; 760 };
761 761
762 sound { 762 sound {
763 compatible = "nvidia,tegra-aud 763 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
764 "nvidia,tegra-aud 764 "nvidia,tegra-audio-wm9712";
765 nvidia,model = "Toradex Colibr 765 nvidia,model = "Toradex Colibri T20";
766 nvidia,audio-routing = 766 nvidia,audio-routing =
767 "Headphone", "HPOUTL", 767 "Headphone", "HPOUTL",
768 "Headphone", "HPOUTR", 768 "Headphone", "HPOUTR",
769 "LineIn", "LINEINL", 769 "LineIn", "LINEINL",
770 "LineIn", "LINEINR", 770 "LineIn", "LINEINR",
771 "Mic", "MIC1"; 771 "Mic", "MIC1";
772 nvidia,ac97-controller = <&teg 772 nvidia,ac97-controller = <&tegra_ac97>;
773 clocks = <&tegra_car TEGRA20_C 773 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
774 <&tegra_car TEGRA20_C 774 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
775 <&tegra_car TEGRA20_C 775 <&tegra_car TEGRA20_CLK_CDEV1>;
776 clock-names = "pll_a", "pll_a_ 776 clock-names = "pll_a", "pll_a_out0", "mclk";
777 }; 777 };
778 }; 778 };
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