1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h> 5 #include <dt-bindings/thermal/thermal.h>
6 6
7 #include "tegra20.dtsi" 7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi" 8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi" 9 #include "tegra20-cpu-opp-microvolt.dtsi"
10 10
11 / { 11 / {
12 model = "Toshiba AC100 / Dynabook AZ"; 12 model = "Toshiba AC100 / Dynabook AZ";
13 compatible = "compal,paz00", "nvidia,t 13 compatible = "compal,paz00", "nvidia,tegra20";
14 14
15 aliases { 15 aliases {
16 mmc0 = &sdmmc4; /* eMMC */ 16 mmc0 = &sdmmc4; /* eMMC */
17 mmc1 = &sdmmc1; /* MicroSD */ 17 mmc1 = &sdmmc1; /* MicroSD */
18 rtc0 = "/i2c@7000d000/tps6586x 18 rtc0 = "/i2c@7000d000/tps6586x@34";
19 rtc1 = "/rtc@7000e000"; 19 rtc1 = "/rtc@7000e000";
20 serial0 = &uarta; 20 serial0 = &uarta;
21 serial1 = &uartc; 21 serial1 = &uartc;
22 }; 22 };
23 23
24 chosen { 24 chosen {
25 stdout-path = "serial0:115200n 25 stdout-path = "serial0:115200n8";
26 }; 26 };
27 27
28 memory@0 { 28 memory@0 {
29 reg = <0x00000000 0x20000000>; 29 reg = <0x00000000 0x20000000>;
30 }; 30 };
31 31
32 host1x@50000000 { 32 host1x@50000000 {
33 dc@54200000 { 33 dc@54200000 {
34 rgb { 34 rgb {
35 status = "okay 35 status = "okay";
36 36
37 nvidia,panel = 37 nvidia,panel = <&panel>;
38 }; 38 };
39 }; 39 };
40 40
41 hdmi@54280000 { 41 hdmi@54280000 {
42 status = "okay"; 42 status = "okay";
43 43
44 vdd-supply = <&hdmi_vd 44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pl 45 pll-supply = <&hdmi_pll_reg>;
46 46
47 nvidia,ddc-i2c-bus = < 47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
48 nvidia,hpd-gpio = <&gp 48 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
49 GPIO_ACTIVE_HI 49 GPIO_ACTIVE_HIGH>;
50 }; 50 };
51 }; 51 };
52 52
53 pinmux@70000014 { 53 pinmux@70000014 {
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 pinctrl-0 = <&state_default>; 55 pinctrl-0 = <&state_default>;
56 56
57 state_default: pinmux { 57 state_default: pinmux {
58 ata { 58 ata {
59 nvidia,pins = 59 nvidia,pins = "ata", "atc", "atd", "ate",
60 "dap2" 60 "dap2", "gmb", "gmc", "gmd", "spia",
61 "spib" 61 "spib", "spic", "spid", "spie";
62 nvidia,functio 62 nvidia,function = "gmi";
63 }; 63 };
64 atb { 64 atb {
65 nvidia,pins = 65 nvidia,pins = "atb", "gma", "gme";
66 nvidia,functio 66 nvidia,function = "sdio4";
67 }; 67 };
68 cdev1 { 68 cdev1 {
69 nvidia,pins = 69 nvidia,pins = "cdev1";
70 nvidia,functio 70 nvidia,function = "plla_out";
71 }; 71 };
72 cdev2 { 72 cdev2 {
73 nvidia,pins = 73 nvidia,pins = "cdev2";
74 nvidia,functio 74 nvidia,function = "pllp_out4";
75 }; 75 };
76 crtp { 76 crtp {
77 nvidia,pins = 77 nvidia,pins = "crtp";
78 nvidia,functio 78 nvidia,function = "crt";
79 }; 79 };
80 csus { 80 csus {
81 nvidia,pins = 81 nvidia,pins = "csus";
82 nvidia,functio 82 nvidia,function = "pllc_out1";
83 }; 83 };
84 dap1 { 84 dap1 {
85 nvidia,pins = 85 nvidia,pins = "dap1";
86 nvidia,functio 86 nvidia,function = "dap1";
87 }; 87 };
88 dap3 { 88 dap3 {
89 nvidia,pins = 89 nvidia,pins = "dap3";
90 nvidia,functio 90 nvidia,function = "dap3";
91 }; 91 };
92 dap4 { 92 dap4 {
93 nvidia,pins = 93 nvidia,pins = "dap4";
94 nvidia,functio 94 nvidia,function = "dap4";
95 }; 95 };
96 ddc { 96 ddc {
97 nvidia,pins = 97 nvidia,pins = "ddc";
98 nvidia,functio 98 nvidia,function = "i2c2";
99 }; 99 };
100 dta { 100 dta {
101 nvidia,pins = 101 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
102 nvidia,functio 102 nvidia,function = "rsvd1";
103 }; 103 };
104 dtf { 104 dtf {
105 nvidia,pins = 105 nvidia,pins = "dtf";
106 nvidia,functio 106 nvidia,function = "i2c3";
107 }; 107 };
108 gpu { 108 gpu {
109 nvidia,pins = 109 nvidia,pins = "gpu", "sdb", "sdd";
110 nvidia,functio 110 nvidia,function = "pwm";
111 }; 111 };
112 gpu7 { 112 gpu7 {
113 nvidia,pins = 113 nvidia,pins = "gpu7";
114 nvidia,functio 114 nvidia,function = "rtck";
115 }; 115 };
116 gpv { 116 gpv {
117 nvidia,pins = 117 nvidia,pins = "gpv", "slxa", "slxk";
118 nvidia,functio 118 nvidia,function = "pcie";
119 }; 119 };
120 hdint { 120 hdint {
121 nvidia,pins = 121 nvidia,pins = "hdint", "pta";
122 nvidia,functio 122 nvidia,function = "hdmi";
123 }; 123 };
124 i2cp { 124 i2cp {
125 nvidia,pins = 125 nvidia,pins = "i2cp";
126 nvidia,functio 126 nvidia,function = "i2cp";
127 }; 127 };
128 irrx { 128 irrx {
129 nvidia,pins = 129 nvidia,pins = "irrx", "irtx";
130 nvidia,functio 130 nvidia,function = "uarta";
131 }; 131 };
132 kbca { 132 kbca {
133 nvidia,pins = 133 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
134 nvidia,functio 134 nvidia,function = "kbc";
135 }; 135 };
136 kbcb { 136 kbcb {
137 nvidia,pins = 137 nvidia,pins = "kbcb", "kbcd";
138 nvidia,functio 138 nvidia,function = "sdio2";
139 }; 139 };
140 lcsn { 140 lcsn {
141 nvidia,pins = 141 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
142 "ld3", 142 "ld3", "ld4", "ld5", "ld6", "ld7",
143 "ld8", 143 "ld8", "ld9", "ld10", "ld11", "ld12",
144 "ld13" 144 "ld13", "ld14", "ld15", "ld16", "ld17",
145 "ldc", 145 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
146 "lhs", 146 "lhs", "lm0", "lm1", "lpp", "lpw0",
147 "lpw1" 147 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
148 "lsda" 148 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
149 "lvs"; 149 "lvs";
150 nvidia,functio 150 nvidia,function = "displaya";
151 }; 151 };
152 owc { 152 owc {
153 nvidia,pins = 153 nvidia,pins = "owc";
154 nvidia,functio 154 nvidia,function = "owr";
155 }; 155 };
156 pmc { 156 pmc {
157 nvidia,pins = 157 nvidia,pins = "pmc";
158 nvidia,functio 158 nvidia,function = "pwr_on";
159 }; 159 };
160 rm { 160 rm {
161 nvidia,pins = 161 nvidia,pins = "rm";
162 nvidia,functio 162 nvidia,function = "i2c1";
163 }; 163 };
164 sdc { 164 sdc {
165 nvidia,pins = 165 nvidia,pins = "sdc";
166 nvidia,functio 166 nvidia,function = "twc";
167 }; 167 };
168 sdio1 { 168 sdio1 {
169 nvidia,pins = 169 nvidia,pins = "sdio1";
170 nvidia,functio 170 nvidia,function = "sdio1";
171 }; 171 };
172 slxc { 172 slxc {
173 nvidia,pins = 173 nvidia,pins = "slxc", "slxd";
174 nvidia,functio 174 nvidia,function = "spi4";
175 }; 175 };
176 spdi { 176 spdi {
177 nvidia,pins = 177 nvidia,pins = "spdi", "spdo";
178 nvidia,functio 178 nvidia,function = "rsvd2";
179 }; 179 };
180 spif { 180 spif {
181 nvidia,pins = 181 nvidia,pins = "spif", "uac";
182 nvidia,functio 182 nvidia,function = "rsvd4";
183 }; 183 };
184 spig { 184 spig {
185 nvidia,pins = 185 nvidia,pins = "spig", "spih";
186 nvidia,functio 186 nvidia,function = "spi2_alt";
187 }; 187 };
188 uaa { 188 uaa {
189 nvidia,pins = 189 nvidia,pins = "uaa", "uab", "uda";
190 nvidia,functio 190 nvidia,function = "ulpi";
191 }; 191 };
192 uad { 192 uad {
193 nvidia,pins = 193 nvidia,pins = "uad";
194 nvidia,functio 194 nvidia,function = "spdif";
195 }; 195 };
196 uca { 196 uca {
197 nvidia,pins = 197 nvidia,pins = "uca", "ucb";
198 nvidia,functio 198 nvidia,function = "uartc";
199 }; 199 };
200 conf_ata { 200 conf_ata {
201 nvidia,pins = 201 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
202 "cdev1 202 "cdev1", "cdev2", "dap1", "dap2", "dtf",
203 "gma", 203 "gma", "gmb", "gmc", "gmd", "gme",
204 "gpu", 204 "gpu", "gpu7", "gpv", "i2cp", "pta",
205 "rm", 205 "rm", "sdio1", "slxk", "spdo", "uac",
206 "uda"; 206 "uda";
207 nvidia,pull = 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristat 208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 }; 209 };
210 conf_ck32 { 210 conf_ck32 {
211 nvidia,pins = 211 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
212 "pmcc" 212 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
213 nvidia,pull = 213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 }; 214 };
215 conf_crtp { 215 conf_crtp {
216 nvidia,pins = 216 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
217 "dtc", 217 "dtc", "dte", "slxa", "slxc", "slxd",
218 "spdi" 218 "spdi";
219 nvidia,pull = 219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristat 220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
221 }; 221 };
222 conf_csus { 222 conf_csus {
223 nvidia,pins = 223 nvidia,pins = "csus", "spia", "spib", "spid",
224 "spif" 224 "spif";
225 nvidia,pull = 225 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
226 nvidia,tristat 226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227 }; 227 };
228 conf_ddc { 228 conf_ddc {
229 nvidia,pins = 229 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
230 "kbcb" 230 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
231 "spic" 231 "spic", "spig", "uaa", "uab";
232 nvidia,pull = 232 nvidia,pull = <TEGRA_PIN_PULL_UP>;
233 nvidia,tristat 233 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 }; 234 };
235 conf_dta { 235 conf_dta {
236 nvidia,pins = 236 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
237 "spie" 237 "spie", "spih", "uad", "uca", "ucb";
238 nvidia,pull = 238 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 nvidia,tristat 239 nvidia,tristate = <TEGRA_PIN_ENABLE>;
240 }; 240 };
241 conf_hdint { 241 conf_hdint {
242 nvidia,pins = 242 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
243 "ld3", 243 "ld3", "ld4", "ld5", "ld6", "ld7",
244 "ld8", 244 "ld8", "ld9", "ld10", "ld11", "ld12",
245 "ld13" 245 "ld13", "ld14", "ld15", "ld16", "ld17",
246 "ldc", 246 "ldc", "ldi", "lhs", "lsc0", "lspi",
247 "lvs", 247 "lvs", "pmc";
248 nvidia,tristat 248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 }; 249 };
250 conf_lc { 250 conf_lc {
251 nvidia,pins = 251 nvidia,pins = "lc", "ls";
252 nvidia,pull = 252 nvidia,pull = <TEGRA_PIN_PULL_UP>;
253 }; 253 };
254 conf_lcsn { 254 conf_lcsn {
255 nvidia,pins = 255 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
256 "lm0", 256 "lm0", "lm1", "lpp", "lpw0", "lpw1",
257 "lpw2" 257 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
258 "lvp0" 258 "lvp0", "lvp1", "sdb";
259 nvidia,tristat 259 nvidia,tristate = <TEGRA_PIN_ENABLE>;
260 }; 260 };
261 conf_ld17_0 { 261 conf_ld17_0 {
262 nvidia,pins = 262 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
263 "ld23_ 263 "ld23_22";
264 nvidia,pull = 264 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
265 }; 265 };
266 }; 266 };
267 }; 267 };
268 268
269 spdif@70002400 { 269 spdif@70002400 {
270 status = "okay"; 270 status = "okay";
271 271
272 nvidia,fixed-parent-rate; 272 nvidia,fixed-parent-rate;
273 }; 273 };
274 274
275 i2s@70002800 { 275 i2s@70002800 {
276 status = "okay"; 276 status = "okay";
277 277
278 nvidia,fixed-parent-rate; 278 nvidia,fixed-parent-rate;
279 }; 279 };
280 280
281 serial@70006000 { 281 serial@70006000 {
282 /delete-property/ dmas; <<
283 /delete-property/ dma-names; <<
284 status = "okay"; 282 status = "okay";
285 }; 283 };
286 284
287 serial@70006200 { 285 serial@70006200 {
288 /delete-property/ dmas; <<
289 /delete-property/ dma-names; <<
290 status = "okay"; 286 status = "okay";
291 }; 287 };
292 288
293 pwm: pwm@7000a000 { 289 pwm: pwm@7000a000 {
294 status = "okay"; 290 status = "okay";
295 }; 291 };
296 292
297 lvds_ddc: i2c@7000c000 { 293 lvds_ddc: i2c@7000c000 {
298 status = "okay"; 294 status = "okay";
299 clock-frequency = <400000>; 295 clock-frequency = <400000>;
300 296
301 alc5632: alc5632@1e { 297 alc5632: alc5632@1e {
302 compatible = "realtek, 298 compatible = "realtek,alc5632";
303 reg = <0x1e>; 299 reg = <0x1e>;
304 gpio-controller; 300 gpio-controller;
305 #gpio-cells = <2>; 301 #gpio-cells = <2>;
306 }; 302 };
307 }; 303 };
308 304
309 hdmi_ddc: i2c@7000c400 { 305 hdmi_ddc: i2c@7000c400 {
310 status = "okay"; 306 status = "okay";
311 clock-frequency = <100000>; 307 clock-frequency = <100000>;
312 }; 308 };
313 309
314 i2c@7000c500 { !! 310 nvec@7000c500 {
315 compatible = "nvidia,nvec"; 311 compatible = "nvidia,nvec";
316 !! 312 reg = <0x7000c500 0x100>;
317 /delete-property/ #address-cel !! 313 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
318 /delete-property/ #size-cells; !! 314 #address-cells = <1>;
319 /delete-property/ dmas; !! 315 #size-cells = <0>;
320 /delete-property/ dma-names; <<
321 <<
322 clock-frequency = <80000>; 316 clock-frequency = <80000>;
323 request-gpios = <&gpio TEGRA_G 317 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
324 slave-addr = <138>; 318 slave-addr = <138>;
325 !! 319 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
326 status = "okay"; !! 320 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
>> 321 clock-names = "div-clk", "fast-clk";
>> 322 resets = <&tegra_car 67>;
>> 323 reset-names = "i2c";
327 }; 324 };
328 325
329 i2c@7000d000 { 326 i2c@7000d000 {
330 status = "okay"; 327 status = "okay";
331 clock-frequency = <400000>; 328 clock-frequency = <400000>;
332 329
333 pmic: tps6586x@34 { 330 pmic: tps6586x@34 {
334 compatible = "ti,tps65 331 compatible = "ti,tps6586x";
335 reg = <0x34>; 332 reg = <0x34>;
336 interrupts = <GIC_SPI 333 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
337 334
338 #gpio-cells = <2>; 335 #gpio-cells = <2>;
339 gpio-controller; 336 gpio-controller;
340 337
341 sys-supply = <&p5valw_ 338 sys-supply = <&p5valw_reg>;
342 vin-sm0-supply = <&sys 339 vin-sm0-supply = <&sys_reg>;
343 vin-sm1-supply = <&sys 340 vin-sm1-supply = <&sys_reg>;
344 vin-sm2-supply = <&sys 341 vin-sm2-supply = <&sys_reg>;
345 vinldo01-supply = <&sm 342 vinldo01-supply = <&sm2_reg>;
346 vinldo23-supply = <&sm 343 vinldo23-supply = <&sm2_reg>;
347 vinldo4-supply = <&sm2 344 vinldo4-supply = <&sm2_reg>;
348 vinldo678-supply = <&s 345 vinldo678-supply = <&sm2_reg>;
349 vinldo9-supply = <&sm2 346 vinldo9-supply = <&sm2_reg>;
350 347
351 regulators { 348 regulators {
352 sys_reg: sys { 349 sys_reg: sys {
353 regula 350 regulator-name = "vdd_sys";
354 regula 351 regulator-always-on;
355 }; 352 };
356 353
357 core_vdd_reg: 354 core_vdd_reg: sm0 {
358 regula 355 regulator-name = "+1.2vs_sm0,vdd_core";
359 regula 356 regulator-min-microvolt = <950000>;
360 regula 357 regulator-max-microvolt = <1300000>;
361 regula 358 regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
362 regula 359 regulator-coupled-max-spread = <170000 550000>;
363 regula 360 regulator-always-on;
364 361
365 nvidia 362 nvidia,tegra-core-regulator;
366 }; 363 };
367 364
368 cpu_vdd_reg: s 365 cpu_vdd_reg: sm1 {
369 regula 366 regulator-name = "+1.0vs_sm1,vdd_cpu";
370 regula 367 regulator-min-microvolt = <750000>;
371 regula 368 regulator-max-microvolt = <1100000>;
372 regula 369 regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
373 regula 370 regulator-coupled-max-spread = <550000 550000>;
374 regula 371 regulator-always-on;
375 372
376 nvidia 373 nvidia,tegra-cpu-regulator;
377 }; 374 };
378 375
379 sm2_reg: sm2 { 376 sm2_reg: sm2 {
380 regula 377 regulator-name = "+3.7vs_sm2,vin_ldo*";
381 regula 378 regulator-min-microvolt = <3700000>;
382 regula 379 regulator-max-microvolt = <3700000>;
383 regula 380 regulator-always-on;
384 }; 381 };
385 382
386 /* LDO0 is not 383 /* LDO0 is not connected to anything */
387 384
388 ldo1 { 385 ldo1 {
389 regula 386 regulator-name = "+1.1vs_ldo1,avdd_pll*";
390 regula 387 regulator-min-microvolt = <1100000>;
391 regula 388 regulator-max-microvolt = <1100000>;
392 regula 389 regulator-always-on;
393 }; 390 };
394 391
395 rtc_vdd_reg: l 392 rtc_vdd_reg: ldo2 {
396 regula 393 regulator-name = "+1.2vs_ldo2,vdd_rtc";
397 regula 394 regulator-min-microvolt = <950000>;
398 regula 395 regulator-max-microvolt = <1300000>;
399 regula 396 regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
400 regula 397 regulator-coupled-max-spread = <170000 550000>;
401 regula 398 regulator-always-on;
402 399
403 nvidia 400 nvidia,tegra-rtc-regulator;
404 }; 401 };
405 402
406 ldo3 { 403 ldo3 {
407 regula 404 regulator-name = "+3.3vs_ldo3,avdd_usb*";
408 regula 405 regulator-min-microvolt = <3300000>;
409 regula 406 regulator-max-microvolt = <3300000>;
410 regula 407 regulator-always-on;
411 }; 408 };
412 409
413 ldo4 { 410 ldo4 {
414 regula 411 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
415 regula 412 regulator-min-microvolt = <1800000>;
416 regula 413 regulator-max-microvolt = <1800000>;
417 regula 414 regulator-always-on;
418 }; 415 };
419 416
420 ldo5 { 417 ldo5 {
421 regula 418 regulator-name = "+2.85vs_ldo5,vcore_mmc";
422 regula 419 regulator-min-microvolt = <2850000>;
423 regula 420 regulator-max-microvolt = <2850000>;
424 regula 421 regulator-always-on;
425 }; 422 };
426 423
427 ldo6 { 424 ldo6 {
428 /* 425 /*
429 * Res 426 * Research indicates this should be
430 * 1.8 427 * 1.8v; other boards that use this
431 * rai 428 * rail for the same purpose need it
432 * set 429 * set to 1.8v. The schematic signal
433 * nam 430 * name is incorrect; perhaps copied
434 * fro 431 * from an incorrect NVIDIA reference.
435 */ 432 */
436 regula 433 regulator-name = "+2.85vs_ldo6,avdd_vdac";
437 regula 434 regulator-min-microvolt = <1800000>;
438 regula 435 regulator-max-microvolt = <1800000>;
439 }; 436 };
440 437
441 hdmi_vdd_reg: 438 hdmi_vdd_reg: ldo7 {
442 regula 439 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
443 regula 440 regulator-min-microvolt = <3300000>;
444 regula 441 regulator-max-microvolt = <3300000>;
445 }; 442 };
446 443
447 hdmi_pll_reg: 444 hdmi_pll_reg: ldo8 {
448 regula 445 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
449 regula 446 regulator-min-microvolt = <1800000>;
450 regula 447 regulator-max-microvolt = <1800000>;
451 }; 448 };
452 449
453 ldo9 { 450 ldo9 {
454 regula 451 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
455 regula 452 regulator-min-microvolt = <2850000>;
456 regula 453 regulator-max-microvolt = <2850000>;
457 regula 454 regulator-always-on;
458 }; 455 };
459 456
460 ldo_rtc { 457 ldo_rtc {
461 regula 458 regulator-name = "+3.3vs_rtc";
462 regula 459 regulator-min-microvolt = <3300000>;
463 regula 460 regulator-max-microvolt = <3300000>;
464 regula 461 regulator-always-on;
465 }; 462 };
466 }; 463 };
467 }; 464 };
468 465
469 adt7461: temperature-sensor@4c 466 adt7461: temperature-sensor@4c {
470 compatible = "adi,adt7 467 compatible = "adi,adt7461";
471 reg = <0x4c>; 468 reg = <0x4c>;
472 469
473 interrupt-parent = <&g 470 interrupt-parent = <&gpio>;
474 interrupts = <TEGRA_GP 471 interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
475 472
476 #thermal-sensor-cells 473 #thermal-sensor-cells = <1>;
477 }; 474 };
478 }; 475 };
479 476
480 pmc@7000e400 { 477 pmc@7000e400 {
481 nvidia,invert-interrupt; 478 nvidia,invert-interrupt;
482 nvidia,suspend-mode = <1>; 479 nvidia,suspend-mode = <1>;
483 nvidia,cpu-pwr-good-time = <20 480 nvidia,cpu-pwr-good-time = <2000>;
484 nvidia,cpu-pwr-off-time = <0>; 481 nvidia,cpu-pwr-off-time = <0>;
485 nvidia,core-pwr-good-time = <3 482 nvidia,core-pwr-good-time = <3845 3845>;
486 nvidia,core-pwr-off-time = <0> 483 nvidia,core-pwr-off-time = <0>;
487 nvidia,sys-clock-req-active-hi 484 nvidia,sys-clock-req-active-high;
488 core-supply = <&core_vdd_reg>; 485 core-supply = <&core_vdd_reg>;
489 }; 486 };
490 487
491 memory-controller@7000f400 { 488 memory-controller@7000f400 {
492 nvidia,use-ram-code; 489 nvidia,use-ram-code;
493 490
494 emc-tables@0 { 491 emc-tables@0 {
495 nvidia,ram-code = <0x0 492 nvidia,ram-code = <0x0>;
496 #address-cells = <1>; 493 #address-cells = <1>;
497 #size-cells = <0>; 494 #size-cells = <0>;
498 reg = <0>; 495 reg = <0>;
499 <<
500 emc-table@166500 { <<
501 reg = <166500> <<
502 compatible = " <<
503 clock-frequenc <<
504 nvidia,emc-reg <<
505 0x0000 <<
506 0x0000 <<
507 0x0000 <<
508 0x0000 <<
509 0x0000 <<
510 0x0000 <<
511 0x0000 <<
512 0x0000 <<
513 0x0000 <<
514 0x007f <<
515 0x0000 <<
516 }; <<
517 <<
518 emc-table@333000 { <<
519 reg = <333000> <<
520 compatible = " <<
521 clock-frequenc <<
522 nvidia,emc-reg <<
523 0x0000 <<
524 0x0000 <<
525 0x0000 <<
526 0x0000 <<
527 0x0000 <<
528 0x0000 <<
529 0x0000 <<
530 0x0000 <<
531 0x0000 <<
532 0x007f <<
533 0x0000 <<
534 }; <<
535 }; <<
536 <<
537 emc-tables@1 { <<
538 nvidia,ram-code = <0x1 <<
539 #address-cells = <1>; <<
540 #size-cells = <0>; <<
541 reg = <1>; <<
542 496
543 emc-table@166500 { 497 emc-table@166500 {
544 reg = <166500> 498 reg = <166500>;
545 compatible = " 499 compatible = "nvidia,tegra20-emc-table";
546 clock-frequenc 500 clock-frequency = <166500>;
547 nvidia,emc-reg 501 nvidia,emc-registers = <0x0000000a 0x00000016
548 0x0000 502 0x00000008 0x00000003 0x00000004 0x00000004
549 0x0000 503 0x00000002 0x0000000c 0x00000003 0x00000003
550 0x0000 504 0x00000002 0x00000001 0x00000004 0x00000005
551 0x0000 505 0x00000004 0x00000009 0x0000000d 0x000004df
552 0x0000 506 0x00000000 0x00000003 0x00000003 0x00000003
553 0x0000 507 0x00000003 0x00000001 0x0000000a 0x000000c8
554 0x0000 508 0x00000003 0x00000006 0x00000004 0x00000008
555 0x0000 509 0x00000002 0x00000000 0x00000000 0x00000002
556 0x0000 510 0x00000000 0x00000000 0x00000083 0xe03b0323
557 0x007f 511 0x007fe010 0x00001414 0x00000000 0x00000000
558 0x0000 512 0x00000000 0x00000000 0x00000000 0x00000000>;
559 }; 513 };
560 514
561 emc-table@333000 { 515 emc-table@333000 {
562 reg = <333000> 516 reg = <333000>;
563 compatible = " 517 compatible = "nvidia,tegra20-emc-table";
564 clock-frequenc 518 clock-frequency = <333000>;
565 nvidia,emc-reg 519 nvidia,emc-registers = <0x00000018 0x00000033
566 0x0000 520 0x00000012 0x00000004 0x00000004 0x00000005
567 0x0000 521 0x00000003 0x0000000c 0x00000006 0x00000006
568 0x0000 522 0x00000003 0x00000001 0x00000004 0x00000005
569 0x0000 523 0x00000004 0x00000009 0x0000000d 0x00000bff
570 0x0000 524 0x00000000 0x00000003 0x00000003 0x00000006
571 0x0000 525 0x00000006 0x00000001 0x00000011 0x000000c8
572 0x0000 526 0x00000003 0x0000000e 0x00000007 0x00000008
573 0x0000 527 0x00000002 0x00000000 0x00000000 0x00000002
574 0x0000 528 0x00000000 0x00000000 0x00000083 0xf0440303
575 0x007f 529 0x007fe010 0x00001414 0x00000000 0x00000000
576 0x0000 530 0x00000000 0x00000000 0x00000000 0x00000000>;
577 }; 531 };
578 }; 532 };
579 }; 533 };
580 534
581 usb@c5000000 { 535 usb@c5000000 {
582 compatible = "nvidia,tegra20-u 536 compatible = "nvidia,tegra20-udc";
583 status = "okay"; 537 status = "okay";
584 dr_mode = "peripheral"; 538 dr_mode = "peripheral";
585 }; 539 };
586 540
587 usb-phy@c5000000 { 541 usb-phy@c5000000 {
588 status = "okay"; 542 status = "okay";
589 }; 543 };
590 544
591 usb@c5004000 { 545 usb@c5004000 {
592 status = "okay"; 546 status = "okay";
593 }; 547 };
594 548
595 usb-phy@c5004000 { 549 usb-phy@c5004000 {
596 status = "okay"; 550 status = "okay";
597 nvidia,phy-reset-gpio = <&gpio 551 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
598 GPIO_ACTIVE_LOW>; 552 GPIO_ACTIVE_LOW>;
599 }; 553 };
600 554
601 usb@c5008000 { 555 usb@c5008000 {
602 status = "okay"; 556 status = "okay";
603 }; 557 };
604 558
605 usb-phy@c5008000 { 559 usb-phy@c5008000 {
606 status = "okay"; 560 status = "okay";
607 }; 561 };
608 562
609 sdmmc1: mmc@c8000000 { 563 sdmmc1: mmc@c8000000 {
610 status = "okay"; 564 status = "okay";
611 cd-gpios = <&gpio TEGRA_GPIO(V 565 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
612 wp-gpios = <&gpio TEGRA_GPIO(H 566 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
613 power-gpios = <&gpio TEGRA_GPI 567 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
614 bus-width = <4>; 568 bus-width = <4>;
615 }; 569 };
616 570
617 sdmmc4: mmc@c8000600 { 571 sdmmc4: mmc@c8000600 {
618 status = "okay"; 572 status = "okay";
619 bus-width = <8>; 573 bus-width = <8>;
620 non-removable; 574 non-removable;
621 }; 575 };
622 576
623 backlight: backlight { 577 backlight: backlight {
624 compatible = "pwm-backlight"; 578 compatible = "pwm-backlight";
625 579
626 enable-gpios = <&gpio TEGRA_GP 580 enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
627 pwms = <&pwm 0 5000000>; 581 pwms = <&pwm 0 5000000>;
628 582
629 brightness-levels = <0 16 32 4 583 brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>;
630 default-brightness-level = <10 584 default-brightness-level = <10>;
631 585
632 /* close enough */ 586 /* close enough */
633 power-supply = <&vdd_pnl_reg>; 587 power-supply = <&vdd_pnl_reg>;
634 }; 588 };
635 589
636 clk32k_in: clock-32k { 590 clk32k_in: clock-32k {
637 compatible = "fixed-clock"; 591 compatible = "fixed-clock";
638 clock-frequency = <32768>; 592 clock-frequency = <32768>;
639 #clock-cells = <0>; 593 #clock-cells = <0>;
640 }; 594 };
641 595
642 cpus { 596 cpus {
643 cpu0: cpu@0 { 597 cpu0: cpu@0 {
644 cpu-supply = <&cpu_vdd 598 cpu-supply = <&cpu_vdd_reg>;
645 operating-points-v2 = 599 operating-points-v2 = <&cpu0_opp_table>;
646 #cooling-cells = <2>; 600 #cooling-cells = <2>;
647 }; 601 };
648 602
649 cpu1: cpu@1 { 603 cpu1: cpu@1 {
650 cpu-supply = <&cpu_vdd 604 cpu-supply = <&cpu_vdd_reg>;
651 operating-points-v2 = 605 operating-points-v2 = <&cpu0_opp_table>;
652 #cooling-cells = <2>; 606 #cooling-cells = <2>;
653 }; 607 };
654 }; 608 };
655 609
656 gpio-keys { 610 gpio-keys {
657 compatible = "gpio-keys"; 611 compatible = "gpio-keys";
658 612
659 key-wakeup { 613 key-wakeup {
660 label = "Wakeup"; 614 label = "Wakeup";
661 gpios = <&gpio TEGRA_G 615 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
662 linux,code = <KEY_WAKE 616 linux,code = <KEY_WAKEUP>;
663 wakeup-source; 617 wakeup-source;
664 }; 618 };
665 }; 619 };
666 620
667 gpio-leds { 621 gpio-leds {
668 compatible = "gpio-leds"; 622 compatible = "gpio-leds";
669 623
670 led-0 { 624 led-0 {
671 label = "wifi-led"; 625 label = "wifi-led";
672 gpios = <&gpio TEGRA_G 626 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
673 linux,default-trigger 627 linux,default-trigger = "rfkill0";
674 }; 628 };
675 }; 629 };
676 630
677 opp-table-emc { 631 opp-table-emc {
678 /delete-node/ opp-760000000; 632 /delete-node/ opp-760000000;
679 }; 633 };
680 634
681 panel: panel { 635 panel: panel {
682 compatible = "samsung,ltn101nt 636 compatible = "samsung,ltn101nt05";
683 637
684 ddc-i2c-bus = <&lvds_ddc>; 638 ddc-i2c-bus = <&lvds_ddc>;
685 power-supply = <&vdd_pnl_reg>; 639 power-supply = <&vdd_pnl_reg>;
686 enable-gpios = <&gpio TEGRA_GP 640 enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>;
687 641
688 backlight = <&backlight>; 642 backlight = <&backlight>;
689 }; 643 };
690 644
691 p5valw_reg: regulator-5v0alw { 645 p5valw_reg: regulator-5v0alw {
692 compatible = "regulator-fixed" 646 compatible = "regulator-fixed";
693 regulator-name = "+5valw"; 647 regulator-name = "+5valw";
694 regulator-min-microvolt = <500 648 regulator-min-microvolt = <5000000>;
695 regulator-max-microvolt = <500 649 regulator-max-microvolt = <5000000>;
696 regulator-always-on; 650 regulator-always-on;
697 }; 651 };
698 652
699 vdd_pnl_reg: regulator-3v0 { 653 vdd_pnl_reg: regulator-3v0 {
700 compatible = "regulator-fixed" 654 compatible = "regulator-fixed";
701 regulator-name = "+3VS,vdd_pnl 655 regulator-name = "+3VS,vdd_pnl";
702 regulator-min-microvolt = <330 656 regulator-min-microvolt = <3300000>;
703 regulator-max-microvolt = <330 657 regulator-max-microvolt = <3300000>;
704 regulator-boot-on; 658 regulator-boot-on;
705 gpio = <&gpio TEGRA_GPIO(A, 4) 659 gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
706 enable-active-high; 660 enable-active-high;
707 }; 661 };
708 662
709 sound { 663 sound {
710 compatible = "nvidia,tegra-aud 664 compatible = "nvidia,tegra-audio-alc5632-paz00",
711 "nvidia,tegra-audio-al 665 "nvidia,tegra-audio-alc5632";
712 666
713 nvidia,model = "Compal PAZ00"; 667 nvidia,model = "Compal PAZ00";
714 668
715 nvidia,audio-routing = 669 nvidia,audio-routing =
716 "Int Spk", "SPKOUT", 670 "Int Spk", "SPKOUT",
717 "Int Spk", "SPKOUTN", 671 "Int Spk", "SPKOUTN",
718 "Headset Mic", "MICBIA 672 "Headset Mic", "MICBIAS1",
719 "MIC1", "Headset Mic", 673 "MIC1", "Headset Mic",
720 "Headset Stereophone", 674 "Headset Stereophone", "HPR",
721 "Headset Stereophone", 675 "Headset Stereophone", "HPL",
722 "DMICDAT", "Digital Mi 676 "DMICDAT", "Digital Mic";
723 677
724 nvidia,audio-codec = <&alc5632 678 nvidia,audio-codec = <&alc5632>;
725 nvidia,i2s-controller = <&tegr 679 nvidia,i2s-controller = <&tegra_i2s1>;
726 nvidia,hp-det-gpios = <&gpio T 680 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
727 GPIO_ACTIVE_HIGH>; 681 GPIO_ACTIVE_HIGH>;
728 682
729 clocks = <&tegra_car TEGRA20_C 683 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
730 <&tegra_car TEGRA20_C 684 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
731 <&tegra_car TEGRA20_C 685 <&tegra_car TEGRA20_CLK_CDEV1>;
732 clock-names = "pll_a", "pll_a_ 686 clock-names = "pll_a", "pll_a_out0", "mclk";
733 }; 687 };
734 688
735 thermal-zones { 689 thermal-zones {
736 cpu-thermal { 690 cpu-thermal {
737 polling-delay-passive 691 polling-delay-passive = <500>; /* milliseconds */
738 polling-delay = <1500> 692 polling-delay = <1500>; /* milliseconds */
739 693
740 thermal-sensors = <&ad 694 thermal-sensors = <&adt7461 1>;
741 695
742 trips { 696 trips {
743 trip0: cpu-ale 697 trip0: cpu-alert0 {
744 /* sta 698 /* start throttling at 80C */
745 temper 699 temperature = <80000>;
746 hyster 700 hysteresis = <200>;
747 type = 701 type = "passive";
748 }; 702 };
749 703
750 trip1: cpu-cri 704 trip1: cpu-crit {
751 /* shu 705 /* shut down at 85C */
752 temper 706 temperature = <85000>;
753 hyster 707 hysteresis = <2000>;
754 type = 708 type = "critical";
755 }; 709 };
756 }; 710 };
757 711
758 cooling-maps { 712 cooling-maps {
759 map0 { 713 map0 {
760 trip = 714 trip = <&trip0>;
761 coolin 715 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
762 716 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
763 }; 717 };
764 }; 718 };
765 }; 719 };
766 }; 720 };
767 }; 721 };
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