1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/; 2 /dts-v1/;
3 3
4 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h> <<
6 #include "tegra20.dtsi" 5 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi" 6 #include "tegra20-cpu-opp.dtsi"
8 7
9 / { 8 / {
10 model = "Compulab TrimSlice board"; 9 model = "Compulab TrimSlice board";
11 compatible = "compulab,trimslice", "nv 10 compatible = "compulab,trimslice", "nvidia,tegra20";
12 11
13 aliases { 12 aliases {
14 rtc0 = "/i2c@7000c500/rtc@56"; 13 rtc0 = "/i2c@7000c500/rtc@56";
15 rtc1 = "/rtc@7000e000"; 14 rtc1 = "/rtc@7000e000";
16 serial0 = &uarta; 15 serial0 = &uarta;
17 }; 16 };
18 17
19 chosen { 18 chosen {
20 stdout-path = "serial0:115200n 19 stdout-path = "serial0:115200n8";
21 }; 20 };
22 21
23 memory@0 { 22 memory@0 {
24 reg = <0x00000000 0x40000000>; 23 reg = <0x00000000 0x40000000>;
25 }; 24 };
26 25
27 host1x@50000000 { 26 host1x@50000000 {
28 hdmi@54280000 { 27 hdmi@54280000 {
29 status = "okay"; 28 status = "okay";
30 29
31 vdd-supply = <&hdmi_vd 30 vdd-supply = <&hdmi_vdd_reg>;
32 pll-supply = <&hdmi_pl 31 pll-supply = <&hdmi_pll_reg>;
33 32
34 nvidia,ddc-i2c-bus = < 33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
35 nvidia,hpd-gpio = <&gp 34 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
36 GPIO_ACTIVE_HI 35 GPIO_ACTIVE_HIGH>;
37 }; 36 };
38 }; 37 };
39 38
40 pinmux@70000014 { 39 pinmux@70000014 {
41 pinctrl-names = "default"; 40 pinctrl-names = "default";
42 pinctrl-0 = <&state_default>; 41 pinctrl-0 = <&state_default>;
43 42
44 state_default: pinmux { 43 state_default: pinmux {
45 ata { 44 ata {
46 nvidia,pins = 45 nvidia,pins = "ata";
47 nvidia,functio 46 nvidia,function = "ide";
48 }; 47 };
49 atb { 48 atb {
50 nvidia,pins = 49 nvidia,pins = "atb", "gma";
51 nvidia,functio 50 nvidia,function = "sdio4";
52 }; 51 };
53 atc { 52 atc {
54 nvidia,pins = 53 nvidia,pins = "atc", "gmb";
55 nvidia,functio 54 nvidia,function = "nand";
56 }; 55 };
57 atd { 56 atd {
58 nvidia,pins = 57 nvidia,pins = "atd", "ate", "gme", "pta";
59 nvidia,functio 58 nvidia,function = "gmi";
60 }; 59 };
61 cdev1 { 60 cdev1 {
62 nvidia,pins = 61 nvidia,pins = "cdev1";
63 nvidia,functio 62 nvidia,function = "plla_out";
64 }; 63 };
65 cdev2 { 64 cdev2 {
66 nvidia,pins = 65 nvidia,pins = "cdev2";
67 nvidia,functio 66 nvidia,function = "pllp_out4";
68 }; 67 };
69 crtp { 68 crtp {
70 nvidia,pins = 69 nvidia,pins = "crtp";
71 nvidia,functio 70 nvidia,function = "crt";
72 }; 71 };
73 csus { 72 csus {
74 nvidia,pins = 73 nvidia,pins = "csus";
75 nvidia,functio 74 nvidia,function = "vi_sensor_clk";
76 }; 75 };
77 dap1 { 76 dap1 {
78 nvidia,pins = 77 nvidia,pins = "dap1";
79 nvidia,functio 78 nvidia,function = "dap1";
80 }; 79 };
81 dap2 { 80 dap2 {
82 nvidia,pins = 81 nvidia,pins = "dap2";
83 nvidia,functio 82 nvidia,function = "dap2";
84 }; 83 };
85 dap3 { 84 dap3 {
86 nvidia,pins = 85 nvidia,pins = "dap3";
87 nvidia,functio 86 nvidia,function = "dap3";
88 }; 87 };
89 dap4 { 88 dap4 {
90 nvidia,pins = 89 nvidia,pins = "dap4";
91 nvidia,functio 90 nvidia,function = "dap4";
92 }; 91 };
93 ddc { 92 ddc {
94 nvidia,pins = 93 nvidia,pins = "ddc";
95 nvidia,functio 94 nvidia,function = "i2c2";
96 }; 95 };
97 dta { 96 dta {
98 nvidia,pins = 97 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
99 nvidia,functio 98 nvidia,function = "vi";
100 }; 99 };
101 dtf { 100 dtf {
102 nvidia,pins = 101 nvidia,pins = "dtf";
103 nvidia,functio 102 nvidia,function = "i2c3";
104 }; 103 };
105 gmc { 104 gmc {
106 nvidia,pins = 105 nvidia,pins = "gmc", "gmd";
107 nvidia,functio 106 nvidia,function = "sflash";
108 }; 107 };
109 gpu { 108 gpu {
110 nvidia,pins = 109 nvidia,pins = "gpu";
111 nvidia,functio 110 nvidia,function = "uarta";
112 }; 111 };
113 gpu7 { 112 gpu7 {
114 nvidia,pins = 113 nvidia,pins = "gpu7";
115 nvidia,functio 114 nvidia,function = "rtck";
116 }; 115 };
117 gpv { 116 gpv {
118 nvidia,pins = 117 nvidia,pins = "gpv", "slxa", "slxk";
119 nvidia,functio 118 nvidia,function = "pcie";
120 }; 119 };
121 hdint { 120 hdint {
122 nvidia,pins = 121 nvidia,pins = "hdint";
123 nvidia,functio 122 nvidia,function = "hdmi";
124 }; 123 };
125 i2cp { 124 i2cp {
126 nvidia,pins = 125 nvidia,pins = "i2cp";
127 nvidia,functio 126 nvidia,function = "i2cp";
128 }; 127 };
129 irrx { 128 irrx {
130 nvidia,pins = 129 nvidia,pins = "irrx", "irtx";
131 nvidia,functio 130 nvidia,function = "uartb";
132 }; 131 };
133 kbca { 132 kbca {
134 nvidia,pins = 133 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
135 "kbce" 134 "kbce", "kbcf";
136 nvidia,functio 135 nvidia,function = "kbc";
137 }; 136 };
138 lcsn { 137 lcsn {
139 nvidia,pins = 138 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
140 "ld3", 139 "ld3", "ld4", "ld5", "ld6", "ld7",
141 "ld8", 140 "ld8", "ld9", "ld10", "ld11", "ld12",
142 "ld13" 141 "ld13", "ld14", "ld15", "ld16", "ld17",
143 "ldc", 142 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
144 "lhs", 143 "lhs", "lm0", "lm1", "lpp", "lpw0",
145 "lpw1" 144 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
146 "lsda" 145 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
147 "lvs"; 146 "lvs";
148 nvidia,functio 147 nvidia,function = "displaya";
149 }; 148 };
150 owc { 149 owc {
151 nvidia,pins = 150 nvidia,pins = "owc", "uac";
152 nvidia,functio 151 nvidia,function = "rsvd2";
153 }; 152 };
154 pmc { 153 pmc {
155 nvidia,pins = 154 nvidia,pins = "pmc";
156 nvidia,functio 155 nvidia,function = "pwr_on";
157 }; 156 };
158 rm { 157 rm {
159 nvidia,pins = 158 nvidia,pins = "rm";
160 nvidia,functio 159 nvidia,function = "i2c1";
161 }; 160 };
162 sdb { 161 sdb {
163 nvidia,pins = 162 nvidia,pins = "sdb", "sdc", "sdd";
164 nvidia,functio 163 nvidia,function = "pwm";
165 }; 164 };
166 sdio1 { 165 sdio1 {
167 nvidia,pins = 166 nvidia,pins = "sdio1";
168 nvidia,functio 167 nvidia,function = "sdio1";
169 }; 168 };
170 slxc { 169 slxc {
171 nvidia,pins = 170 nvidia,pins = "slxc", "slxd";
172 nvidia,functio 171 nvidia,function = "sdio3";
173 }; 172 };
174 spdi { 173 spdi {
175 nvidia,pins = 174 nvidia,pins = "spdi", "spdo";
176 nvidia,functio 175 nvidia,function = "spdif";
177 }; 176 };
178 spia { 177 spia {
179 nvidia,pins = 178 nvidia,pins = "spia", "spib", "spic";
180 nvidia,functio 179 nvidia,function = "spi2";
181 }; 180 };
182 spid { 181 spid {
183 nvidia,pins = 182 nvidia,pins = "spid", "spie", "spif";
184 nvidia,functio 183 nvidia,function = "spi1";
185 }; 184 };
186 spig { 185 spig {
187 nvidia,pins = 186 nvidia,pins = "spig", "spih";
188 nvidia,functio 187 nvidia,function = "spi2_alt";
189 }; 188 };
190 uaa { 189 uaa {
191 nvidia,pins = 190 nvidia,pins = "uaa", "uab", "uda";
192 nvidia,functio 191 nvidia,function = "ulpi";
193 }; 192 };
194 uad { 193 uad {
195 nvidia,pins = 194 nvidia,pins = "uad";
196 nvidia,functio 195 nvidia,function = "irda";
197 }; 196 };
198 uca { 197 uca {
199 nvidia,pins = 198 nvidia,pins = "uca", "ucb";
200 nvidia,functio 199 nvidia,function = "uartc";
201 }; 200 };
202 conf_ata { 201 conf_ata {
203 nvidia,pins = 202 nvidia,pins = "ata", "atc", "atd", "ate",
204 "crtp" 203 "crtp", "dap2", "dap3", "dap4", "dta",
205 "dtb", !! 204 "dtb", "dtc", "dtd", "dte", "gmb",
206 "i2cp" !! 205 "gme", "i2cp", "pta", "slxc", "slxd",
207 "spdo" !! 206 "spdi", "spdo", "uda";
208 nvidia,pull = 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristat 208 nvidia,tristate = <TEGRA_PIN_ENABLE>;
210 }; 209 };
211 conf_atb { 210 conf_atb {
212 nvidia,pins = 211 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
213 "dte", !! 212 "gma", "gmc", "gmd", "gpu", "gpu7",
214 "gpu7" !! 213 "gpv", "sdio1", "slxa", "slxk", "uac";
215 "uac"; <<
216 nvidia,pull = 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
217 nvidia,tristat 215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
218 }; 216 };
219 conf_ck32 { 217 conf_ck32 {
220 nvidia,pins = 218 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
221 "pmcc" 219 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
222 nvidia,pull = 220 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 }; 221 };
224 conf_csus { 222 conf_csus {
225 nvidia,pins = 223 nvidia,pins = "csus", "spia", "spib",
226 "spid" 224 "spid", "spif";
227 nvidia,pull = 225 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
228 nvidia,tristat 226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
229 }; 227 };
230 conf_ddc { 228 conf_ddc {
231 nvidia,pins = 229 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
232 nvidia,pull = 230 nvidia,pull = <TEGRA_PIN_PULL_UP>;
233 nvidia,tristat 231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
234 }; 232 };
235 conf_hdint { 233 conf_hdint {
236 nvidia,pins = 234 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
237 "lpw1" 235 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
238 "lvp0" 236 "lvp0", "pmc";
239 nvidia,tristat 237 nvidia,tristate = <TEGRA_PIN_ENABLE>;
240 }; 238 };
241 conf_irrx { 239 conf_irrx {
242 nvidia,pins = 240 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
243 "kbcc" 241 "kbcc", "kbcd", "kbce", "kbcf", "owc",
244 "spic" 242 "spic", "spie", "spig", "spih", "uaa",
245 "uab", 243 "uab", "uad", "uca", "ucb";
246 nvidia,pull = 244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
247 nvidia,tristat 245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
248 }; 246 };
249 conf_lc { 247 conf_lc {
250 nvidia,pins = 248 nvidia,pins = "lc", "ls";
251 nvidia,pull = 249 nvidia,pull = <TEGRA_PIN_PULL_UP>;
252 }; 250 };
253 conf_ld0 { 251 conf_ld0 {
254 nvidia,pins = 252 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
255 "ld5", 253 "ld5", "ld6", "ld7", "ld8", "ld9",
256 "ld10" 254 "ld10", "ld11", "ld12", "ld13", "ld14",
257 "ld15" 255 "ld15", "ld16", "ld17", "ldi", "lhp0",
258 "lhp1" 256 "lhp1", "lhp2", "lhs", "lm0", "lpp",
259 "lpw0" 257 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
260 "lvs", 258 "lvs", "sdb";
261 nvidia,tristat 259 nvidia,tristate = <TEGRA_PIN_DISABLE>;
262 }; 260 };
263 conf_ld17_0 { 261 conf_ld17_0 {
264 nvidia,pins = 262 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
265 "ld23_ 263 "ld23_22";
266 nvidia,pull = 264 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
267 }; 265 };
268 conf_spif { 266 conf_spif {
269 nvidia,pins = 267 nvidia,pins = "spif";
270 nvidia,pull = 268 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
271 nvidia,tristat 269 nvidia,tristate = <TEGRA_PIN_DISABLE>;
272 }; 270 };
273 }; 271 };
274 }; 272 };
275 273
276 i2s@70002800 { 274 i2s@70002800 {
277 status = "okay"; 275 status = "okay";
278 }; 276 };
279 277
280 serial@70006000 { 278 serial@70006000 {
281 /delete-property/ dmas; <<
282 /delete-property/ dma-names; <<
283 status = "okay"; 279 status = "okay";
284 }; 280 };
285 281
286 dvi_ddc: i2c@7000c000 { 282 dvi_ddc: i2c@7000c000 {
287 status = "okay"; 283 status = "okay";
288 clock-frequency = <100000>; 284 clock-frequency = <100000>;
289 }; 285 };
290 286
291 spi@7000c380 { 287 spi@7000c380 {
292 status = "okay"; 288 status = "okay";
293 spi-max-frequency = <48000000> 289 spi-max-frequency = <48000000>;
294 290
295 flash@0 { 291 flash@0 {
296 compatible = "winbond, 292 compatible = "winbond,w25q80bl", "jedec,spi-nor";
297 reg = <0>; 293 reg = <0>;
298 spi-max-frequency = <4 294 spi-max-frequency = <48000000>;
299 }; 295 };
300 }; 296 };
301 297
302 hdmi_ddc: i2c@7000c400 { 298 hdmi_ddc: i2c@7000c400 {
303 status = "okay"; 299 status = "okay";
304 clock-frequency = <100000>; 300 clock-frequency = <100000>;
305 }; 301 };
306 302
307 i2c@7000c500 { 303 i2c@7000c500 {
308 status = "okay"; 304 status = "okay";
309 clock-frequency = <400000>; 305 clock-frequency = <400000>;
310 306
311 codec: codec@1a { 307 codec: codec@1a {
312 compatible = "ti,tlv32 308 compatible = "ti,tlv320aic23";
313 reg = <0x1a>; 309 reg = <0x1a>;
314 }; 310 };
315 311
316 rtc@56 { 312 rtc@56 {
317 compatible = "emmicro, 313 compatible = "emmicro,em3027";
318 reg = <0x56>; 314 reg = <0x56>;
319 }; 315 };
320 }; 316 };
321 317
322 pmc@7000e400 { 318 pmc@7000e400 {
323 nvidia,suspend-mode = <1>; 319 nvidia,suspend-mode = <1>;
324 nvidia,cpu-pwr-good-time = <50 320 nvidia,cpu-pwr-good-time = <5000>;
325 nvidia,cpu-pwr-off-time = <500 321 nvidia,cpu-pwr-off-time = <5000>;
326 nvidia,core-pwr-good-time = <3 322 nvidia,core-pwr-good-time = <3845 3845>;
327 nvidia,core-pwr-off-time = <38 323 nvidia,core-pwr-off-time = <3875>;
328 nvidia,sys-clock-req-active-hi 324 nvidia,sys-clock-req-active-high;
329 core-supply = <&vdd_core>; 325 core-supply = <&vdd_core>;
330 }; 326 };
331 327
332 pcie@80003000 { 328 pcie@80003000 {
333 status = "okay"; 329 status = "okay";
334 330
335 avdd-pex-supply = <&pci_vdd_re 331 avdd-pex-supply = <&pci_vdd_reg>;
336 vdd-pex-supply = <&pci_vdd_reg 332 vdd-pex-supply = <&pci_vdd_reg>;
337 avdd-pex-pll-supply = <&pci_vd 333 avdd-pex-pll-supply = <&pci_vdd_reg>;
338 avdd-plle-supply = <&pci_vdd_r 334 avdd-plle-supply = <&pci_vdd_reg>;
339 vddio-pex-clk-supply = <&pci_c 335 vddio-pex-clk-supply = <&pci_clk_reg>;
340 336
341 pci@1,0 { 337 pci@1,0 {
342 status = "okay"; 338 status = "okay";
343 }; 339 };
344 }; 340 };
345 341
346 usb@c5000000 { 342 usb@c5000000 {
347 status = "okay"; 343 status = "okay";
348 }; 344 };
349 345
350 usb-phy@c5000000 { 346 usb-phy@c5000000 {
351 status = "okay"; 347 status = "okay";
352 vbus-supply = <&vbus_reg>; 348 vbus-supply = <&vbus_reg>;
353 }; 349 };
354 350
355 usb@c5004000 { 351 usb@c5004000 {
356 status = "okay"; 352 status = "okay";
357 }; 353 };
358 354
359 usb-phy@c5004000 { 355 usb-phy@c5004000 {
360 status = "okay"; 356 status = "okay";
361 nvidia,phy-reset-gpio = <&gpio 357 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
362 GPIO_ACTIVE_LOW>; 358 GPIO_ACTIVE_LOW>;
363 }; 359 };
364 360
365 usb@c5008000 { 361 usb@c5008000 {
366 status = "okay"; 362 status = "okay";
367 }; 363 };
368 364
369 usb-phy@c5008000 { 365 usb-phy@c5008000 {
370 status = "okay"; 366 status = "okay";
371 }; 367 };
372 368
373 mmc@c8000000 { 369 mmc@c8000000 {
374 status = "okay"; 370 status = "okay";
375 broken-cd; 371 broken-cd;
376 bus-width = <4>; 372 bus-width = <4>;
377 }; 373 };
378 374
379 mmc@c8000600 { 375 mmc@c8000600 {
380 status = "okay"; 376 status = "okay";
381 cd-gpios = <&gpio TEGRA_GPIO(P 377 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
382 wp-gpios = <&gpio TEGRA_GPIO(P 378 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
383 bus-width = <4>; 379 bus-width = <4>;
384 }; 380 };
385 381
386 clk32k_in: clock-32k { 382 clk32k_in: clock-32k {
387 compatible = "fixed-clock"; 383 compatible = "fixed-clock";
388 clock-frequency = <32768>; 384 clock-frequency = <32768>;
389 #clock-cells = <0>; 385 #clock-cells = <0>;
390 }; 386 };
391 387
392 cpus { 388 cpus {
393 cpu0: cpu@0 { 389 cpu0: cpu@0 {
394 operating-points-v2 = 390 operating-points-v2 = <&cpu0_opp_table>;
395 }; 391 };
396 392
397 cpu@1 { 393 cpu@1 {
398 operating-points-v2 = 394 operating-points-v2 = <&cpu0_opp_table>;
399 }; 395 };
400 }; 396 };
401 397
402 gpio-keys { 398 gpio-keys {
403 compatible = "gpio-keys"; 399 compatible = "gpio-keys";
404 400
405 key-power { 401 key-power {
406 label = "Power"; 402 label = "Power";
407 gpios = <&gpio TEGRA_G 403 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
408 linux,code = <KEY_POWE 404 linux,code = <KEY_POWER>;
409 wakeup-source; 405 wakeup-source;
410 }; <<
411 }; <<
412 <<
413 leds { <<
414 compatible = "gpio-leds"; <<
415 <<
416 led-ds2 { <<
417 color = <LED_COLOR_ID_ <<
418 function = LED_FUNCTIO <<
419 function-enumerator = <<
420 gpios = <&gpio TEGRA_G <<
421 }; <<
422 <<
423 led-ds3 { <<
424 color = <LED_COLOR_ID_ <<
425 function = LED_FUNCTIO <<
426 function-enumerator = <<
427 gpios = <&gpio TEGRA_G <<
428 }; 406 };
429 }; 407 };
430 408
431 poweroff { 409 poweroff {
432 compatible = "gpio-poweroff"; 410 compatible = "gpio-poweroff";
433 gpios = <&gpio TEGRA_GPIO(X, 7 411 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
434 }; 412 };
435 413
436 hdmi_vdd_reg: regulator-hdmi { 414 hdmi_vdd_reg: regulator-hdmi {
437 compatible = "regulator-fixed" 415 compatible = "regulator-fixed";
438 regulator-name = "avdd_hdmi"; 416 regulator-name = "avdd_hdmi";
439 regulator-min-microvolt = <330 417 regulator-min-microvolt = <3300000>;
440 regulator-max-microvolt = <330 418 regulator-max-microvolt = <3300000>;
441 regulator-always-on; 419 regulator-always-on;
442 }; 420 };
443 421
444 hdmi_pll_reg: regulator-hdmipll { 422 hdmi_pll_reg: regulator-hdmipll {
445 compatible = "regulator-fixed" 423 compatible = "regulator-fixed";
446 regulator-name = "avdd_hdmi_pl 424 regulator-name = "avdd_hdmi_pll";
447 regulator-min-microvolt = <180 425 regulator-min-microvolt = <1800000>;
448 regulator-max-microvolt = <180 426 regulator-max-microvolt = <1800000>;
449 regulator-always-on; 427 regulator-always-on;
450 }; 428 };
451 429
452 vbus_reg: regulator-vbus { 430 vbus_reg: regulator-vbus {
453 compatible = "regulator-fixed" 431 compatible = "regulator-fixed";
454 regulator-name = "usb1_vbus"; 432 regulator-name = "usb1_vbus";
455 regulator-min-microvolt = <500 433 regulator-min-microvolt = <5000000>;
456 regulator-max-microvolt = <500 434 regulator-max-microvolt = <5000000>;
457 enable-active-high; 435 enable-active-high;
458 gpio = <&gpio TEGRA_GPIO(V, 2) 436 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
459 regulator-always-on; 437 regulator-always-on;
460 regulator-boot-on; 438 regulator-boot-on;
461 }; 439 };
462 440
463 pci_clk_reg: regulator-pciclk { 441 pci_clk_reg: regulator-pciclk {
464 compatible = "regulator-fixed" 442 compatible = "regulator-fixed";
465 regulator-name = "pci_clk"; 443 regulator-name = "pci_clk";
466 regulator-min-microvolt = <330 444 regulator-min-microvolt = <3300000>;
467 regulator-max-microvolt = <330 445 regulator-max-microvolt = <3300000>;
468 regulator-always-on; 446 regulator-always-on;
469 }; 447 };
470 448
471 pci_vdd_reg: regulator-pcivdd { 449 pci_vdd_reg: regulator-pcivdd {
472 compatible = "regulator-fixed" 450 compatible = "regulator-fixed";
473 regulator-name = "pci_vdd"; 451 regulator-name = "pci_vdd";
474 regulator-min-microvolt = <105 452 regulator-min-microvolt = <1050000>;
475 regulator-max-microvolt = <105 453 regulator-max-microvolt = <1050000>;
476 regulator-always-on; 454 regulator-always-on;
477 }; 455 };
478 456
479 vdd_core: regulator-core { 457 vdd_core: regulator-core {
480 compatible = "regulator-fixed" 458 compatible = "regulator-fixed";
481 regulator-name = "vdd_core"; 459 regulator-name = "vdd_core";
482 regulator-min-microvolt = <130 460 regulator-min-microvolt = <1300000>;
483 regulator-max-microvolt = <130 461 regulator-max-microvolt = <1300000>;
484 regulator-always-on; 462 regulator-always-on;
485 }; 463 };
486 464
487 sound { 465 sound {
488 compatible = "nvidia,tegra-aud 466 compatible = "nvidia,tegra-audio-trimslice";
489 nvidia,i2s-controller = <&tegr 467 nvidia,i2s-controller = <&tegra_i2s1>;
490 nvidia,audio-codec = <&codec>; 468 nvidia,audio-codec = <&codec>;
491 469
492 clocks = <&tegra_car TEGRA20_C 470 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
493 <&tegra_car TEGRA20_C 471 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
494 <&tegra_car TEGRA20_C 472 <&tegra_car TEGRA20_CLK_CDEV1>;
495 clock-names = "pll_a", "pll_a_ 473 clock-names = "pll_a", "pll_a_out0", "mclk";
496 }; 474 };
497 }; 475 };
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