1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 #include "tegra30.dtsi"
3
4 /*
5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.1A, V1.1B;
7 * 2GB: V1.1A, V1.1B
8 */
9 / {
10 memory@80000000 {
11 reg = <0x80000000 0x40000000>;
12 };
13
14 pcie@3000 {
15 status = "okay";
16 avdd-pexa-supply = <&vdd2_reg>
17 avdd-pexb-supply = <&vdd2_reg>
18 avdd-pex-pll-supply = <&vdd2_r
19 avdd-plle-supply = <&ldo6_reg>
20 hvdd-pex-supply = <®_module
21 vddio-pex-ctl-supply = <®_m
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
24
25 /* Apalis type specific */
26 pci@1,0 {
27 nvidia,num-lanes = <4>
28 };
29
30 /* Apalis PCIe */
31 pci@2,0 {
32 nvidia,num-lanes = <1>
33 };
34
35 /* I210/I211 Gigabit Ethernet
36 pci@3,0 {
37 status = "okay";
38 nvidia,num-lanes = <1>
39
40 ethernet@0,0 {
41 reg = <0 0 0 0
42 local-mac-addr
43 };
44 };
45 };
46
47 host1x@50000000 {
48 hdmi@54280000 {
49 nvidia,ddc-i2c-bus = <
50 nvidia,hpd-gpio =
51 <&gpio TEGRA_G
52 pll-supply = <®_1v8
53 vdd-supply = <®_3v3
54 };
55 };
56
57 pinmux@70000868 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&state_default>;
60
61 state_default: pinmux {
62 /* Analogue Audio (On-
63 clk1-out-pw4 {
64 nvidia,pins =
65 nvidia,functio
66 nvidia,pull =
67 nvidia,tristat
68 nvidia,enable-
69 };
70 dap3-fs-pp0 {
71 nvidia,pins =
72
73
74
75 nvidia,functio
76 nvidia,pull =
77 nvidia,tristat
78 };
79
80 /* Apalis BKL1_ON */
81 pv2 {
82 nvidia,pins =
83 nvidia,functio
84 nvidia,pull =
85 nvidia,tristat
86 nvidia,enable-
87 };
88
89 /* Apalis BKL1_PWM */
90 uart3-rts-n-pc0 {
91 nvidia,pins =
92 nvidia,functio
93 nvidia,pull =
94 nvidia,tristat
95 nvidia,enable-
96 };
97 /* BKL1_PWM_EN#, disab
98 uart3-cts-n-pa1 {
99 nvidia,pins =
100 nvidia,functio
101 nvidia,pull =
102 nvidia,tristat
103 nvidia,enable-
104 };
105
106 /* Apalis CAN1 on SPI6
107 spi2-cs0-n-px3 {
108 nvidia,pins =
109
110
111
112 nvidia,functio
113 nvidia,pull =
114 nvidia,tristat
115 };
116 /* CAN_INT1 */
117 spi2-cs1-n-pw2 {
118 nvidia,pins =
119 nvidia,functio
120 nvidia,pull =
121 nvidia,tristat
122 nvidia,enable-
123 };
124
125 /* Apalis CAN2 on SPI4
126 gmi-a16-pj7 {
127 nvidia,pins =
128
129
130
131 nvidia,functio
132 nvidia,pull =
133 nvidia,tristat
134 nvidia,enable-
135 };
136 /* CAN_INT2 */
137 spi2-cs2-n-pw3 {
138 nvidia,pins =
139 nvidia,functio
140 nvidia,pull =
141 nvidia,tristat
142 nvidia,enable-
143 };
144
145 /* Apalis Digital Audi
146 clk1-req-pee2 {
147 nvidia,pins =
148 nvidia,functio
149 nvidia,pull =
150 nvidia,tristat
151 };
152 clk2-out-pw5 {
153 nvidia,pins =
154 nvidia,functio
155 nvidia,pull =
156 nvidia,tristat
157 nvidia,enable-
158 };
159 dap1-fs-pn0 {
160 nvidia,pins =
161
162
163
164 nvidia,functio
165 nvidia,pull =
166 nvidia,tristat
167 };
168
169 /* Apalis GPIO */
170 kb-col0-pq0 {
171 nvidia,pins =
172
173
174
175
176
177
178
179 nvidia,functio
180 nvidia,pull =
181 nvidia,tristat
182 nvidia,enable-
183 };
184 /* Multiplexed and the
185 owr {
186 nvidia,pins =
187 nvidia,functio
188 nvidia,pull =
189 nvidia,tristat
190 nvidia,enable-
191 };
192
193 /* Apalis HDMI1 */
194 hdmi-cec-pee3 {
195 nvidia,pins =
196 nvidia,functio
197 nvidia,pull =
198 nvidia,tristat
199 nvidia,enable-
200 nvidia,open-dr
201 };
202 hdmi-int-pn7 {
203 nvidia,pins =
204 nvidia,functio
205 nvidia,pull =
206 nvidia,tristat
207 nvidia,enable-
208 };
209
210 /* Apalis I2C1 */
211 gen1-i2c-scl-pc4 {
212 nvidia,pins =
213
214 nvidia,functio
215 nvidia,pull =
216 nvidia,tristat
217 nvidia,enable-
218 nvidia,open-dr
219 };
220
221 /* Apalis I2C2 (DDC) *
222 ddc-scl-pv4 {
223 nvidia,pins =
224
225 nvidia,functio
226 nvidia,pull =
227 nvidia,tristat
228 nvidia,enable-
229 };
230
231 /* Apalis I2C3 (CAM) *
232 cam-i2c-scl-pbb1 {
233 nvidia,pins =
234
235 nvidia,functio
236 nvidia,pull =
237 nvidia,tristat
238 nvidia,enable-
239 nvidia,open-dr
240 };
241
242 /* Apalis LCD1 */
243 lcd-d0-pe0 {
244 nvidia,pins =
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272 nvidia,functio
273 nvidia,pull =
274 nvidia,tristat
275 nvidia,enable-
276 };
277
278 /* Apalis MMC1 */
279 sdmmc3-clk-pa6 {
280 nvidia,pins =
281 nvidia,functio
282 nvidia,pull =
283 nvidia,tristat
284 };
285 sdmmc3-dat0-pb7 {
286 nvidia,pins =
287
288
289
290
291
292
293
294
295 nvidia,functio
296 nvidia,pull =
297 nvidia,tristat
298 };
299 /* Apalis MMC1_CD# */
300 pv3 {
301 nvidia,pins =
302 nvidia,functio
303 nvidia,pull =
304 nvidia,tristat
305 nvidia,enable-
306 };
307
308 /* Apalis Parallel Cam
309 cam-mclk-pcc0 {
310 nvidia,pins =
311 nvidia,functio
312 nvidia,pull =
313 nvidia,tristat
314 nvidia,enable-
315 };
316 vi-vsync-pd6 {
317 nvidia,pins =
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332 nvidia,functio
333 nvidia,pull =
334 nvidia,tristat
335 nvidia,enable-
336 };
337 /* Multiplexed and the
338 kb-col2-pq2 {
339 nvidia,pins =
340
341
342
343 nvidia,functio
344 nvidia,pull =
345 nvidia,tristat
346 nvidia,enable-
347 };
348 kb-row0-pr0 {
349 nvidia,pins =
350
351
352
353 nvidia,functio
354 nvidia,pull =
355 nvidia,tristat
356 nvidia,enable-
357 };
358 kb-row5-pr5 {
359 nvidia,pins =
360
361
362 nvidia,functio
363 nvidia,pull =
364 nvidia,tristat
365 nvidia,enable-
366 };
367 /*
368 * VI level-shifter di
369 * (pull-down => defau
370 */
371 vi-mclk-pt1 {
372 nvidia,pins =
373 nvidia,functio
374 nvidia,pull =
375 nvidia,tristat
376 nvidia,enable-
377 };
378
379 /* Apalis PWM1 */
380 pu6 {
381 nvidia,pins =
382 nvidia,functio
383 nvidia,pull =
384 nvidia,tristat
385 };
386
387 /* Apalis PWM2 */
388 pu5 {
389 nvidia,pins =
390 nvidia,functio
391 nvidia,pull =
392 nvidia,tristat
393 };
394
395 /* Apalis PWM3 */
396 pu4 {
397 nvidia,pins =
398 nvidia,functio
399 nvidia,pull =
400 nvidia,tristat
401 };
402
403 /* Apalis PWM4 */
404 pu3 {
405 nvidia,pins =
406 nvidia,functio
407 nvidia,pull =
408 nvidia,tristat
409 };
410
411 /* Apalis RESET_MOCI#
412 gmi-rst-n-pi4 {
413 nvidia,pins =
414 nvidia,functio
415 nvidia,pull =
416 nvidia,tristat
417 };
418
419 /* Apalis SATA1_ACT# *
420 pex-l0-prsnt-n-pdd0 {
421 nvidia,pins =
422 nvidia,functio
423 nvidia,pull =
424 nvidia,tristat
425 nvidia,enable-
426 };
427
428 /* Apalis SD1 */
429 sdmmc1-clk-pz0 {
430 nvidia,pins =
431 nvidia,functio
432 nvidia,pull =
433 nvidia,tristat
434 };
435 sdmmc1-cmd-pz1 {
436 nvidia,pins =
437
438
439
440
441 nvidia,functio
442 nvidia,pull =
443 nvidia,tristat
444 };
445 /* Apalis SD1_CD# */
446 clk2-req-pcc5 {
447 nvidia,pins =
448 nvidia,functio
449 nvidia,pull =
450 nvidia,tristat
451 nvidia,enable-
452 };
453
454 /* Apalis SPDIF1 */
455 spdif-out-pk5 {
456 nvidia,pins =
457
458 nvidia,functio
459 nvidia,pull =
460 nvidia,tristat
461 nvidia,enable-
462 };
463
464 /* Apalis SPI1 */
465 spi1-sck-px5 {
466 nvidia,pins =
467
468
469
470 nvidia,functio
471 nvidia,pull =
472 nvidia,tristat
473 };
474
475 /* Apalis SPI2 */
476 lcd-sck-pz4 {
477 nvidia,pins =
478
479
480
481 nvidia,functio
482 nvidia,pull =
483 nvidia,tristat
484 };
485
486 /*
487 * Apalis TS (Low-spee
488 * pins may be used as
489 */
490 kb-col5-pq5 {
491 nvidia,pins =
492 nvidia,functio
493 nvidia,pull =
494 nvidia,tristat
495 nvidia,enable-
496 };
497 kb-col6-pq6 {
498 nvidia,pins =
499
500
501
502 nvidia,functio
503 nvidia,pull =
504 nvidia,tristat
505 nvidia,enable-
506 };
507
508 /* Apalis UART1 */
509 ulpi-data0 {
510 nvidia,pins =
511
512
513
514
515
516
517
518 nvidia,functio
519 nvidia,pull =
520 nvidia,tristat
521 };
522
523 /* Apalis UART2 */
524 ulpi-clk-py0 {
525 nvidia,pins =
526
527
528
529 nvidia,functio
530 nvidia,pull =
531 nvidia,tristat
532 };
533
534 /* Apalis UART3 */
535 uart2-rxd-pc3 {
536 nvidia,pins =
537
538 nvidia,functio
539 nvidia,pull =
540 nvidia,tristat
541 };
542
543 /* Apalis UART4 */
544 uart3-rxd-pw7 {
545 nvidia,pins =
546
547 nvidia,functio
548 nvidia,pull =
549 nvidia,tristat
550 };
551
552 /* Apalis USBH_EN */
553 pex-l0-rst-n-pdd1 {
554 nvidia,pins =
555 nvidia,functio
556 nvidia,pull =
557 nvidia,tristat
558 nvidia,enable-
559 };
560
561 /* Apalis USBH_OC# */
562 pex-l0-clkreq-n-pdd2 {
563 nvidia,pins =
564 nvidia,functio
565 nvidia,pull =
566 nvidia,tristat
567 nvidia,enable-
568 };
569
570 /* Apalis USBO1_EN */
571 gen2-i2c-scl-pt5 {
572 nvidia,pins =
573 nvidia,functio
574 nvidia,open-dr
575 nvidia,pull =
576 nvidia,tristat
577 };
578
579 /* Apalis USBO1_OC# */
580 gen2-i2c-sda-pt6 {
581 nvidia,pins =
582 nvidia,functio
583 nvidia,open-dr
584 nvidia,pull =
585 nvidia,tristat
586 nvidia,enable-
587 };
588
589 /* Apalis VGA1 not sup
590 crt-hsync-pv6 {
591 nvidia,pins =
592
593 nvidia,functio
594 nvidia,pull =
595 nvidia,tristat
596 nvidia,enable-
597 };
598
599 /* Apalis WAKE1_MICO *
600 pv1 {
601 nvidia,pins =
602 nvidia,functio
603 nvidia,pull =
604 nvidia,tristat
605 nvidia,enable-
606 };
607
608 /* eMMC (On-module) */
609 sdmmc4-clk-pcc4 {
610 nvidia,pins =
611
612
613 nvidia,functio
614 nvidia,pull =
615 nvidia,tristat
616 nvidia,enable-
617 };
618 sdmmc4-dat0-paa0 {
619 nvidia,pins =
620
621
622
623
624
625
626
627 nvidia,functio
628 nvidia,pull =
629 nvidia,tristat
630 nvidia,enable-
631 };
632
633 /* EN_+3.3_SDMMC3 */
634 uart2-cts-n-pj5 {
635 nvidia,pins =
636 nvidia,functio
637 nvidia,pull =
638 nvidia,tristat
639 nvidia,enable-
640 };
641
642 /* LAN i210/i211 DEV_O
643 pex-l2-prsnt-n-pdd7 {
644 nvidia,pins =
645
646 nvidia,functio
647 nvidia,pull =
648 nvidia,tristat
649 nvidia,enable-
650 };
651 /* LAN i210/i211 PE_WA
652 pex-wake-n-pdd3 {
653 nvidia,pins =
654
655 nvidia,functio
656 nvidia,pull =
657 nvidia,tristat
658 nvidia,enable-
659 };
660 /* LAN i210/i211 SMB_A
661 sys-clk-req-pz5 {
662 nvidia,pins =
663 nvidia,functio
664 nvidia,pull =
665 nvidia,tristat
666 nvidia,enable-
667 };
668
669 /* LVDS Transceiver Co
670 pbb0 {
671 nvidia,pins =
672
673
674
675 nvidia,functio
676 nvidia,pull =
677 nvidia,tristat
678 nvidia,enable-
679 };
680 pbb3 {
681 nvidia,pins =
682
683
684
685 nvidia,functio
686 nvidia,pull =
687 nvidia,tristat
688 nvidia,enable-
689 };
690
691 /* Not connected and t
692 clk-32k-out-pa0 {
693 nvidia,pins =
694
695
696
697
698
699
700 nvidia,functio
701 nvidia,pull =
702 nvidia,tristat
703 nvidia,enable-
704 };
705 dap2-fs-pa2 {
706 nvidia,pins =
707
708
709
710
711
712
713
714
715
716 nvidia,functio
717 nvidia,pull =
718 nvidia,tristat
719 nvidia,enable-
720 };
721 gmi-ad0-pg0 {
722 nvidia,pins =
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750 nvidia,functio
751 nvidia,pull =
752 nvidia,tristat
753 nvidia,enable-
754 };
755 gmi-cs0-n-pj0 {
756 nvidia,pins =
757
758
759 nvidia,functio
760 nvidia,pull =
761 nvidia,tristat
762 nvidia,enable-
763 };
764 gmi-cs6-n-pi3 {
765 nvidia,pins =
766 nvidia,functio
767 nvidia,pull =
768 nvidia,tristat
769 nvidia,enable-
770 };
771 gmi-cs7-n-pi6 {
772 nvidia,pins =
773 nvidia,functio
774 nvidia,pull =
775 nvidia,tristat
776 nvidia,enable-
777 };
778 lcd-pwr0-pb2 {
779 nvidia,pins =
780
781
782 nvidia,functio
783 nvidia,pull =
784 nvidia,tristat
785 nvidia,enable-
786 };
787 uart2-rts-n-pj6 {
788 nvidia,pins =
789 nvidia,functio
790 nvidia,pull =
791 nvidia,tristat
792 nvidia,enable-
793 };
794
795 /* Power I2C (On-modul
796 pwr-i2c-scl-pz6 {
797 nvidia,pins =
798
799 nvidia,functio
800 nvidia,pull =
801 nvidia,tristat
802 nvidia,enable-
803 nvidia,open-dr
804 };
805
806 /*
807 * THERMD_ALERT#, unla
808 * temperature sensor
809 * now
810 */
811 lcd-dc1-pd2 {
812 nvidia,pins =
813 nvidia,functio
814 nvidia,pull =
815 nvidia,tristat
816 nvidia,enable-
817 };
818
819 /* TOUCH_PEN_INT# (On-
820 pv0 {
821 nvidia,pins =
822 nvidia,functio
823 nvidia,pull =
824 nvidia,tristat
825 nvidia,enable-
826 };
827 };
828 };
829
830 serial@70006040 {
831 compatible = "nvidia,tegra30-h
832 reset-names = "serial";
833 /delete-property/ reg-shift;
834 };
835
836 serial@70006200 {
837 compatible = "nvidia,tegra30-h
838 reset-names = "serial";
839 /delete-property/ reg-shift;
840 };
841
842 serial@70006300 {
843 compatible = "nvidia,tegra30-h
844 reset-names = "serial";
845 /delete-property/ reg-shift;
846 };
847
848 hdmi_ddc: i2c@7000c700 {
849 clock-frequency = <10000>;
850 };
851
852 /*
853 * PWR_I2C: power I2C to audio codec,
854 * touch screen controller
855 */
856 i2c@7000d000 {
857 status = "okay";
858 clock-frequency = <100000>;
859
860 /* SGTL5000 audio codec */
861 sgtl5000: codec@a {
862 compatible = "fsl,sgtl
863 reg = <0x0a>;
864 #sound-dai-cells = <0>
865 VDDA-supply = <®_mo
866 VDDD-supply = <®_1v
867 VDDIO-supply = <®_m
868 clocks = <&tegra_car T
869 };
870
871 pmic: pmic@2d {
872 compatible = "ti,tps65
873 reg = <0x2d>;
874
875 interrupts = <GIC_SPI
876 #interrupt-cells = <2>
877 interrupt-controller;
878
879 ti,system-power-contro
880
881 #gpio-cells = <2>;
882 gpio-controller;
883
884 vcc1-supply = <®_mo
885 vcc2-supply = <®_mo
886 vcc3-supply = <®_1v
887 vcc4-supply = <®_mo
888 vcc5-supply = <®_mo
889 vcc6-supply = <®_1v
890 vcc7-supply = <®_5v
891 vccio-supply = <®_m
892
893 regulators {
894 vdd1_reg: vdd1
895 regula
896 regula
897 regula
898 regula
899 };
900
901 vdd2_reg: vdd2
902 regula
903 regula
904 regula
905 };
906
907 vddctrl_reg: v
908 regula
909 regula
910 regula
911 regula
912 };
913
914 reg_1v8_vio: v
915 regula
916 regula
917 regula
918 regula
919 };
920
921 /*
922 * 1.8 volt +V
923 * is off
924 */
925 vddio_sdmmc_1v
926 regula
927 regula
928 regula
929 regula
930 };
931
932 /*
933 * EN_+V3.3 sw
934 * +V3.3_AUDIO
935 * see also +V
936 */
937 ldo2_reg: ldo2
938 regula
939 regula
940 regula
941 regula
942 };
943
944 ldo3_reg: ldo3
945 regula
946 regula
947 regula
948 };
949
950 ldo4_reg: ldo4
951 regula
952 regula
953 regula
954 regula
955 };
956
957 /*
958 * +V2.8_AVDD_
959 * only requir
960 */
961 ldo5_reg: ldo5
962 regula
963 regula
964 regula
965 regula
966 };
967
968 /*
969 * +V1.05_AVDD
970 * but LDO6 ca
971 * granularity
972 */
973 ldo6_reg: ldo6
974 regula
975 regula
976 regula
977 };
978
979 ldo7_reg: ldo7
980 regula
981 regula
982 regula
983 regula
984 };
985
986 ldo8_reg: ldo8
987 regula
988 regula
989 regula
990 regula
991 };
992 };
993 };
994
995 /* STMPE811 touch screen contr
996 touchscreen@41 {
997 compatible = "st,stmpe
998 reg = <0x41>;
999 irq-gpio = <&gpio TEGR
1000 id = <0>;
1001 blocks = <0x5>;
1002 irq-trigger = <0x1>;
1003 /* 3.25 MHz ADC clock
1004 st,adc-freq = <1>;
1005 /* 12-bit ADC */
1006 st,mod-12b = <1>;
1007 /* internal ADC refer
1008 st,ref-sel = <0>;
1009 /* ADC converstion ti
1010 st,sample-time = <4>;
1011
1012 stmpe_adc {
1013 compatible =
1014 /* forbid to
1015 st,norequest-
1016 };
1017
1018 stmpe_touchscreen {
1019 compatible =
1020 /* 8 sample a
1021 st,ave-ctrl =
1022 /* 7 length f
1023 st,fraction-z
1024 /*
1025 * 50 mA typi
1026 * current li
1027 */
1028 st,i-drive =
1029 /* 1 ms panel
1030 st,settling =
1031 /* 5 ms touch
1032 st,touch-det-
1033 };
1034 };
1035
1036 /*
1037 * LM95245 temperature sensor
1038 * Note: OVERT1# directly con
1039 */
1040 temp-sensor@4c {
1041 compatible = "nationa
1042 reg = <0x4c>;
1043 };
1044
1045 /* SW: +V1.2_VDD_CORE */
1046 regulator@60 {
1047 compatible = "ti,tps6
1048 reg = <0x60>;
1049
1050 regulator-name = "tps
1051 regulator-min-microvo
1052 regulator-max-microvo
1053 regulator-boot-on;
1054 regulator-always-on;
1055 };
1056 };
1057
1058 /* SPI4: CAN2 */
1059 spi@7000da00 {
1060 status = "okay";
1061 spi-max-frequency = <10000000
1062
1063 can@1 {
1064 compatible = "microch
1065 reg = <1>;
1066 clocks = <&clk16m>;
1067 interrupt-parent = <&
1068 interrupts = <TEGRA_G
1069 spi-max-frequency = <
1070 };
1071 };
1072
1073 /* SPI6: CAN1 */
1074 spi@7000de00 {
1075 status = "okay";
1076 spi-max-frequency = <10000000
1077
1078 can@0 {
1079 compatible = "microch
1080 reg = <0>;
1081 clocks = <&clk16m>;
1082 interrupt-parent = <&
1083 interrupts = <TEGRA_G
1084 spi-max-frequency = <
1085 };
1086 };
1087
1088 pmc@7000e400 {
1089 nvidia,invert-interrupt;
1090 nvidia,suspend-mode = <1>;
1091 nvidia,cpu-pwr-good-time = <5
1092 nvidia,cpu-pwr-off-time = <50
1093 nvidia,core-pwr-good-time = <
1094 nvidia,core-pwr-off-time = <0
1095 nvidia,core-power-req-active-
1096 nvidia,sys-clock-req-active-h
1097
1098 /* Set DEV_OFF bit in DCDC co
1099 i2c-thermtrip {
1100 nvidia,i2c-controller
1101 nvidia,bus-addr = <0x
1102 nvidia,reg-addr = <0x
1103 nvidia,reg-data = <0x
1104 };
1105 };
1106
1107 hda@70030000 {
1108 status = "okay";
1109 };
1110
1111 ahub@70080000 {
1112 i2s@70080500 {
1113 status = "okay";
1114 };
1115 };
1116
1117 /* eMMC */
1118 mmc@78000600 {
1119 status = "okay";
1120 bus-width = <8>;
1121 non-removable;
1122 vmmc-supply = <®_module_3v
1123 vqmmc-supply = <®_1v8_vio>
1124 mmc-ddr-1_8v;
1125 };
1126
1127 clk16m: clock-osc4 {
1128 compatible = "fixed-clock";
1129 #clock-cells = <0>;
1130 clock-frequency = <16000000>;
1131 };
1132
1133 clk32k_in: clock-xtal1 {
1134 compatible = "fixed-clock";
1135 #clock-cells = <0>;
1136 clock-frequency = <32768>;
1137 };
1138
1139 reg_1v8_avdd_hdmi_pll: regulator-1v8-
1140 compatible = "regulator-fixed
1141 regulator-name = "+V1.8_AVDD_
1142 regulator-min-microvolt = <18
1143 regulator-max-microvolt = <18
1144 enable-active-high;
1145 gpio = <&pmic 6 GPIO_ACTIVE_H
1146 vin-supply = <®_1v8_vio>;
1147 };
1148
1149 reg_3v3_avdd_hdmi: regulator-3v3-avdd
1150 compatible = "regulator-fixed
1151 regulator-name = "+V3.3_AVDD_
1152 regulator-min-microvolt = <33
1153 regulator-max-microvolt = <33
1154 enable-active-high;
1155 gpio = <&pmic 6 GPIO_ACTIVE_H
1156 vin-supply = <®_module_3v3
1157 };
1158
1159 reg_5v0_charge_pump: regulator-5v0-ch
1160 compatible = "regulator-fixed
1161 regulator-name = "+V5.0";
1162 regulator-min-microvolt = <50
1163 regulator-max-microvolt = <50
1164 regulator-always-on;
1165 };
1166
1167 reg_module_3v3: regulator-module-3v3
1168 compatible = "regulator-fixed
1169 regulator-name = "+V3.3";
1170 regulator-min-microvolt = <33
1171 regulator-max-microvolt = <33
1172 regulator-always-on;
1173 };
1174
1175 reg_module_3v3_audio: regulator-modul
1176 compatible = "regulator-fixed
1177 regulator-name = "+V3.3_AUDIO
1178 regulator-min-microvolt = <33
1179 regulator-max-microvolt = <33
1180 regulator-always-on;
1181 };
1182
1183 sound {
1184 compatible = "toradex,tegra-a
1185 "nvidia,tegra-au
1186 nvidia,model = "Toradex Apali
1187 nvidia,audio-routing =
1188 "Headphone Jack", "HP
1189 "LINE_IN", "Line In J
1190 "MIC_IN", "Mic Jack";
1191 nvidia,i2s-controller = <&teg
1192 nvidia,audio-codec = <&sgtl50
1193 clocks = <&tegra_car TEGRA30_
1194 <&tegra_car TEGRA30_
1195 <&tegra_pmc TEGRA_PM
1196 clock-names = "pll_a", "pll_a
1197
1198 assigned-clocks = <&tegra_car
1199 <&tegra_pmc
1200
1201 assigned-clock-parents = <&te
1202 <&te
1203 };
1204 };
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TOMOYO® is a registered trademark of NTT DATA CORPORATION.