1 // SPDX-License-Identifier: GPL-2.0 OR MIT 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 #include "tegra30.dtsi" 2 #include "tegra30.dtsi"
3 3
4 /* 4 /*
5 * Toradex Apalis T30 Module Device Tree 5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.1A, V1.1B; 6 * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
7 * 2GB: V1.1A, V1.1B 7 * 2GB: V1.1A, V1.1B
8 */ 8 */
9 / { 9 / {
10 memory@80000000 { 10 memory@80000000 {
11 reg = <0x80000000 0x40000000>; 11 reg = <0x80000000 0x40000000>;
12 }; 12 };
13 13
14 pcie@3000 { 14 pcie@3000 {
15 status = "okay"; 15 status = "okay";
16 avdd-pexa-supply = <&vdd2_reg> 16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg> 17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_r 18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg> 19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <®_module 20 hvdd-pex-supply = <®_module_3v3>;
21 vddio-pex-ctl-supply = <®_m 21 vddio-pex-ctl-supply = <®_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>; 22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>; 23 vdd-pexb-supply = <&vdd2_reg>;
24 24
25 /* Apalis type specific */ 25 /* Apalis type specific */
26 pci@1,0 { 26 pci@1,0 {
27 nvidia,num-lanes = <4> 27 nvidia,num-lanes = <4>;
28 }; 28 };
29 29
30 /* Apalis PCIe */ 30 /* Apalis PCIe */
31 pci@2,0 { 31 pci@2,0 {
32 nvidia,num-lanes = <1> 32 nvidia,num-lanes = <1>;
33 }; 33 };
34 34
35 /* I210/I211 Gigabit Ethernet 35 /* I210/I211 Gigabit Ethernet Controller (on-module) */
36 pci@3,0 { 36 pci@3,0 {
37 status = "okay"; 37 status = "okay";
38 nvidia,num-lanes = <1> 38 nvidia,num-lanes = <1>;
39 39
40 ethernet@0,0 { 40 ethernet@0,0 {
41 reg = <0 0 0 0 41 reg = <0 0 0 0 0>;
42 local-mac-addr 42 local-mac-address = [00 00 00 00 00 00];
43 }; 43 };
44 }; 44 };
45 }; 45 };
46 46
47 host1x@50000000 { 47 host1x@50000000 {
48 hdmi@54280000 { 48 hdmi@54280000 {
49 nvidia,ddc-i2c-bus = < 49 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
50 nvidia,hpd-gpio = 50 nvidia,hpd-gpio =
51 <&gpio TEGRA_G 51 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
52 pll-supply = <®_1v8 52 pll-supply = <®_1v8_avdd_hdmi_pll>;
53 vdd-supply = <®_3v3 53 vdd-supply = <®_3v3_avdd_hdmi>;
54 }; 54 };
55 }; 55 };
56 56
57 pinmux@70000868 { 57 pinmux@70000868 {
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 pinctrl-0 = <&state_default>; 59 pinctrl-0 = <&state_default>;
60 60
61 state_default: pinmux { 61 state_default: pinmux {
62 /* Analogue Audio (On- 62 /* Analogue Audio (On-module) */
63 clk1-out-pw4 { 63 clk1-out-pw4 {
64 nvidia,pins = 64 nvidia,pins = "clk1_out_pw4";
65 nvidia,functio 65 nvidia,function = "extperiph1";
66 nvidia,pull = 66 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristat 67 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 nvidia,enable- 68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
69 }; 69 };
70 dap3-fs-pp0 { 70 dap3-fs-pp0 {
71 nvidia,pins = 71 nvidia,pins = "dap3_fs_pp0",
72 72 "dap3_sclk_pp3",
73 73 "dap3_din_pp1",
74 74 "dap3_dout_pp2";
75 nvidia,functio 75 nvidia,function = "i2s2";
76 nvidia,pull = 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77 nvidia,tristat 77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
78 }; 78 };
79 79
80 /* Apalis BKL1_ON */ 80 /* Apalis BKL1_ON */
81 pv2 { 81 pv2 {
82 nvidia,pins = 82 nvidia,pins = "pv2";
83 nvidia,functio 83 nvidia,function = "rsvd4";
84 nvidia,pull = 84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristat 85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 nvidia,enable- 86 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
87 }; 87 };
88 88
89 /* Apalis BKL1_PWM */ 89 /* Apalis BKL1_PWM */
90 uart3-rts-n-pc0 { 90 uart3-rts-n-pc0 {
91 nvidia,pins = 91 nvidia,pins = "uart3_rts_n_pc0";
92 nvidia,functio 92 nvidia,function = "pwm0";
93 nvidia,pull = 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristat 94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
95 nvidia,enable- 95 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
96 }; 96 };
97 /* BKL1_PWM_EN#, disab 97 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
98 uart3-cts-n-pa1 { 98 uart3-cts-n-pa1 {
99 nvidia,pins = 99 nvidia,pins = "uart3_cts_n_pa1";
100 nvidia,functio 100 nvidia,function = "rsvd2";
101 nvidia,pull = 101 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristat 102 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 nvidia,enable- 103 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
104 }; 104 };
105 105
106 /* Apalis CAN1 on SPI6 106 /* Apalis CAN1 on SPI6 */
107 spi2-cs0-n-px3 { 107 spi2-cs0-n-px3 {
108 nvidia,pins = 108 nvidia,pins = "spi2_cs0_n_px3",
109 109 "spi2_miso_px1",
110 110 "spi2_mosi_px0",
111 111 "spi2_sck_px2";
112 nvidia,functio 112 nvidia,function = "spi6";
113 nvidia,pull = 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristat 114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 }; 115 };
116 /* CAN_INT1 */ 116 /* CAN_INT1 */
117 spi2-cs1-n-pw2 { 117 spi2-cs1-n-pw2 {
118 nvidia,pins = 118 nvidia,pins = "spi2_cs1_n_pw2";
119 nvidia,functio 119 nvidia,function = "spi3";
120 nvidia,pull = 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristat 121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,enable- 122 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
123 }; 123 };
124 124
125 /* Apalis CAN2 on SPI4 125 /* Apalis CAN2 on SPI4 */
126 gmi-a16-pj7 { 126 gmi-a16-pj7 {
127 nvidia,pins = 127 nvidia,pins = "gmi_a16_pj7",
128 128 "gmi_a17_pb0",
129 129 "gmi_a18_pb1",
130 130 "gmi_a19_pk7";
131 nvidia,functio 131 nvidia,function = "spi4";
132 nvidia,pull = 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristat 133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 nvidia,enable- 134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135 }; 135 };
136 /* CAN_INT2 */ 136 /* CAN_INT2 */
137 spi2-cs2-n-pw3 { 137 spi2-cs2-n-pw3 {
138 nvidia,pins = 138 nvidia,pins = "spi2_cs2_n_pw3";
139 nvidia,functio 139 nvidia,function = "spi3";
140 nvidia,pull = 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141 nvidia,tristat 141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
142 nvidia,enable- 142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143 }; 143 };
144 144
145 /* Apalis Digital Audi 145 /* Apalis Digital Audio */
146 clk1-req-pee2 { 146 clk1-req-pee2 {
147 nvidia,pins = 147 nvidia,pins = "clk1_req_pee2";
148 nvidia,functio 148 nvidia,function = "hda";
149 nvidia,pull = 149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristat 150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 }; 151 };
152 clk2-out-pw5 { 152 clk2-out-pw5 {
153 nvidia,pins = 153 nvidia,pins = "clk2_out_pw5";
154 nvidia,functio 154 nvidia,function = "extperiph2";
155 nvidia,pull = 155 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
156 nvidia,tristat 156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
157 nvidia,enable- 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
158 }; 158 };
159 dap1-fs-pn0 { 159 dap1-fs-pn0 {
160 nvidia,pins = 160 nvidia,pins = "dap1_fs_pn0",
161 161 "dap1_din_pn1",
162 162 "dap1_dout_pn2",
163 163 "dap1_sclk_pn3";
164 nvidia,functio 164 nvidia,function = "hda";
165 nvidia,pull = 165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristat 166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 }; 167 };
168 168
169 /* Apalis GPIO */ 169 /* Apalis GPIO */
170 kb-col0-pq0 { 170 kb-col0-pq0 {
171 nvidia,pins = 171 nvidia,pins = "kb_col0_pq0",
172 172 "kb_col1_pq1",
173 173 "kb_row10_ps2",
174 174 "kb_row11_ps3",
175 175 "kb_row12_ps4",
176 176 "kb_row13_ps5",
177 177 "kb_row14_ps6",
178 178 "kb_row15_ps7";
179 nvidia,functio 179 nvidia,function = "kbc";
180 nvidia,pull = 180 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristat 181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 nvidia,enable- 182 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
183 }; 183 };
184 /* Multiplexed and the 184 /* Multiplexed and therefore disabled */
185 owr { 185 owr {
186 nvidia,pins = 186 nvidia,pins = "owr";
187 nvidia,functio 187 nvidia,function = "rsvd3";
188 nvidia,pull = 188 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
189 nvidia,tristat 189 nvidia,tristate = <TEGRA_PIN_ENABLE>;
190 nvidia,enable- 190 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
191 }; 191 };
192 192
193 /* Apalis HDMI1 */ 193 /* Apalis HDMI1 */
194 hdmi-cec-pee3 { 194 hdmi-cec-pee3 {
195 nvidia,pins = 195 nvidia,pins = "hdmi_cec_pee3";
196 nvidia,functio 196 nvidia,function = "cec";
197 nvidia,pull = 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristat 198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 nvidia,enable- 199 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
200 nvidia,open-dr 200 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
201 }; 201 };
202 hdmi-int-pn7 { 202 hdmi-int-pn7 {
203 nvidia,pins = 203 nvidia,pins = "hdmi_int_pn7";
204 nvidia,functio 204 nvidia,function = "hdmi";
205 nvidia,pull = 205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristat 206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 nvidia,enable- 207 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
208 }; 208 };
209 209
210 /* Apalis I2C1 */ 210 /* Apalis I2C1 */
211 gen1-i2c-scl-pc4 { 211 gen1-i2c-scl-pc4 {
212 nvidia,pins = 212 nvidia,pins = "gen1_i2c_scl_pc4",
213 213 "gen1_i2c_sda_pc5";
214 nvidia,functio 214 nvidia,function = "i2c1";
215 nvidia,pull = 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216 nvidia,tristat 216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 nvidia,enable- 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218 nvidia,open-dr 218 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
219 }; 219 };
220 220
221 /* Apalis I2C2 (DDC) * 221 /* Apalis I2C2 (DDC) */
222 ddc-scl-pv4 { 222 ddc-scl-pv4 {
223 nvidia,pins = 223 nvidia,pins = "ddc_scl_pv4",
224 224 "ddc_sda_pv5";
225 nvidia,functio 225 nvidia,function = "i2c4";
226 nvidia,pull = 226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristat 227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 nvidia,enable- 228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
229 }; 229 };
230 230
231 /* Apalis I2C3 (CAM) * 231 /* Apalis I2C3 (CAM) */
232 cam-i2c-scl-pbb1 { 232 cam-i2c-scl-pbb1 {
233 nvidia,pins = 233 nvidia,pins = "cam_i2c_scl_pbb1",
234 234 "cam_i2c_sda_pbb2";
235 nvidia,functio 235 nvidia,function = "i2c3";
236 nvidia,pull = 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
237 nvidia,tristat 237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
238 nvidia,enable- 238 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
239 nvidia,open-dr 239 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
240 }; 240 };
241 241
242 /* Apalis LCD1 */ 242 /* Apalis LCD1 */
243 lcd-d0-pe0 { 243 lcd-d0-pe0 {
244 nvidia,pins = 244 nvidia,pins = "lcd_d0_pe0",
245 245 "lcd_d1_pe1",
246 246 "lcd_d2_pe2",
247 247 "lcd_d3_pe3",
248 248 "lcd_d4_pe4",
249 249 "lcd_d5_pe5",
250 250 "lcd_d6_pe6",
251 251 "lcd_d7_pe7",
252 252 "lcd_d8_pf0",
253 253 "lcd_d9_pf1",
254 254 "lcd_d10_pf2",
255 255 "lcd_d11_pf3",
256 256 "lcd_d12_pf4",
257 257 "lcd_d13_pf5",
258 258 "lcd_d14_pf6",
259 259 "lcd_d15_pf7",
260 260 "lcd_d16_pm0",
261 261 "lcd_d17_pm1",
262 262 "lcd_d18_pm2",
263 263 "lcd_d19_pm3",
264 264 "lcd_d20_pm4",
265 265 "lcd_d21_pm5",
266 266 "lcd_d22_pm6",
267 267 "lcd_d23_pm7",
268 268 "lcd_de_pj1",
269 269 "lcd_hsync_pj3",
270 270 "lcd_pclk_pb3",
271 271 "lcd_vsync_pj4";
272 nvidia,functio 272 nvidia,function = "displaya";
273 nvidia,pull = 273 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
274 nvidia,tristat 274 nvidia,tristate = <TEGRA_PIN_DISABLE>;
275 nvidia,enable- 275 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
276 }; 276 };
277 277
278 /* Apalis MMC1 */ 278 /* Apalis MMC1 */
279 sdmmc3-clk-pa6 { 279 sdmmc3-clk-pa6 {
280 nvidia,pins = 280 nvidia,pins = "sdmmc3_clk_pa6";
281 nvidia,functio 281 nvidia,function = "sdmmc3";
282 nvidia,pull = 282 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
283 nvidia,tristat 283 nvidia,tristate = <TEGRA_PIN_DISABLE>;
284 }; 284 };
285 sdmmc3-dat0-pb7 { 285 sdmmc3-dat0-pb7 {
286 nvidia,pins = 286 nvidia,pins = "sdmmc3_cmd_pa7",
287 287 "sdmmc3_dat0_pb7",
288 288 "sdmmc3_dat1_pb6",
289 289 "sdmmc3_dat2_pb5",
290 290 "sdmmc3_dat3_pb4",
291 291 "sdmmc3_dat4_pd1",
292 292 "sdmmc3_dat5_pd0",
293 293 "sdmmc3_dat6_pd3",
294 294 "sdmmc3_dat7_pd4";
295 nvidia,functio 295 nvidia,function = "sdmmc3";
296 nvidia,pull = 296 nvidia,pull = <TEGRA_PIN_PULL_UP>;
297 nvidia,tristat 297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 }; 298 };
299 /* Apalis MMC1_CD# */ 299 /* Apalis MMC1_CD# */
300 pv3 { 300 pv3 {
301 nvidia,pins = 301 nvidia,pins = "pv3";
302 nvidia,functio 302 nvidia,function = "rsvd2";
303 nvidia,pull = 303 nvidia,pull = <TEGRA_PIN_PULL_UP>;
304 nvidia,tristat 304 nvidia,tristate = <TEGRA_PIN_DISABLE>;
305 nvidia,enable- 305 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306 }; 306 };
307 307
308 /* Apalis Parallel Cam 308 /* Apalis Parallel Camera */
309 cam-mclk-pcc0 { 309 cam-mclk-pcc0 {
310 nvidia,pins = 310 nvidia,pins = "cam_mclk_pcc0";
311 nvidia,functio 311 nvidia,function = "vi_alt3";
312 nvidia,pull = 312 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313 nvidia,tristat 313 nvidia,tristate = <TEGRA_PIN_DISABLE>;
314 nvidia,enable- 314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315 }; 315 };
316 vi-vsync-pd6 { 316 vi-vsync-pd6 {
317 nvidia,pins = 317 nvidia,pins = "vi_d0_pt4",
318 318 "vi_d1_pd5",
319 319 "vi_d2_pl0",
320 320 "vi_d3_pl1",
321 321 "vi_d4_pl2",
322 322 "vi_d5_pl3",
323 323 "vi_d6_pl4",
324 324 "vi_d7_pl5",
325 325 "vi_d8_pl6",
326 326 "vi_d9_pl7",
327 327 "vi_d10_pt2",
328 328 "vi_d11_pt3",
329 329 "vi_hsync_pd7",
330 330 "vi_pclk_pt0",
331 331 "vi_vsync_pd6";
332 nvidia,functio 332 nvidia,function = "vi";
333 nvidia,pull = 333 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334 nvidia,tristat 334 nvidia,tristate = <TEGRA_PIN_DISABLE>;
335 nvidia,enable- 335 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336 }; 336 };
337 /* Multiplexed and the 337 /* Multiplexed and therefore disabled */
338 kb-col2-pq2 { 338 kb-col2-pq2 {
339 nvidia,pins = 339 nvidia,pins = "kb_col2_pq2",
340 340 "kb_col3_pq3",
341 341 "kb_col4_pq4",
342 342 "kb_row4_pr4";
343 nvidia,functio 343 nvidia,function = "rsvd4";
344 nvidia,pull = 344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
345 nvidia,tristat 345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
346 nvidia,enable- 346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347 }; 347 };
348 kb-row0-pr0 { 348 kb-row0-pr0 {
349 nvidia,pins = 349 nvidia,pins = "kb_row0_pr0",
350 350 "kb_row1_pr1",
351 351 "kb_row2_pr2",
352 352 "kb_row3_pr3";
353 nvidia,functio 353 nvidia,function = "rsvd3";
354 nvidia,pull = 354 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
355 nvidia,tristat 355 nvidia,tristate = <TEGRA_PIN_ENABLE>;
356 nvidia,enable- 356 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
357 }; 357 };
358 kb-row5-pr5 { 358 kb-row5-pr5 {
359 nvidia,pins = 359 nvidia,pins = "kb_row5_pr5",
360 360 "kb_row6_pr6",
361 361 "kb_row7_pr7";
362 nvidia,functio 362 nvidia,function = "kbc";
363 nvidia,pull = 363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
364 nvidia,tristat 364 nvidia,tristate = <TEGRA_PIN_ENABLE>;
365 nvidia,enable- 365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 }; 366 };
367 /* 367 /*
368 * VI level-shifter di 368 * VI level-shifter direction
369 * (pull-down => defau 369 * (pull-down => default direction input)
370 */ 370 */
371 vi-mclk-pt1 { 371 vi-mclk-pt1 {
372 nvidia,pins = 372 nvidia,pins = "vi_mclk_pt1";
373 nvidia,functio 373 nvidia,function = "vi_alt3";
374 nvidia,pull = 374 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
375 nvidia,tristat 375 nvidia,tristate = <TEGRA_PIN_ENABLE>;
376 nvidia,enable- 376 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377 }; 377 };
378 378
379 /* Apalis PWM1 */ 379 /* Apalis PWM1 */
380 pu6 { 380 pu6 {
381 nvidia,pins = 381 nvidia,pins = "pu6";
382 nvidia,functio 382 nvidia,function = "pwm3";
383 nvidia,pull = 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristat 384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 }; 385 };
386 386
387 /* Apalis PWM2 */ 387 /* Apalis PWM2 */
388 pu5 { 388 pu5 {
389 nvidia,pins = 389 nvidia,pins = "pu5";
390 nvidia,functio 390 nvidia,function = "pwm2";
391 nvidia,pull = 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristat 392 nvidia,tristate = <TEGRA_PIN_DISABLE>;
393 }; 393 };
394 394
395 /* Apalis PWM3 */ 395 /* Apalis PWM3 */
396 pu4 { 396 pu4 {
397 nvidia,pins = 397 nvidia,pins = "pu4";
398 nvidia,functio 398 nvidia,function = "pwm1";
399 nvidia,pull = 399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristat 400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 }; 401 };
402 402
403 /* Apalis PWM4 */ 403 /* Apalis PWM4 */
404 pu3 { 404 pu3 {
405 nvidia,pins = 405 nvidia,pins = "pu3";
406 nvidia,functio 406 nvidia,function = "pwm0";
407 nvidia,pull = 407 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
408 nvidia,tristat 408 nvidia,tristate = <TEGRA_PIN_DISABLE>;
409 }; 409 };
410 410
411 /* Apalis RESET_MOCI# 411 /* Apalis RESET_MOCI# */
412 gmi-rst-n-pi4 { 412 gmi-rst-n-pi4 {
413 nvidia,pins = 413 nvidia,pins = "gmi_rst_n_pi4";
414 nvidia,functio 414 nvidia,function = "gmi";
415 nvidia,pull = 415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416 nvidia,tristat 416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
417 }; 417 };
418 418
419 /* Apalis SATA1_ACT# * 419 /* Apalis SATA1_ACT# */
420 pex-l0-prsnt-n-pdd0 { 420 pex-l0-prsnt-n-pdd0 {
421 nvidia,pins = 421 nvidia,pins = "pex_l0_prsnt_n_pdd0";
422 nvidia,functio 422 nvidia,function = "rsvd3";
423 nvidia,pull = 423 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
424 nvidia,tristat 424 nvidia,tristate = <TEGRA_PIN_DISABLE>;
425 nvidia,enable- 425 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
426 }; 426 };
427 427
428 /* Apalis SD1 */ 428 /* Apalis SD1 */
429 sdmmc1-clk-pz0 { 429 sdmmc1-clk-pz0 {
430 nvidia,pins = 430 nvidia,pins = "sdmmc1_clk_pz0";
431 nvidia,functio 431 nvidia,function = "sdmmc1";
432 nvidia,pull = 432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristat 433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 }; 434 };
435 sdmmc1-cmd-pz1 { 435 sdmmc1-cmd-pz1 {
436 nvidia,pins = 436 nvidia,pins = "sdmmc1_cmd_pz1",
437 437 "sdmmc1_dat0_py7",
438 438 "sdmmc1_dat1_py6",
439 439 "sdmmc1_dat2_py5",
440 440 "sdmmc1_dat3_py4";
441 nvidia,functio 441 nvidia,function = "sdmmc1";
442 nvidia,pull = 442 nvidia,pull = <TEGRA_PIN_PULL_UP>;
443 nvidia,tristat 443 nvidia,tristate = <TEGRA_PIN_DISABLE>;
444 }; 444 };
445 /* Apalis SD1_CD# */ 445 /* Apalis SD1_CD# */
446 clk2-req-pcc5 { 446 clk2-req-pcc5 {
447 nvidia,pins = 447 nvidia,pins = "clk2_req_pcc5";
448 nvidia,functio 448 nvidia,function = "rsvd2";
449 nvidia,pull = 449 nvidia,pull = <TEGRA_PIN_PULL_UP>;
450 nvidia,tristat 450 nvidia,tristate = <TEGRA_PIN_DISABLE>;
451 nvidia,enable- 451 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
452 }; 452 };
453 453
454 /* Apalis SPDIF1 */ 454 /* Apalis SPDIF1 */
455 spdif-out-pk5 { 455 spdif-out-pk5 {
456 nvidia,pins = 456 nvidia,pins = "spdif_out_pk5",
457 457 "spdif_in_pk6";
458 nvidia,functio 458 nvidia,function = "spdif";
459 nvidia,pull = 459 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
460 nvidia,tristat 460 nvidia,tristate = <TEGRA_PIN_DISABLE>;
461 nvidia,enable- 461 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
462 }; 462 };
463 463
464 /* Apalis SPI1 */ 464 /* Apalis SPI1 */
465 spi1-sck-px5 { 465 spi1-sck-px5 {
466 nvidia,pins = 466 nvidia,pins = "spi1_sck_px5",
467 467 "spi1_mosi_px4",
468 468 "spi1_miso_px7",
469 469 "spi1_cs0_n_px6";
470 nvidia,functio 470 nvidia,function = "spi1";
471 nvidia,pull = 471 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472 nvidia,tristat 472 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 }; 473 };
474 474
475 /* Apalis SPI2 */ 475 /* Apalis SPI2 */
476 lcd-sck-pz4 { 476 lcd-sck-pz4 {
477 nvidia,pins = 477 nvidia,pins = "lcd_sck_pz4",
478 478 "lcd_sdout_pn5",
479 479 "lcd_sdin_pz2",
480 480 "lcd_cs0_n_pn4";
481 nvidia,functio 481 nvidia,function = "spi5";
482 nvidia,pull = 482 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483 nvidia,tristat 483 nvidia,tristate = <TEGRA_PIN_DISABLE>;
484 }; 484 };
485 485
486 /* 486 /*
487 * Apalis TS (Low-spee 487 * Apalis TS (Low-speed type specific)
488 * pins may be used as 488 * pins may be used as GPIOs
489 */ 489 */
490 kb-col5-pq5 { 490 kb-col5-pq5 {
491 nvidia,pins = 491 nvidia,pins = "kb_col5_pq5";
492 nvidia,functio 492 nvidia,function = "rsvd4";
493 nvidia,pull = 493 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
494 nvidia,tristat 494 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable- 495 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 }; 496 };
497 kb-col6-pq6 { 497 kb-col6-pq6 {
498 nvidia,pins = 498 nvidia,pins = "kb_col6_pq6",
499 499 "kb_col7_pq7",
500 500 "kb_row8_ps0",
501 501 "kb_row9_ps1";
502 nvidia,functio 502 nvidia,function = "kbc";
503 nvidia,pull = 503 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
504 nvidia,tristat 504 nvidia,tristate = <TEGRA_PIN_DISABLE>;
505 nvidia,enable- 505 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
506 }; 506 };
507 507
508 /* Apalis UART1 */ 508 /* Apalis UART1 */
509 ulpi-data0 { 509 ulpi-data0 {
510 nvidia,pins = 510 nvidia,pins = "ulpi_data0_po1",
511 511 "ulpi_data1_po2",
512 512 "ulpi_data2_po3",
513 513 "ulpi_data3_po4",
514 514 "ulpi_data4_po5",
515 515 "ulpi_data5_po6",
516 516 "ulpi_data6_po7",
517 517 "ulpi_data7_po0";
518 nvidia,functio 518 nvidia,function = "uarta";
519 nvidia,pull = 519 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520 nvidia,tristat 520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 }; 521 };
522 522
523 /* Apalis UART2 */ 523 /* Apalis UART2 */
524 ulpi-clk-py0 { 524 ulpi-clk-py0 {
525 nvidia,pins = 525 nvidia,pins = "ulpi_clk_py0",
526 526 "ulpi_dir_py1",
527 527 "ulpi_nxt_py2",
528 528 "ulpi_stp_py3";
529 nvidia,functio 529 nvidia,function = "uartd";
530 nvidia,pull = 530 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531 nvidia,tristat 531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 }; 532 };
533 533
534 /* Apalis UART3 */ 534 /* Apalis UART3 */
535 uart2-rxd-pc3 { 535 uart2-rxd-pc3 {
536 nvidia,pins = 536 nvidia,pins = "uart2_rxd_pc3",
537 537 "uart2_txd_pc2";
538 nvidia,functio 538 nvidia,function = "uartb";
539 nvidia,pull = 539 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
540 nvidia,tristat 540 nvidia,tristate = <TEGRA_PIN_DISABLE>;
541 }; 541 };
542 542
543 /* Apalis UART4 */ 543 /* Apalis UART4 */
544 uart3-rxd-pw7 { 544 uart3-rxd-pw7 {
545 nvidia,pins = 545 nvidia,pins = "uart3_rxd_pw7",
546 546 "uart3_txd_pw6";
547 nvidia,functio 547 nvidia,function = "uartc";
548 nvidia,pull = 548 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549 nvidia,tristat 549 nvidia,tristate = <TEGRA_PIN_DISABLE>;
550 }; 550 };
551 551
552 /* Apalis USBH_EN */ 552 /* Apalis USBH_EN */
553 pex-l0-rst-n-pdd1 { 553 pex-l0-rst-n-pdd1 {
554 nvidia,pins = 554 nvidia,pins = "pex_l0_rst_n_pdd1";
555 nvidia,functio 555 nvidia,function = "rsvd3";
556 nvidia,pull = 556 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557 nvidia,tristat 557 nvidia,tristate = <TEGRA_PIN_DISABLE>;
558 nvidia,enable- 558 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
559 }; 559 };
560 560
561 /* Apalis USBH_OC# */ 561 /* Apalis USBH_OC# */
562 pex-l0-clkreq-n-pdd2 { 562 pex-l0-clkreq-n-pdd2 {
563 nvidia,pins = 563 nvidia,pins = "pex_l0_clkreq_n_pdd2";
564 nvidia,functio 564 nvidia,function = "rsvd3";
565 nvidia,pull = 565 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
566 nvidia,tristat 566 nvidia,tristate = <TEGRA_PIN_DISABLE>;
567 nvidia,enable- 567 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
568 }; 568 };
569 569
570 /* Apalis USBO1_EN */ 570 /* Apalis USBO1_EN */
571 gen2-i2c-scl-pt5 { 571 gen2-i2c-scl-pt5 {
572 nvidia,pins = 572 nvidia,pins = "gen2_i2c_scl_pt5";
573 nvidia,functio 573 nvidia,function = "rsvd4";
574 nvidia,open-dr 574 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
575 nvidia,pull = 575 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
576 nvidia,tristat 576 nvidia,tristate = <TEGRA_PIN_DISABLE>;
577 }; 577 };
578 578
579 /* Apalis USBO1_OC# */ 579 /* Apalis USBO1_OC# */
580 gen2-i2c-sda-pt6 { 580 gen2-i2c-sda-pt6 {
581 nvidia,pins = 581 nvidia,pins = "gen2_i2c_sda_pt6";
582 nvidia,functio 582 nvidia,function = "rsvd4";
583 nvidia,open-dr 583 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
584 nvidia,pull = 584 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
585 nvidia,tristat 585 nvidia,tristate = <TEGRA_PIN_DISABLE>;
586 nvidia,enable- 586 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
587 }; 587 };
588 588
589 /* Apalis VGA1 not sup 589 /* Apalis VGA1 not supported and therefore disabled */
590 crt-hsync-pv6 { 590 crt-hsync-pv6 {
591 nvidia,pins = 591 nvidia,pins = "crt_hsync_pv6",
592 592 "crt_vsync_pv7";
593 nvidia,functio 593 nvidia,function = "rsvd2";
594 nvidia,pull = 594 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
595 nvidia,tristat 595 nvidia,tristate = <TEGRA_PIN_ENABLE>;
596 nvidia,enable- 596 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
597 }; 597 };
598 598
599 /* Apalis WAKE1_MICO * 599 /* Apalis WAKE1_MICO */
600 pv1 { 600 pv1 {
601 nvidia,pins = 601 nvidia,pins = "pv1";
602 nvidia,functio 602 nvidia,function = "rsvd1";
603 nvidia,pull = 603 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604 nvidia,tristat 604 nvidia,tristate = <TEGRA_PIN_DISABLE>;
605 nvidia,enable- 605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 }; 606 };
607 607
608 /* eMMC (On-module) */ 608 /* eMMC (On-module) */
609 sdmmc4-clk-pcc4 { 609 sdmmc4-clk-pcc4 {
610 nvidia,pins = 610 nvidia,pins = "sdmmc4_clk_pcc4",
611 611 "sdmmc4_cmd_pt7",
612 612 "sdmmc4_rst_n_pcc3";
613 nvidia,functio 613 nvidia,function = "sdmmc4";
614 nvidia,pull = 614 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
615 nvidia,tristat 615 nvidia,tristate = <TEGRA_PIN_DISABLE>;
616 nvidia,enable- 616 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
617 }; 617 };
618 sdmmc4-dat0-paa0 { 618 sdmmc4-dat0-paa0 {
619 nvidia,pins = 619 nvidia,pins = "sdmmc4_dat0_paa0",
620 620 "sdmmc4_dat1_paa1",
621 621 "sdmmc4_dat2_paa2",
622 622 "sdmmc4_dat3_paa3",
623 623 "sdmmc4_dat4_paa4",
624 624 "sdmmc4_dat5_paa5",
625 625 "sdmmc4_dat6_paa6",
626 626 "sdmmc4_dat7_paa7";
627 nvidia,functio 627 nvidia,function = "sdmmc4";
628 nvidia,pull = 628 nvidia,pull = <TEGRA_PIN_PULL_UP>;
629 nvidia,tristat 629 nvidia,tristate = <TEGRA_PIN_DISABLE>;
630 nvidia,enable- 630 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
631 }; 631 };
632 632
633 /* EN_+3.3_SDMMC3 */ 633 /* EN_+3.3_SDMMC3 */
634 uart2-cts-n-pj5 { 634 uart2-cts-n-pj5 {
635 nvidia,pins = 635 nvidia,pins = "uart2_cts_n_pj5";
636 nvidia,functio 636 nvidia,function = "gmi";
637 nvidia,pull = 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristat 638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable- 639 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640 }; 640 };
641 641
642 /* LAN i210/i211 DEV_O 642 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
643 pex-l2-prsnt-n-pdd7 { 643 pex-l2-prsnt-n-pdd7 {
644 nvidia,pins = 644 nvidia,pins = "pex_l2_prsnt_n_pdd7",
645 645 "pex_l2_rst_n_pcc6";
646 nvidia,functio 646 nvidia,function = "pcie";
647 nvidia,pull = 647 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648 nvidia,tristat 648 nvidia,tristate = <TEGRA_PIN_DISABLE>;
649 nvidia,enable- 649 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
650 }; 650 };
651 /* LAN i210/i211 PE_WA 651 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
652 pex-wake-n-pdd3 { 652 pex-wake-n-pdd3 {
653 nvidia,pins = 653 nvidia,pins = "pex_wake_n_pdd3",
654 654 "pex_l2_clkreq_n_pcc7";
655 nvidia,functio 655 nvidia,function = "pcie";
656 nvidia,pull = 656 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
657 nvidia,tristat 657 nvidia,tristate = <TEGRA_PIN_DISABLE>;
658 nvidia,enable- 658 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
659 }; 659 };
660 /* LAN i210/i211 SMB_A 660 /* LAN i210/i211 SMB_ALERT_N (On-module) */
661 sys-clk-req-pz5 { 661 sys-clk-req-pz5 {
662 nvidia,pins = 662 nvidia,pins = "sys_clk_req_pz5";
663 nvidia,functio 663 nvidia,function = "rsvd2";
664 nvidia,pull = 664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristat 665 nvidia,tristate = <TEGRA_PIN_DISABLE>;
666 nvidia,enable- 666 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
667 }; 667 };
668 668
669 /* LVDS Transceiver Co 669 /* LVDS Transceiver Configuration */
670 pbb0 { 670 pbb0 {
671 nvidia,pins = 671 nvidia,pins = "pbb0",
672 672 "pbb7",
673 673 "pcc1",
674 674 "pcc2";
675 nvidia,functio 675 nvidia,function = "rsvd2";
676 nvidia,pull = 676 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677 nvidia,tristat 677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
678 nvidia,enable- 678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679 }; 679 };
680 pbb3 { 680 pbb3 {
681 nvidia,pins = 681 nvidia,pins = "pbb3",
682 682 "pbb4",
683 683 "pbb5",
684 684 "pbb6";
685 nvidia,functio 685 nvidia,function = "displayb";
686 nvidia,pull = 686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
687 nvidia,tristat 687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
688 nvidia,enable- 688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689 }; 689 };
690 690
691 /* Not connected and t 691 /* Not connected and therefore disabled */
692 clk-32k-out-pa0 { 692 clk-32k-out-pa0 {
693 nvidia,pins = 693 nvidia,pins = "clk3_out_pee0",
694 694 "clk3_req_pee1",
695 695 "clk_32k_out_pa0",
696 696 "dap4_din_pp5",
697 697 "dap4_dout_pp6",
698 698 "dap4_fs_pp4",
699 699 "dap4_sclk_pp7";
700 nvidia,functio 700 nvidia,function = "rsvd2";
701 nvidia,pull = 701 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
702 nvidia,tristat 702 nvidia,tristate = <TEGRA_PIN_ENABLE>;
703 nvidia,enable- 703 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
704 }; 704 };
705 dap2-fs-pa2 { 705 dap2-fs-pa2 {
706 nvidia,pins = 706 nvidia,pins = "dap2_fs_pa2",
707 707 "dap2_sclk_pa3",
708 708 "dap2_din_pa4",
709 709 "dap2_dout_pa5",
710 710 "lcd_dc0_pn6",
711 711 "lcd_m1_pw1",
712 712 "lcd_pwr1_pc1",
713 713 "pex_l1_clkreq_n_pdd6",
714 714 "pex_l1_prsnt_n_pdd4",
715 715 "pex_l1_rst_n_pdd5";
716 nvidia,functio 716 nvidia,function = "rsvd3";
717 nvidia,pull = 717 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
718 nvidia,tristat 718 nvidia,tristate = <TEGRA_PIN_ENABLE>;
719 nvidia,enable- 719 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
720 }; 720 };
721 gmi-ad0-pg0 { 721 gmi-ad0-pg0 {
722 nvidia,pins = 722 nvidia,pins = "gmi_ad0_pg0",
723 723 "gmi_ad2_pg2",
724 724 "gmi_ad3_pg3",
725 725 "gmi_ad4_pg4",
726 726 "gmi_ad5_pg5",
727 727 "gmi_ad6_pg6",
728 728 "gmi_ad7_pg7",
729 729 "gmi_ad8_ph0",
730 730 "gmi_ad9_ph1",
731 731 "gmi_ad10_ph2",
732 732 "gmi_ad11_ph3",
733 733 "gmi_ad12_ph4",
734 734 "gmi_ad13_ph5",
735 735 "gmi_ad14_ph6",
736 736 "gmi_ad15_ph7",
737 737 "gmi_adv_n_pk0",
738 738 "gmi_clk_pk1",
739 739 "gmi_cs4_n_pk2",
740 740 "gmi_cs2_n_pk3",
741 741 "gmi_dqs_pi2",
742 742 "gmi_iordy_pi5",
743 743 "gmi_oe_n_pi1",
744 744 "gmi_wait_pi7",
745 745 "gmi_wr_n_pi0",
746 746 "lcd_cs1_n_pw0",
747 747 "pu0",
748 748 "pu1",
749 749 "pu2";
750 nvidia,functio 750 nvidia,function = "rsvd4";
751 nvidia,pull = 751 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
752 nvidia,tristat 752 nvidia,tristate = <TEGRA_PIN_ENABLE>;
753 nvidia,enable- 753 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
754 }; 754 };
755 gmi-cs0-n-pj0 { 755 gmi-cs0-n-pj0 {
756 nvidia,pins = 756 nvidia,pins = "gmi_cs0_n_pj0",
757 757 "gmi_cs1_n_pj2",
758 758 "gmi_cs3_n_pk4";
759 nvidia,functio 759 nvidia,function = "rsvd1";
760 nvidia,pull = 760 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
761 nvidia,tristat 761 nvidia,tristate = <TEGRA_PIN_ENABLE>;
762 nvidia,enable- 762 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
763 }; 763 };
764 gmi-cs6-n-pi3 { 764 gmi-cs6-n-pi3 {
765 nvidia,pins = 765 nvidia,pins = "gmi_cs6_n_pi3";
766 nvidia,functio 766 nvidia,function = "sata";
767 nvidia,pull = 767 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
768 nvidia,tristat 768 nvidia,tristate = <TEGRA_PIN_ENABLE>;
769 nvidia,enable- 769 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
770 }; 770 };
771 gmi-cs7-n-pi6 { 771 gmi-cs7-n-pi6 {
772 nvidia,pins = 772 nvidia,pins = "gmi_cs7_n_pi6";
773 nvidia,functio 773 nvidia,function = "gmi_alt";
774 nvidia,pull = 774 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
775 nvidia,tristat 775 nvidia,tristate = <TEGRA_PIN_ENABLE>;
776 nvidia,enable- 776 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
777 }; 777 };
778 lcd-pwr0-pb2 { 778 lcd-pwr0-pb2 {
779 nvidia,pins = 779 nvidia,pins = "lcd_pwr0_pb2",
780 780 "lcd_pwr2_pc6",
781 781 "lcd_wr_n_pz3";
782 nvidia,functio 782 nvidia,function = "hdcp";
783 nvidia,pull = 783 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
784 nvidia,tristat 784 nvidia,tristate = <TEGRA_PIN_ENABLE>;
785 nvidia,enable- 785 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
786 }; 786 };
787 uart2-rts-n-pj6 { 787 uart2-rts-n-pj6 {
788 nvidia,pins = 788 nvidia,pins = "uart2_rts_n_pj6";
789 nvidia,functio 789 nvidia,function = "gmi";
790 nvidia,pull = 790 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
791 nvidia,tristat 791 nvidia,tristate = <TEGRA_PIN_ENABLE>;
792 nvidia,enable- 792 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
793 }; 793 };
794 794
795 /* Power I2C (On-modul 795 /* Power I2C (On-module) */
796 pwr-i2c-scl-pz6 { 796 pwr-i2c-scl-pz6 {
797 nvidia,pins = 797 nvidia,pins = "pwr_i2c_scl_pz6",
798 798 "pwr_i2c_sda_pz7";
799 nvidia,functio 799 nvidia,function = "i2cpwr";
800 nvidia,pull = 800 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
801 nvidia,tristat 801 nvidia,tristate = <TEGRA_PIN_DISABLE>;
802 nvidia,enable- 802 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
803 nvidia,open-dr 803 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
804 }; 804 };
805 805
806 /* 806 /*
807 * THERMD_ALERT#, unla 807 * THERMD_ALERT#, unlatched I2C address pin of LM95245
808 * temperature sensor 808 * temperature sensor therefore requires disabling for
809 * now 809 * now
810 */ 810 */
811 lcd-dc1-pd2 { 811 lcd-dc1-pd2 {
812 nvidia,pins = 812 nvidia,pins = "lcd_dc1_pd2";
813 nvidia,functio 813 nvidia,function = "rsvd3";
814 nvidia,pull = 814 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
815 nvidia,tristat 815 nvidia,tristate = <TEGRA_PIN_ENABLE>;
816 nvidia,enable- 816 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
817 }; 817 };
818 818
819 /* TOUCH_PEN_INT# (On- 819 /* TOUCH_PEN_INT# (On-module) */
820 pv0 { 820 pv0 {
821 nvidia,pins = 821 nvidia,pins = "pv0";
822 nvidia,functio 822 nvidia,function = "rsvd1";
823 nvidia,pull = 823 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824 nvidia,tristat 824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable- 825 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826 }; 826 };
827 }; 827 };
828 }; 828 };
829 829
830 serial@70006040 { 830 serial@70006040 {
831 compatible = "nvidia,tegra30-h 831 compatible = "nvidia,tegra30-hsuart";
832 reset-names = "serial"; 832 reset-names = "serial";
833 /delete-property/ reg-shift; 833 /delete-property/ reg-shift;
834 }; 834 };
835 835
836 serial@70006200 { 836 serial@70006200 {
837 compatible = "nvidia,tegra30-h 837 compatible = "nvidia,tegra30-hsuart";
838 reset-names = "serial"; 838 reset-names = "serial";
839 /delete-property/ reg-shift; 839 /delete-property/ reg-shift;
840 }; 840 };
841 841
842 serial@70006300 { 842 serial@70006300 {
843 compatible = "nvidia,tegra30-h 843 compatible = "nvidia,tegra30-hsuart";
844 reset-names = "serial"; 844 reset-names = "serial";
845 /delete-property/ reg-shift; 845 /delete-property/ reg-shift;
846 }; 846 };
847 847
848 hdmi_ddc: i2c@7000c700 { 848 hdmi_ddc: i2c@7000c700 {
849 clock-frequency = <10000>; 849 clock-frequency = <10000>;
850 }; 850 };
851 851
852 /* 852 /*
853 * PWR_I2C: power I2C to audio codec, 853 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
854 * touch screen controller 854 * touch screen controller
855 */ 855 */
856 i2c@7000d000 { 856 i2c@7000d000 {
857 status = "okay"; 857 status = "okay";
858 clock-frequency = <100000>; 858 clock-frequency = <100000>;
859 859
860 /* SGTL5000 audio codec */ 860 /* SGTL5000 audio codec */
861 sgtl5000: codec@a { 861 sgtl5000: codec@a {
862 compatible = "fsl,sgtl 862 compatible = "fsl,sgtl5000";
863 reg = <0x0a>; 863 reg = <0x0a>;
864 #sound-dai-cells = <0> 864 #sound-dai-cells = <0>;
865 VDDA-supply = <®_mo 865 VDDA-supply = <®_module_3v3_audio>;
866 VDDD-supply = <®_1v 866 VDDD-supply = <®_1v8_vio>;
867 VDDIO-supply = <®_m 867 VDDIO-supply = <®_module_3v3>;
868 clocks = <&tegra_car T 868 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
869 }; 869 };
870 870
871 pmic: pmic@2d { 871 pmic: pmic@2d {
872 compatible = "ti,tps65 872 compatible = "ti,tps65911";
873 reg = <0x2d>; 873 reg = <0x2d>;
874 874
875 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
876 #interrupt-cells = <2> 876 #interrupt-cells = <2>;
877 interrupt-controller; 877 interrupt-controller;
878 878
879 ti,system-power-contro 879 ti,system-power-controller;
880 880
881 #gpio-cells = <2>; 881 #gpio-cells = <2>;
882 gpio-controller; 882 gpio-controller;
883 883
884 vcc1-supply = <®_mo 884 vcc1-supply = <®_module_3v3>;
885 vcc2-supply = <®_mo 885 vcc2-supply = <®_module_3v3>;
886 vcc3-supply = <®_1v 886 vcc3-supply = <®_1v8_vio>;
887 vcc4-supply = <®_mo 887 vcc4-supply = <®_module_3v3>;
888 vcc5-supply = <®_mo 888 vcc5-supply = <®_module_3v3>;
889 vcc6-supply = <®_1v 889 vcc6-supply = <®_1v8_vio>;
890 vcc7-supply = <®_5v 890 vcc7-supply = <®_5v0_charge_pump>;
891 vccio-supply = <®_m 891 vccio-supply = <®_module_3v3>;
892 892
893 regulators { 893 regulators {
894 vdd1_reg: vdd1 894 vdd1_reg: vdd1 {
895 regula 895 regulator-name = "+V1.35_VDDIO_DDR";
896 regula 896 regulator-min-microvolt = <1350000>;
897 regula 897 regulator-max-microvolt = <1350000>;
898 regula 898 regulator-always-on;
899 }; 899 };
900 900
901 vdd2_reg: vdd2 901 vdd2_reg: vdd2 {
902 regula 902 regulator-name = "+V1.05";
903 regula 903 regulator-min-microvolt = <1050000>;
904 regula 904 regulator-max-microvolt = <1050000>;
905 }; 905 };
906 906
907 vddctrl_reg: v 907 vddctrl_reg: vddctrl {
908 regula 908 regulator-name = "+V1.0_VDD_CPU";
909 regula 909 regulator-min-microvolt = <1150000>;
910 regula 910 regulator-max-microvolt = <1150000>;
911 regula 911 regulator-always-on;
912 }; 912 };
913 913
914 reg_1v8_vio: v 914 reg_1v8_vio: vio {
915 regula 915 regulator-name = "+V1.8";
916 regula 916 regulator-min-microvolt = <1800000>;
917 regula 917 regulator-max-microvolt = <1800000>;
918 regula 918 regulator-always-on;
919 }; 919 };
920 920
921 /* 921 /*
922 * 1.8 volt +V 922 * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
923 * is off 923 * is off
924 */ 924 */
925 vddio_sdmmc_1v 925 vddio_sdmmc_1v8_reg: ldo1 {
926 regula 926 regulator-name = "+VDDIO_SDMMC3_1V8";
927 regula 927 regulator-min-microvolt = <1800000>;
928 regula 928 regulator-max-microvolt = <1800000>;
929 regula 929 regulator-always-on;
930 }; 930 };
931 931
932 /* 932 /*
933 * EN_+V3.3 sw 933 * EN_+V3.3 switching via FET:
934 * +V3.3_AUDIO 934 * +V3.3_AUDIO_AVDD_S, +V3.3
935 * see also +V 935 * see also +V3.3 fixed supply
936 */ 936 */
937 ldo2_reg: ldo2 937 ldo2_reg: ldo2 {
938 regula 938 regulator-name = "EN_+V3.3";
939 regula 939 regulator-min-microvolt = <3300000>;
940 regula 940 regulator-max-microvolt = <3300000>;
941 regula 941 regulator-always-on;
942 }; 942 };
943 943
944 ldo3_reg: ldo3 944 ldo3_reg: ldo3 {
945 regula 945 regulator-name = "+V1.2_CSI";
946 regula 946 regulator-min-microvolt = <1200000>;
947 regula 947 regulator-max-microvolt = <1200000>;
948 }; 948 };
949 949
950 ldo4_reg: ldo4 950 ldo4_reg: ldo4 {
951 regula 951 regulator-name = "+V1.2_VDD_RTC";
952 regula 952 regulator-min-microvolt = <1200000>;
953 regula 953 regulator-max-microvolt = <1200000>;
954 regula 954 regulator-always-on;
955 }; 955 };
956 956
957 /* 957 /*
958 * +V2.8_AVDD_ 958 * +V2.8_AVDD_VDAC:
959 * only requir 959 * only required for (unsupported) analog RGB
960 */ 960 */
961 ldo5_reg: ldo5 961 ldo5_reg: ldo5 {
962 regula 962 regulator-name = "+V2.8_AVDD_VDAC";
963 regula 963 regulator-min-microvolt = <2800000>;
964 regula 964 regulator-max-microvolt = <2800000>;
965 regula 965 regulator-always-on;
966 }; 966 };
967 967
968 /* 968 /*
969 * +V1.05_AVDD 969 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
970 * but LDO6 ca 970 * but LDO6 can't set voltage in 50mV
971 * granularity 971 * granularity
972 */ 972 */
973 ldo6_reg: ldo6 973 ldo6_reg: ldo6 {
974 regula 974 regulator-name = "+V1.05_AVDD_PLLE";
975 regula 975 regulator-min-microvolt = <1100000>;
976 regula 976 regulator-max-microvolt = <1100000>;
977 }; 977 };
978 978
979 ldo7_reg: ldo7 979 ldo7_reg: ldo7 {
980 regula 980 regulator-name = "+V1.2_AVDD_PLL";
981 regula 981 regulator-min-microvolt = <1200000>;
982 regula 982 regulator-max-microvolt = <1200000>;
983 regula 983 regulator-always-on;
984 }; 984 };
985 985
986 ldo8_reg: ldo8 986 ldo8_reg: ldo8 {
987 regula 987 regulator-name = "+V1.0_VDD_DDR_HS";
988 regula 988 regulator-min-microvolt = <1000000>;
989 regula 989 regulator-max-microvolt = <1000000>;
990 regula 990 regulator-always-on;
991 }; 991 };
992 }; 992 };
993 }; 993 };
994 994
995 /* STMPE811 touch screen contr 995 /* STMPE811 touch screen controller */
996 touchscreen@41 { 996 touchscreen@41 {
997 compatible = "st,stmpe 997 compatible = "st,stmpe811";
998 reg = <0x41>; 998 reg = <0x41>;
999 irq-gpio = <&gpio TEGR 999 irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1000 id = <0>; 1000 id = <0>;
1001 blocks = <0x5>; 1001 blocks = <0x5>;
1002 irq-trigger = <0x1>; 1002 irq-trigger = <0x1>;
1003 /* 3.25 MHz ADC clock 1003 /* 3.25 MHz ADC clock speed */
1004 st,adc-freq = <1>; 1004 st,adc-freq = <1>;
1005 /* 12-bit ADC */ 1005 /* 12-bit ADC */
1006 st,mod-12b = <1>; 1006 st,mod-12b = <1>;
1007 /* internal ADC refer 1007 /* internal ADC reference */
1008 st,ref-sel = <0>; 1008 st,ref-sel = <0>;
1009 /* ADC converstion ti 1009 /* ADC converstion time: 80 clocks */
1010 st,sample-time = <4>; 1010 st,sample-time = <4>;
1011 1011
1012 stmpe_adc { 1012 stmpe_adc {
1013 compatible = 1013 compatible = "st,stmpe-adc";
1014 /* forbid to 1014 /* forbid to use ADC channels 3-0 (touch) */
1015 st,norequest- 1015 st,norequest-mask = <0x0F>;
1016 }; 1016 };
1017 1017
1018 stmpe_touchscreen { 1018 stmpe_touchscreen {
1019 compatible = 1019 compatible = "st,stmpe-ts";
1020 /* 8 sample a 1020 /* 8 sample average control */
1021 st,ave-ctrl = 1021 st,ave-ctrl = <3>;
1022 /* 7 length f 1022 /* 7 length fractional part in z */
1023 st,fraction-z 1023 st,fraction-z = <7>;
1024 /* 1024 /*
1025 * 50 mA typi 1025 * 50 mA typical 80 mA max touchscreen drivers
1026 * current li 1026 * current limit value
1027 */ 1027 */
1028 st,i-drive = 1028 st,i-drive = <1>;
1029 /* 1 ms panel 1029 /* 1 ms panel driver settling time */
1030 st,settling = 1030 st,settling = <3>;
1031 /* 5 ms touch 1031 /* 5 ms touch detect interrupt delay */
1032 st,touch-det- 1032 st,touch-det-delay = <5>;
1033 }; 1033 };
1034 }; 1034 };
1035 1035
1036 /* 1036 /*
1037 * LM95245 temperature sensor 1037 * LM95245 temperature sensor
1038 * Note: OVERT1# directly con 1038 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1039 */ 1039 */
1040 temp-sensor@4c { 1040 temp-sensor@4c {
1041 compatible = "nationa 1041 compatible = "national,lm95245";
1042 reg = <0x4c>; 1042 reg = <0x4c>;
1043 }; 1043 };
1044 1044
1045 /* SW: +V1.2_VDD_CORE */ 1045 /* SW: +V1.2_VDD_CORE */
1046 regulator@60 { 1046 regulator@60 {
1047 compatible = "ti,tps6 1047 compatible = "ti,tps62362";
1048 reg = <0x60>; 1048 reg = <0x60>;
1049 1049
1050 regulator-name = "tps 1050 regulator-name = "tps62362-vout";
1051 regulator-min-microvo 1051 regulator-min-microvolt = <900000>;
1052 regulator-max-microvo 1052 regulator-max-microvolt = <1400000>;
1053 regulator-boot-on; 1053 regulator-boot-on;
1054 regulator-always-on; 1054 regulator-always-on;
1055 }; 1055 };
1056 }; 1056 };
1057 1057
1058 /* SPI4: CAN2 */ 1058 /* SPI4: CAN2 */
1059 spi@7000da00 { 1059 spi@7000da00 {
1060 status = "okay"; 1060 status = "okay";
1061 spi-max-frequency = <10000000 1061 spi-max-frequency = <10000000>;
1062 1062
1063 can@1 { 1063 can@1 {
1064 compatible = "microch 1064 compatible = "microchip,mcp2515";
1065 reg = <1>; 1065 reg = <1>;
1066 clocks = <&clk16m>; 1066 clocks = <&clk16m>;
1067 interrupt-parent = <& 1067 interrupt-parent = <&gpio>;
1068 interrupts = <TEGRA_G 1068 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1069 spi-max-frequency = < 1069 spi-max-frequency = <10000000>;
1070 }; 1070 };
1071 }; 1071 };
1072 1072
1073 /* SPI6: CAN1 */ 1073 /* SPI6: CAN1 */
1074 spi@7000de00 { 1074 spi@7000de00 {
1075 status = "okay"; 1075 status = "okay";
1076 spi-max-frequency = <10000000 1076 spi-max-frequency = <10000000>;
1077 1077
1078 can@0 { 1078 can@0 {
1079 compatible = "microch 1079 compatible = "microchip,mcp2515";
1080 reg = <0>; 1080 reg = <0>;
1081 clocks = <&clk16m>; 1081 clocks = <&clk16m>;
1082 interrupt-parent = <& 1082 interrupt-parent = <&gpio>;
1083 interrupts = <TEGRA_G 1083 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1084 spi-max-frequency = < 1084 spi-max-frequency = <10000000>;
1085 }; 1085 };
1086 }; 1086 };
1087 1087
1088 pmc@7000e400 { 1088 pmc@7000e400 {
1089 nvidia,invert-interrupt; 1089 nvidia,invert-interrupt;
1090 nvidia,suspend-mode = <1>; 1090 nvidia,suspend-mode = <1>;
1091 nvidia,cpu-pwr-good-time = <5 1091 nvidia,cpu-pwr-good-time = <5000>;
1092 nvidia,cpu-pwr-off-time = <50 1092 nvidia,cpu-pwr-off-time = <5000>;
1093 nvidia,core-pwr-good-time = < 1093 nvidia,core-pwr-good-time = <3845 3845>;
1094 nvidia,core-pwr-off-time = <0 1094 nvidia,core-pwr-off-time = <0>;
1095 nvidia,core-power-req-active- 1095 nvidia,core-power-req-active-high;
1096 nvidia,sys-clock-req-active-h 1096 nvidia,sys-clock-req-active-high;
1097 1097
1098 /* Set DEV_OFF bit in DCDC co 1098 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1099 i2c-thermtrip { 1099 i2c-thermtrip {
1100 nvidia,i2c-controller 1100 nvidia,i2c-controller-id = <4>;
1101 nvidia,bus-addr = <0x 1101 nvidia,bus-addr = <0x2d>;
1102 nvidia,reg-addr = <0x 1102 nvidia,reg-addr = <0x3f>;
1103 nvidia,reg-data = <0x 1103 nvidia,reg-data = <0x1>;
1104 }; 1104 };
1105 }; 1105 };
1106 1106
1107 hda@70030000 { 1107 hda@70030000 {
1108 status = "okay"; 1108 status = "okay";
1109 }; 1109 };
1110 1110
1111 ahub@70080000 { 1111 ahub@70080000 {
1112 i2s@70080500 { 1112 i2s@70080500 {
1113 status = "okay"; 1113 status = "okay";
1114 }; 1114 };
1115 }; 1115 };
1116 1116
1117 /* eMMC */ 1117 /* eMMC */
1118 mmc@78000600 { 1118 mmc@78000600 {
1119 status = "okay"; 1119 status = "okay";
1120 bus-width = <8>; 1120 bus-width = <8>;
1121 non-removable; 1121 non-removable;
1122 vmmc-supply = <®_module_3v 1122 vmmc-supply = <®_module_3v3>; /* VCC */
1123 vqmmc-supply = <®_1v8_vio> 1123 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
1124 mmc-ddr-1_8v; 1124 mmc-ddr-1_8v;
1125 }; 1125 };
1126 1126
1127 clk16m: clock-osc4 { 1127 clk16m: clock-osc4 {
1128 compatible = "fixed-clock"; 1128 compatible = "fixed-clock";
1129 #clock-cells = <0>; 1129 #clock-cells = <0>;
1130 clock-frequency = <16000000>; 1130 clock-frequency = <16000000>;
1131 }; 1131 };
1132 1132
1133 clk32k_in: clock-xtal1 { 1133 clk32k_in: clock-xtal1 {
1134 compatible = "fixed-clock"; 1134 compatible = "fixed-clock";
1135 #clock-cells = <0>; 1135 #clock-cells = <0>;
1136 clock-frequency = <32768>; 1136 clock-frequency = <32768>;
1137 }; 1137 };
1138 1138
1139 reg_1v8_avdd_hdmi_pll: regulator-1v8- 1139 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1140 compatible = "regulator-fixed 1140 compatible = "regulator-fixed";
1141 regulator-name = "+V1.8_AVDD_ 1141 regulator-name = "+V1.8_AVDD_HDMI_PLL";
1142 regulator-min-microvolt = <18 1142 regulator-min-microvolt = <1800000>;
1143 regulator-max-microvolt = <18 1143 regulator-max-microvolt = <1800000>;
1144 enable-active-high; 1144 enable-active-high;
1145 gpio = <&pmic 6 GPIO_ACTIVE_H 1145 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1146 vin-supply = <®_1v8_vio>; 1146 vin-supply = <®_1v8_vio>;
1147 }; 1147 };
1148 1148
1149 reg_3v3_avdd_hdmi: regulator-3v3-avdd 1149 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1150 compatible = "regulator-fixed 1150 compatible = "regulator-fixed";
1151 regulator-name = "+V3.3_AVDD_ 1151 regulator-name = "+V3.3_AVDD_HDMI";
1152 regulator-min-microvolt = <33 1152 regulator-min-microvolt = <3300000>;
1153 regulator-max-microvolt = <33 1153 regulator-max-microvolt = <3300000>;
1154 enable-active-high; 1154 enable-active-high;
1155 gpio = <&pmic 6 GPIO_ACTIVE_H 1155 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1156 vin-supply = <®_module_3v3 1156 vin-supply = <®_module_3v3>;
1157 }; 1157 };
1158 1158
1159 reg_5v0_charge_pump: regulator-5v0-ch 1159 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1160 compatible = "regulator-fixed 1160 compatible = "regulator-fixed";
1161 regulator-name = "+V5.0"; 1161 regulator-name = "+V5.0";
1162 regulator-min-microvolt = <50 1162 regulator-min-microvolt = <5000000>;
1163 regulator-max-microvolt = <50 1163 regulator-max-microvolt = <5000000>;
1164 regulator-always-on; 1164 regulator-always-on;
1165 }; 1165 };
1166 1166
1167 reg_module_3v3: regulator-module-3v3 1167 reg_module_3v3: regulator-module-3v3 {
1168 compatible = "regulator-fixed 1168 compatible = "regulator-fixed";
1169 regulator-name = "+V3.3"; 1169 regulator-name = "+V3.3";
1170 regulator-min-microvolt = <33 1170 regulator-min-microvolt = <3300000>;
1171 regulator-max-microvolt = <33 1171 regulator-max-microvolt = <3300000>;
1172 regulator-always-on; 1172 regulator-always-on;
1173 }; 1173 };
1174 1174
1175 reg_module_3v3_audio: regulator-modul 1175 reg_module_3v3_audio: regulator-module-3v3-audio {
1176 compatible = "regulator-fixed 1176 compatible = "regulator-fixed";
1177 regulator-name = "+V3.3_AUDIO 1177 regulator-name = "+V3.3_AUDIO_AVDD_S";
1178 regulator-min-microvolt = <33 1178 regulator-min-microvolt = <3300000>;
1179 regulator-max-microvolt = <33 1179 regulator-max-microvolt = <3300000>;
1180 regulator-always-on; 1180 regulator-always-on;
1181 }; 1181 };
1182 1182
1183 sound { 1183 sound {
1184 compatible = "toradex,tegra-a 1184 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1185 "nvidia,tegra-au 1185 "nvidia,tegra-audio-sgtl5000";
1186 nvidia,model = "Toradex Apali 1186 nvidia,model = "Toradex Apalis T30";
1187 nvidia,audio-routing = 1187 nvidia,audio-routing =
1188 "Headphone Jack", "HP 1188 "Headphone Jack", "HP_OUT",
1189 "LINE_IN", "Line In J 1189 "LINE_IN", "Line In Jack",
1190 "MIC_IN", "Mic Jack"; 1190 "MIC_IN", "Mic Jack";
1191 nvidia,i2s-controller = <&teg 1191 nvidia,i2s-controller = <&tegra_i2s2>;
1192 nvidia,audio-codec = <&sgtl50 1192 nvidia,audio-codec = <&sgtl5000>;
1193 clocks = <&tegra_car TEGRA30_ 1193 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1194 <&tegra_car TEGRA30_ 1194 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1195 <&tegra_pmc TEGRA_PM 1195 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1196 clock-names = "pll_a", "pll_a 1196 clock-names = "pll_a", "pll_a_out0", "mclk";
1197 1197
1198 assigned-clocks = <&tegra_car 1198 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1199 <&tegra_pmc 1199 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1200 1200
1201 assigned-clock-parents = <&te 1201 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1202 <&te 1202 <&tegra_car TEGRA30_CLK_EXTERN1>;
1203 }; 1203 };
1204 }; 1204 };
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