1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra30.dtsi"
3
4 /*
5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A; 2GB: V
7 */
8 / {
9 memory@80000000 {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 pcie@3000 {
14 status = "okay";
15 avdd-pexa-supply = <&vdd2_reg>
16 avdd-pexb-supply = <&vdd2_reg>
17 avdd-pex-pll-supply = <&vdd2_r
18 avdd-plle-supply = <&ldo6_reg>
19 hvdd-pex-supply = <®_module
20 vddio-pex-ctl-supply = <®_m
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
23
24 /* Apalis type specific */
25 pci@1,0 {
26 nvidia,num-lanes = <4>
27 };
28
29 /* Apalis PCIe */
30 pci@2,0 {
31 nvidia,num-lanes = <1>
32 };
33
34 /* I210/I211 Gigabit Ethernet
35 pci@3,0 {
36 status = "okay";
37 nvidia,num-lanes = <1>
38
39 ethernet@0,0 {
40 reg = <0 0 0 0
41 local-mac-addr
42 };
43 };
44 };
45
46 host1x@50000000 {
47 hdmi@54280000 {
48 nvidia,ddc-i2c-bus = <
49 nvidia,hpd-gpio =
50 <&gpio TEGRA_G
51 pll-supply = <®_1v8
52 vdd-supply = <®_3v3
53 };
54 };
55
56 pinmux@70000868 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&state_default>;
59
60 state_default: pinmux {
61 /* Analogue Audio (On-
62 clk1-out-pw4 {
63 nvidia,pins =
64 nvidia,functio
65 nvidia,pull =
66 nvidia,tristat
67 nvidia,enable-
68 };
69 dap3-fs-pp0 {
70 nvidia,pins =
71
72
73
74 nvidia,functio
75 nvidia,pull =
76 nvidia,tristat
77 };
78
79 /* Apalis BKL1_ON */
80 pv2 {
81 nvidia,pins =
82 nvidia,functio
83 nvidia,pull =
84 nvidia,tristat
85 nvidia,enable-
86 };
87
88 /* Apalis BKL1_PWM */
89 uart3-rts-n-pc0 {
90 nvidia,pins =
91 nvidia,functio
92 nvidia,pull =
93 nvidia,tristat
94 nvidia,enable-
95 };
96 /* BKL1_PWM_EN#, disab
97 uart3-cts-n-pa1 {
98 nvidia,pins =
99 nvidia,functio
100 nvidia,pull =
101 nvidia,tristat
102 nvidia,enable-
103 };
104
105 /* Apalis CAN1 on SPI6
106 spi2-cs0-n-px3 {
107 nvidia,pins =
108
109
110
111 nvidia,functio
112 nvidia,pull =
113 nvidia,tristat
114 };
115 /* CAN_INT1 */
116 spi2-cs1-n-pw2 {
117 nvidia,pins =
118 nvidia,functio
119 nvidia,pull =
120 nvidia,tristat
121 nvidia,enable-
122 };
123
124 /* Apalis CAN2 on SPI4
125 gmi-a16-pj7 {
126 nvidia,pins =
127
128
129
130 nvidia,functio
131 nvidia,pull =
132 nvidia,tristat
133 nvidia,enable-
134 };
135 /* CAN_INT2 */
136 spi2-cs2-n-pw3 {
137 nvidia,pins =
138 nvidia,functio
139 nvidia,pull =
140 nvidia,tristat
141 nvidia,enable-
142 };
143
144 /* Apalis Digital Audi
145 clk1-req-pee2 {
146 nvidia,pins =
147 nvidia,functio
148 nvidia,pull =
149 nvidia,tristat
150 };
151 clk2-out-pw5 {
152 nvidia,pins =
153 nvidia,functio
154 nvidia,pull =
155 nvidia,tristat
156 nvidia,enable-
157 };
158 dap1-fs-pn0 {
159 nvidia,pins =
160
161
162
163 nvidia,functio
164 nvidia,pull =
165 nvidia,tristat
166 };
167
168 /* Apalis GPIO */
169 kb-col0-pq0 {
170 nvidia,pins =
171
172
173
174
175
176
177
178 nvidia,functio
179 nvidia,pull =
180 nvidia,tristat
181 nvidia,enable-
182 };
183 /* Multiplexed and the
184 owr {
185 nvidia,pins =
186 nvidia,functio
187 nvidia,pull =
188 nvidia,tristat
189 nvidia,enable-
190 };
191
192 /* Apalis HDMI1 */
193 hdmi-cec-pee3 {
194 nvidia,pins =
195 nvidia,functio
196 nvidia,pull =
197 nvidia,tristat
198 nvidia,enable-
199 nvidia,open-dr
200 };
201 hdmi-int-pn7 {
202 nvidia,pins =
203 nvidia,functio
204 nvidia,pull =
205 nvidia,tristat
206 nvidia,enable-
207 };
208
209 /* Apalis I2C1 */
210 gen1-i2c-scl-pc4 {
211 nvidia,pins =
212
213 nvidia,functio
214 nvidia,pull =
215 nvidia,tristat
216 nvidia,enable-
217 nvidia,open-dr
218 };
219
220 /* Apalis I2C2 (DDC) *
221 ddc-scl-pv4 {
222 nvidia,pins =
223
224 nvidia,functio
225 nvidia,pull =
226 nvidia,tristat
227 nvidia,enable-
228 };
229
230 /* Apalis I2C3 (CAM) *
231 cam-i2c-scl-pbb1 {
232 nvidia,pins =
233
234 nvidia,functio
235 nvidia,pull =
236 nvidia,tristat
237 nvidia,enable-
238 nvidia,open-dr
239 };
240
241 /* Apalis LCD1 */
242 lcd-d0-pe0 {
243 nvidia,pins =
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271 nvidia,functio
272 nvidia,pull =
273 nvidia,tristat
274 nvidia,enable-
275 };
276
277 /* Apalis MMC1 */
278 sdmmc3-clk-pa6 {
279 nvidia,pins =
280 nvidia,functio
281 nvidia,pull =
282 nvidia,tristat
283 };
284 sdmmc3-dat0-pb7 {
285 nvidia,pins =
286
287
288
289
290
291
292
293
294 nvidia,functio
295 nvidia,pull =
296 nvidia,tristat
297 };
298 /* Apalis MMC1_CD# */
299 pv3 {
300 nvidia,pins =
301 nvidia,functio
302 nvidia,pull =
303 nvidia,tristat
304 nvidia,enable-
305 };
306
307 /* Apalis Parallel Cam
308 cam-mclk-pcc0 {
309 nvidia,pins =
310 nvidia,functio
311 nvidia,pull =
312 nvidia,tristat
313 nvidia,enable-
314 };
315 vi-vsync-pd6 {
316 nvidia,pins =
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331 nvidia,functio
332 nvidia,pull =
333 nvidia,tristat
334 nvidia,enable-
335 };
336 /* Multiplexed and the
337 kb-col2-pq2 {
338 nvidia,pins =
339
340
341
342 nvidia,functio
343 nvidia,pull =
344 nvidia,tristat
345 nvidia,enable-
346 };
347 kb-row0-pr0 {
348 nvidia,pins =
349
350
351
352 nvidia,functio
353 nvidia,pull =
354 nvidia,tristat
355 nvidia,enable-
356 };
357 kb-row5-pr5 {
358 nvidia,pins =
359
360
361 nvidia,functio
362 nvidia,pull =
363 nvidia,tristat
364 nvidia,enable-
365 };
366 /*
367 * VI level-shifter di
368 * (pull-down => defau
369 */
370 vi-mclk-pt1 {
371 nvidia,pins =
372 nvidia,functio
373 nvidia,pull =
374 nvidia,tristat
375 nvidia,enable-
376 };
377
378 /* Apalis PWM1 */
379 pu6 {
380 nvidia,pins =
381 nvidia,functio
382 nvidia,pull =
383 nvidia,tristat
384 };
385
386 /* Apalis PWM2 */
387 pu5 {
388 nvidia,pins =
389 nvidia,functio
390 nvidia,pull =
391 nvidia,tristat
392 };
393
394 /* Apalis PWM3 */
395 pu4 {
396 nvidia,pins =
397 nvidia,functio
398 nvidia,pull =
399 nvidia,tristat
400 };
401
402 /* Apalis PWM4 */
403 pu3 {
404 nvidia,pins =
405 nvidia,functio
406 nvidia,pull =
407 nvidia,tristat
408 };
409
410 /* Apalis RESET_MOCI#
411 gmi-rst-n-pi4 {
412 nvidia,pins =
413 nvidia,functio
414 nvidia,pull =
415 nvidia,tristat
416 };
417
418 /* Apalis SATA1_ACT# *
419 pex-l0-prsnt-n-pdd0 {
420 nvidia,pins =
421 nvidia,functio
422 nvidia,pull =
423 nvidia,tristat
424 nvidia,enable-
425 };
426
427 /* Apalis SD1 */
428 sdmmc1-clk-pz0 {
429 nvidia,pins =
430 nvidia,functio
431 nvidia,pull =
432 nvidia,tristat
433 };
434 sdmmc1-cmd-pz1 {
435 nvidia,pins =
436
437
438
439
440 nvidia,functio
441 nvidia,pull =
442 nvidia,tristat
443 };
444 /* Apalis SD1_CD# */
445 clk2-req-pcc5 {
446 nvidia,pins =
447 nvidia,functio
448 nvidia,pull =
449 nvidia,tristat
450 nvidia,enable-
451 };
452
453 /* Apalis SPDIF1 */
454 spdif-out-pk5 {
455 nvidia,pins =
456
457 nvidia,functio
458 nvidia,pull =
459 nvidia,tristat
460 nvidia,enable-
461 };
462
463 /* Apalis SPI1 */
464 spi1-sck-px5 {
465 nvidia,pins =
466
467
468
469 nvidia,functio
470 nvidia,pull =
471 nvidia,tristat
472 };
473
474 /* Apalis SPI2 */
475 lcd-sck-pz4 {
476 nvidia,pins =
477
478
479
480 nvidia,functio
481 nvidia,pull =
482 nvidia,tristat
483 };
484
485 /*
486 * Apalis TS (Low-spee
487 * pins may be used as
488 */
489 kb-col5-pq5 {
490 nvidia,pins =
491 nvidia,functio
492 nvidia,pull =
493 nvidia,tristat
494 nvidia,enable-
495 };
496 kb-col6-pq6 {
497 nvidia,pins =
498
499
500
501 nvidia,functio
502 nvidia,pull =
503 nvidia,tristat
504 nvidia,enable-
505 };
506
507 /* Apalis UART1 */
508 ulpi-data0 {
509 nvidia,pins =
510
511
512
513
514
515
516
517 nvidia,functio
518 nvidia,pull =
519 nvidia,tristat
520 };
521
522 /* Apalis UART2 */
523 ulpi-clk-py0 {
524 nvidia,pins =
525
526
527
528 nvidia,functio
529 nvidia,pull =
530 nvidia,tristat
531 };
532
533 /* Apalis UART3 */
534 uart2-rxd-pc3 {
535 nvidia,pins =
536
537 nvidia,functio
538 nvidia,pull =
539 nvidia,tristat
540 };
541
542 /* Apalis UART4 */
543 uart3-rxd-pw7 {
544 nvidia,pins =
545
546 nvidia,functio
547 nvidia,pull =
548 nvidia,tristat
549 };
550
551 /* Apalis USBH_EN */
552 pex-l0-rst-n-pdd1 {
553 nvidia,pins =
554 nvidia,functio
555 nvidia,pull =
556 nvidia,tristat
557 nvidia,enable-
558 };
559
560 /* Apalis USBH_OC# */
561 pex-l0-clkreq-n-pdd2 {
562 nvidia,pins =
563 nvidia,functio
564 nvidia,pull =
565 nvidia,tristat
566 nvidia,enable-
567 };
568
569 /* Apalis USBO1_EN */
570 gen2-i2c-scl-pt5 {
571 nvidia,pins =
572 nvidia,functio
573 nvidia,open-dr
574 nvidia,pull =
575 nvidia,tristat
576 };
577
578 /* Apalis USBO1_OC# */
579 gen2-i2c-sda-pt6 {
580 nvidia,pins =
581 nvidia,functio
582 nvidia,open-dr
583 nvidia,pull =
584 nvidia,tristat
585 nvidia,enable-
586 };
587
588 /* Apalis VGA1 not sup
589 crt-hsync-pv6 {
590 nvidia,pins =
591
592 nvidia,functio
593 nvidia,pull =
594 nvidia,tristat
595 nvidia,enable-
596 };
597
598 /* Apalis WAKE1_MICO *
599 pv1 {
600 nvidia,pins =
601 nvidia,functio
602 nvidia,pull =
603 nvidia,tristat
604 nvidia,enable-
605 };
606
607 /* eMMC (On-module) */
608 sdmmc4-clk-pcc4 {
609 nvidia,pins =
610
611
612 nvidia,functio
613 nvidia,pull =
614 nvidia,tristat
615 nvidia,enable-
616 };
617 sdmmc4-dat0-paa0 {
618 nvidia,pins =
619
620
621
622
623
624
625
626 nvidia,functio
627 nvidia,pull =
628 nvidia,tristat
629 nvidia,enable-
630 };
631
632 /* LAN i210/i211 DEV_O
633 pex-l2-prsnt-n-pdd7 {
634 nvidia,pins =
635
636 nvidia,functio
637 nvidia,pull =
638 nvidia,tristat
639 nvidia,enable-
640 };
641 /* LAN i210/i211 PE_WA
642 pex-wake-n-pdd3 {
643 nvidia,pins =
644
645 nvidia,functio
646 nvidia,pull =
647 nvidia,tristat
648 nvidia,enable-
649 };
650 /* LAN i210/i211 SMB_A
651 sys-clk-req-pz5 {
652 nvidia,pins =
653 nvidia,functio
654 nvidia,pull =
655 nvidia,tristat
656 nvidia,enable-
657 };
658
659 /* LVDS Transceiver Co
660 pbb0 {
661 nvidia,pins =
662
663
664
665 nvidia,functio
666 nvidia,pull =
667 nvidia,tristat
668 nvidia,enable-
669 };
670 pbb3 {
671 nvidia,pins =
672
673
674
675 nvidia,functio
676 nvidia,pull =
677 nvidia,tristat
678 nvidia,enable-
679 };
680
681 /* Not connected and t
682 clk-32k-out-pa0 {
683 nvidia,pins =
684
685
686
687
688
689
690 nvidia,functio
691 nvidia,pull =
692 nvidia,tristat
693 nvidia,enable-
694 };
695 dap2-fs-pa2 {
696 nvidia,pins =
697
698
699
700
701
702
703
704
705
706 nvidia,functio
707 nvidia,pull =
708 nvidia,tristat
709 nvidia,enable-
710 };
711 gmi-ad0-pg0 {
712 nvidia,pins =
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740 nvidia,functio
741 nvidia,pull =
742 nvidia,tristat
743 nvidia,enable-
744 };
745 gmi-cs0-n-pj0 {
746 nvidia,pins =
747
748
749 nvidia,functio
750 nvidia,pull =
751 nvidia,tristat
752 nvidia,enable-
753 };
754 gmi-cs6-n-pi3 {
755 nvidia,pins =
756 nvidia,functio
757 nvidia,pull =
758 nvidia,tristat
759 nvidia,enable-
760 };
761 gmi-cs7-n-pi6 {
762 nvidia,pins =
763 nvidia,functio
764 nvidia,pull =
765 nvidia,tristat
766 nvidia,enable-
767 };
768 lcd-pwr0-pb2 {
769 nvidia,pins =
770
771
772 nvidia,functio
773 nvidia,pull =
774 nvidia,tristat
775 nvidia,enable-
776 };
777 uart2-cts-n-pj5 {
778 nvidia,pins =
779
780 nvidia,functio
781 nvidia,pull =
782 nvidia,tristat
783 nvidia,enable-
784 };
785
786 /* Power I2C (On-modul
787 pwr-i2c-scl-pz6 {
788 nvidia,pins =
789
790 nvidia,functio
791 nvidia,pull =
792 nvidia,tristat
793 nvidia,enable-
794 nvidia,open-dr
795 };
796
797 /*
798 * THERMD_ALERT#, unla
799 * temperature sensor
800 * now
801 */
802 lcd-dc1-pd2 {
803 nvidia,pins =
804 nvidia,functio
805 nvidia,pull =
806 nvidia,tristat
807 nvidia,enable-
808 };
809
810 /* TOUCH_PEN_INT# (On-
811 pv0 {
812 nvidia,pins =
813 nvidia,functio
814 nvidia,pull =
815 nvidia,tristat
816 nvidia,enable-
817 };
818 };
819 };
820
821 serial@70006040 {
822 compatible = "nvidia,tegra30-h
823 reset-names = "serial";
824 /delete-property/ reg-shift;
825 };
826
827 serial@70006200 {
828 compatible = "nvidia,tegra30-h
829 reset-names = "serial";
830 /delete-property/ reg-shift;
831 };
832
833 serial@70006300 {
834 compatible = "nvidia,tegra30-h
835 reset-names = "serial";
836 /delete-property/ reg-shift;
837 };
838
839 hdmi_ddc: i2c@7000c700 {
840 clock-frequency = <10000>;
841 };
842
843 /*
844 * PWR_I2C: power I2C to audio codec,
845 * touch screen controller
846 */
847 i2c@7000d000 {
848 status = "okay";
849 clock-frequency = <100000>;
850
851 /* SGTL5000 audio codec */
852 sgtl5000: codec@a {
853 compatible = "fsl,sgtl
854 reg = <0x0a>;
855 #sound-dai-cells = <0>
856 VDDA-supply = <®_mo
857 VDDD-supply = <®_1v
858 VDDIO-supply = <®_m
859 clocks = <&tegra_car T
860 };
861
862 pmic: pmic@2d {
863 compatible = "ti,tps65
864 reg = <0x2d>;
865
866 interrupts = <GIC_SPI
867 #interrupt-cells = <2>
868 interrupt-controller;
869 wakeup-source;
870
871 ti,system-power-contro
872
873 #gpio-cells = <2>;
874 gpio-controller;
875
876 vcc1-supply = <®_mo
877 vcc2-supply = <®_mo
878 vcc3-supply = <®_1v
879 vcc4-supply = <®_mo
880 vcc5-supply = <®_mo
881 vcc6-supply = <®_1v
882 vcc7-supply = <®_5v
883 vccio-supply = <®_m
884
885 regulators {
886 vdd1_reg: vdd1
887 regula
888 regula
889 regula
890 regula
891 };
892
893 vdd2_reg: vdd2
894 regula
895 regula
896 regula
897 };
898
899 vddctrl_reg: v
900 regula
901 regula
902 regula
903 regula
904 };
905
906 reg_1v8_vio: v
907 regula
908 regula
909 regula
910 regula
911 };
912
913 /* LDO1: unuse
914
915 /*
916 * EN_+V3.3 sw
917 * +V3.3_AUDIO
918 * see also +V
919 */
920 ldo2_reg: ldo2
921 regula
922 regula
923 regula
924 regula
925 };
926
927 ldo3_reg: ldo3
928 regula
929 regula
930 regula
931 };
932
933 ldo4_reg: ldo4
934 regula
935 regula
936 regula
937 regula
938 };
939
940 /*
941 * +V2.8_AVDD_
942 * only requir
943 */
944 ldo5_reg: ldo5
945 regula
946 regula
947 regula
948 regula
949 };
950
951 /*
952 * +V1.05_AVDD
953 * but LDO6 ca
954 * granularity
955 */
956 ldo6_reg: ldo6
957 regula
958 regula
959 regula
960 };
961
962 ldo7_reg: ldo7
963 regula
964 regula
965 regula
966 regula
967 };
968
969 ldo8_reg: ldo8
970 regula
971 regula
972 regula
973 regula
974 };
975 };
976 };
977
978 /* STMPE811 touch screen contr
979 touchscreen@41 {
980 compatible = "st,stmpe
981 reg = <0x41>;
982 irq-gpio = <&gpio TEGR
983 id = <0>;
984 blocks = <0x5>;
985 irq-trigger = <0x1>;
986 /* 3.25 MHz ADC clock
987 st,adc-freq = <1>;
988 /* 12-bit ADC */
989 st,mod-12b = <1>;
990 /* internal ADC refere
991 st,ref-sel = <0>;
992 /* ADC converstion tim
993 st,sample-time = <4>;
994
995 stmpe_adc {
996 compatible = "
997 /* forbid to u
998 st,norequest-m
999 };
1000
1001 stmpe_touchscreen {
1002 compatible =
1003 /* 8 sample a
1004 st,ave-ctrl =
1005 /* 7 length f
1006 st,fraction-z
1007 /*
1008 * 50 mA typi
1009 * current li
1010 */
1011 st,i-drive =
1012 /* 1 ms panel
1013 st,settling =
1014 /* 5 ms touch
1015 st,touch-det-
1016 };
1017 };
1018
1019 /*
1020 * LM95245 temperature sensor
1021 * Note: OVERT1# directly con
1022 */
1023 temp-sensor@4c {
1024 compatible = "nationa
1025 reg = <0x4c>;
1026 };
1027
1028 /* SW: +V1.2_VDD_CORE */
1029 regulator@60 {
1030 compatible = "ti,tps6
1031 reg = <0x60>;
1032
1033 regulator-name = "tps
1034 regulator-min-microvo
1035 regulator-max-microvo
1036 regulator-boot-on;
1037 regulator-always-on;
1038 };
1039 };
1040
1041 /* SPI4: CAN2 */
1042 spi@7000da00 {
1043 status = "okay";
1044 spi-max-frequency = <10000000
1045
1046 can@1 {
1047 compatible = "microch
1048 reg = <1>;
1049 clocks = <&clk16m>;
1050 interrupt-parent = <&
1051 interrupts = <TEGRA_G
1052 spi-max-frequency = <
1053 };
1054 };
1055
1056 /* SPI6: CAN1 */
1057 spi@7000de00 {
1058 status = "okay";
1059 spi-max-frequency = <10000000
1060
1061 can@0 {
1062 compatible = "microch
1063 reg = <0>;
1064 clocks = <&clk16m>;
1065 interrupt-parent = <&
1066 interrupts = <TEGRA_G
1067 spi-max-frequency = <
1068 };
1069 };
1070
1071 pmc@7000e400 {
1072 nvidia,invert-interrupt;
1073 nvidia,suspend-mode = <1>;
1074 nvidia,cpu-pwr-good-time = <5
1075 nvidia,cpu-pwr-off-time = <50
1076 nvidia,core-pwr-good-time = <
1077 nvidia,core-pwr-off-time = <0
1078 nvidia,core-power-req-active-
1079 nvidia,sys-clock-req-active-h
1080
1081 /* Set DEV_OFF bit in DCDC co
1082 i2c-thermtrip {
1083 nvidia,i2c-controller
1084 nvidia,bus-addr = <0x
1085 nvidia,reg-addr = <0x
1086 nvidia,reg-data = <0x
1087 };
1088 };
1089
1090 hda@70030000 {
1091 status = "okay";
1092 };
1093
1094 ahub@70080000 {
1095 i2s@70080500 {
1096 status = "okay";
1097 };
1098 };
1099
1100 /* eMMC */
1101 mmc@78000600 {
1102 status = "okay";
1103 bus-width = <8>;
1104 non-removable;
1105 vmmc-supply = <®_module_3v
1106 vqmmc-supply = <®_1v8_vio>
1107 mmc-ddr-1_8v;
1108 };
1109
1110 clk16m: clock-osc4 {
1111 compatible = "fixed-clock";
1112 #clock-cells = <0>;
1113 clock-frequency = <16000000>;
1114 };
1115
1116 clk32k_in: clock-xtal1 {
1117 compatible = "fixed-clock";
1118 #clock-cells = <0>;
1119 clock-frequency = <32768>;
1120 };
1121
1122 reg_1v8_avdd_hdmi_pll: regulator-1v8-
1123 compatible = "regulator-fixed
1124 regulator-name = "+V1.8_AVDD_
1125 regulator-min-microvolt = <18
1126 regulator-max-microvolt = <18
1127 enable-active-high;
1128 gpio = <&pmic 6 GPIO_ACTIVE_H
1129 vin-supply = <®_1v8_vio>;
1130 };
1131
1132 reg_3v3_avdd_hdmi: regulator-3v3-avdd
1133 compatible = "regulator-fixed
1134 regulator-name = "+V3.3_AVDD_
1135 regulator-min-microvolt = <33
1136 regulator-max-microvolt = <33
1137 enable-active-high;
1138 gpio = <&pmic 6 GPIO_ACTIVE_H
1139 vin-supply = <®_module_3v3
1140 };
1141
1142 reg_5v0_charge_pump: regulator-5v0-ch
1143 compatible = "regulator-fixed
1144 regulator-name = "+V5.0";
1145 regulator-min-microvolt = <50
1146 regulator-max-microvolt = <50
1147 regulator-always-on;
1148 };
1149
1150 reg_module_3v3: regulator-module-3v3
1151 compatible = "regulator-fixed
1152 regulator-name = "+V3.3";
1153 regulator-min-microvolt = <33
1154 regulator-max-microvolt = <33
1155 regulator-always-on;
1156 };
1157
1158 reg_module_3v3_audio: regulator-modul
1159 compatible = "regulator-fixed
1160 regulator-name = "+V3.3_AUDIO
1161 regulator-min-microvolt = <33
1162 regulator-max-microvolt = <33
1163 regulator-always-on;
1164 };
1165
1166 sound {
1167 compatible = "toradex,tegra-a
1168 "nvidia,tegra-au
1169 nvidia,model = "Toradex Apali
1170 nvidia,audio-routing =
1171 "Headphone Jack", "HP
1172 "LINE_IN", "Line In J
1173 "MIC_IN", "Mic Jack";
1174 nvidia,i2s-controller = <&teg
1175 nvidia,audio-codec = <&sgtl50
1176 clocks = <&tegra_car TEGRA30_
1177 <&tegra_car TEGRA30_
1178 <&tegra_pmc TEGRA_PM
1179 clock-names = "pll_a", "pll_a
1180
1181 assigned-clocks = <&tegra_car
1182 <&tegra_pmc
1183
1184 assigned-clock-parents = <&te
1185 <&te
1186 };
1187 };
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