1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra30.dtsi" 2 #include "tegra30.dtsi"
3 3
4 /* 4 /*
5 * Toradex Apalis T30 Module Device Tree 5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A; 2GB: V 6 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
7 */ 7 */
8 / { 8 / {
9 memory@80000000 { 9 memory@80000000 {
10 reg = <0x80000000 0x40000000>; 10 reg = <0x80000000 0x40000000>;
11 }; 11 };
12 12
13 pcie@3000 { 13 pcie@3000 {
14 status = "okay"; 14 status = "okay";
15 avdd-pexa-supply = <&vdd2_reg> 15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg> 16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_r 17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg> 18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <®_module 19 hvdd-pex-supply = <®_module_3v3>;
20 vddio-pex-ctl-supply = <®_m 20 vddio-pex-ctl-supply = <®_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>; 21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>; 22 vdd-pexb-supply = <&vdd2_reg>;
23 23
24 /* Apalis type specific */ 24 /* Apalis type specific */
25 pci@1,0 { 25 pci@1,0 {
26 nvidia,num-lanes = <4> 26 nvidia,num-lanes = <4>;
27 }; 27 };
28 28
29 /* Apalis PCIe */ 29 /* Apalis PCIe */
30 pci@2,0 { 30 pci@2,0 {
31 nvidia,num-lanes = <1> 31 nvidia,num-lanes = <1>;
32 }; 32 };
33 33
34 /* I210/I211 Gigabit Ethernet 34 /* I210/I211 Gigabit Ethernet Controller (on-module) */
35 pci@3,0 { 35 pci@3,0 {
36 status = "okay"; 36 status = "okay";
37 nvidia,num-lanes = <1> 37 nvidia,num-lanes = <1>;
38 38
39 ethernet@0,0 { 39 ethernet@0,0 {
40 reg = <0 0 0 0 40 reg = <0 0 0 0 0>;
41 local-mac-addr 41 local-mac-address = [00 00 00 00 00 00];
42 }; 42 };
43 }; 43 };
44 }; 44 };
45 45
46 host1x@50000000 { 46 host1x@50000000 {
47 hdmi@54280000 { 47 hdmi@54280000 {
48 nvidia,ddc-i2c-bus = < 48 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
49 nvidia,hpd-gpio = 49 nvidia,hpd-gpio =
50 <&gpio TEGRA_G 50 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
51 pll-supply = <®_1v8 51 pll-supply = <®_1v8_avdd_hdmi_pll>;
52 vdd-supply = <®_3v3 52 vdd-supply = <®_3v3_avdd_hdmi>;
53 }; 53 };
54 }; 54 };
55 55
56 pinmux@70000868 { 56 pinmux@70000868 {
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&state_default>; 58 pinctrl-0 = <&state_default>;
59 59
60 state_default: pinmux { 60 state_default: pinmux {
61 /* Analogue Audio (On- 61 /* Analogue Audio (On-module) */
62 clk1-out-pw4 { 62 clk1-out-pw4 {
63 nvidia,pins = 63 nvidia,pins = "clk1_out_pw4";
64 nvidia,functio 64 nvidia,function = "extperiph1";
65 nvidia,pull = 65 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
66 nvidia,tristat 66 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 nvidia,enable- 67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 }; 68 };
69 dap3-fs-pp0 { 69 dap3-fs-pp0 {
70 nvidia,pins = 70 nvidia,pins = "dap3_fs_pp0",
71 71 "dap3_sclk_pp3",
72 72 "dap3_din_pp1",
73 73 "dap3_dout_pp2";
74 nvidia,functio 74 nvidia,function = "i2s2";
75 nvidia,pull = 75 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
76 nvidia,tristat 76 nvidia,tristate = <TEGRA_PIN_DISABLE>;
77 }; 77 };
78 78
79 /* Apalis BKL1_ON */ 79 /* Apalis BKL1_ON */
80 pv2 { 80 pv2 {
81 nvidia,pins = 81 nvidia,pins = "pv2";
82 nvidia,functio 82 nvidia,function = "rsvd4";
83 nvidia,pull = 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84 nvidia,tristat 84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 nvidia,enable- 85 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
86 }; 86 };
87 87
88 /* Apalis BKL1_PWM */ 88 /* Apalis BKL1_PWM */
89 uart3-rts-n-pc0 { 89 uart3-rts-n-pc0 {
90 nvidia,pins = 90 nvidia,pins = "uart3_rts_n_pc0";
91 nvidia,functio 91 nvidia,function = "pwm0";
92 nvidia,pull = 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristat 93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,enable- 94 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95 }; 95 };
96 /* BKL1_PWM_EN#, disab 96 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
97 uart3-cts-n-pa1 { 97 uart3-cts-n-pa1 {
98 nvidia,pins = 98 nvidia,pins = "uart3_cts_n_pa1";
99 nvidia,functio 99 nvidia,function = "rsvd2";
100 nvidia,pull = 100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
101 nvidia,tristat 101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
102 nvidia,enable- 102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
103 }; 103 };
104 104
105 /* Apalis CAN1 on SPI6 105 /* Apalis CAN1 on SPI6 */
106 spi2-cs0-n-px3 { 106 spi2-cs0-n-px3 {
107 nvidia,pins = 107 nvidia,pins = "spi2_cs0_n_px3",
108 108 "spi2_miso_px1",
109 109 "spi2_mosi_px0",
110 110 "spi2_sck_px2";
111 nvidia,functio 111 nvidia,function = "spi6";
112 nvidia,pull = 112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
113 nvidia,tristat 113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
114 }; 114 };
115 /* CAN_INT1 */ 115 /* CAN_INT1 */
116 spi2-cs1-n-pw2 { 116 spi2-cs1-n-pw2 {
117 nvidia,pins = 117 nvidia,pins = "spi2_cs1_n_pw2";
118 nvidia,functio 118 nvidia,function = "spi3";
119 nvidia,pull = 119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristat 120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 nvidia,enable- 121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
122 }; 122 };
123 123
124 /* Apalis CAN2 on SPI4 124 /* Apalis CAN2 on SPI4 */
125 gmi-a16-pj7 { 125 gmi-a16-pj7 {
126 nvidia,pins = 126 nvidia,pins = "gmi_a16_pj7",
127 127 "gmi_a17_pb0",
128 128 "gmi_a18_pb1",
129 129 "gmi_a19_pk7";
130 nvidia,functio 130 nvidia,function = "spi4";
131 nvidia,pull = 131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristat 132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 nvidia,enable- 133 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
134 }; 134 };
135 /* CAN_INT2 */ 135 /* CAN_INT2 */
136 spi2-cs2-n-pw3 { 136 spi2-cs2-n-pw3 {
137 nvidia,pins = 137 nvidia,pins = "spi2_cs2_n_pw3";
138 nvidia,functio 138 nvidia,function = "spi3";
139 nvidia,pull = 139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
140 nvidia,tristat 140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 nvidia,enable- 141 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
142 }; 142 };
143 143
144 /* Apalis Digital Audi 144 /* Apalis Digital Audio */
145 clk1-req-pee2 { 145 clk1-req-pee2 {
146 nvidia,pins = 146 nvidia,pins = "clk1_req_pee2";
147 nvidia,functio 147 nvidia,function = "hda";
148 nvidia,pull = 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristat 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 }; 150 };
151 clk2-out-pw5 { 151 clk2-out-pw5 {
152 nvidia,pins = 152 nvidia,pins = "clk2_out_pw5";
153 nvidia,functio 153 nvidia,function = "extperiph2";
154 nvidia,pull = 154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristat 155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
156 nvidia,enable- 156 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
157 }; 157 };
158 dap1-fs-pn0 { 158 dap1-fs-pn0 {
159 nvidia,pins = 159 nvidia,pins = "dap1_fs_pn0",
160 160 "dap1_din_pn1",
161 161 "dap1_dout_pn2",
162 162 "dap1_sclk_pn3";
163 nvidia,functio 163 nvidia,function = "hda";
164 nvidia,pull = 164 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
165 nvidia,tristat 165 nvidia,tristate = <TEGRA_PIN_DISABLE>;
166 }; 166 };
167 167
168 /* Apalis GPIO */ 168 /* Apalis GPIO */
169 kb-col0-pq0 { 169 kb-col0-pq0 {
170 nvidia,pins = 170 nvidia,pins = "kb_col0_pq0",
171 171 "kb_col1_pq1",
172 172 "kb_row10_ps2",
173 173 "kb_row11_ps3",
174 174 "kb_row12_ps4",
175 175 "kb_row13_ps5",
176 176 "kb_row14_ps6",
177 177 "kb_row15_ps7";
178 nvidia,functio 178 nvidia,function = "kbc";
179 nvidia,pull = 179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristat 180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 nvidia,enable- 181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
182 }; 182 };
183 /* Multiplexed and the 183 /* Multiplexed and therefore disabled */
184 owr { 184 owr {
185 nvidia,pins = 185 nvidia,pins = "owr";
186 nvidia,functio 186 nvidia,function = "rsvd3";
187 nvidia,pull = 187 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
188 nvidia,tristat 188 nvidia,tristate = <TEGRA_PIN_ENABLE>;
189 nvidia,enable- 189 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
190 }; 190 };
191 191
192 /* Apalis HDMI1 */ 192 /* Apalis HDMI1 */
193 hdmi-cec-pee3 { 193 hdmi-cec-pee3 {
194 nvidia,pins = 194 nvidia,pins = "hdmi_cec_pee3";
195 nvidia,functio 195 nvidia,function = "cec";
196 nvidia,pull = 196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristat 197 nvidia,tristate = <TEGRA_PIN_DISABLE>;
198 nvidia,enable- 198 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
199 nvidia,open-dr 199 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
200 }; 200 };
201 hdmi-int-pn7 { 201 hdmi-int-pn7 {
202 nvidia,pins = 202 nvidia,pins = "hdmi_int_pn7";
203 nvidia,functio 203 nvidia,function = "hdmi";
204 nvidia,pull = 204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
205 nvidia,tristat 205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
206 nvidia,enable- 206 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
207 }; 207 };
208 208
209 /* Apalis I2C1 */ 209 /* Apalis I2C1 */
210 gen1-i2c-scl-pc4 { 210 gen1-i2c-scl-pc4 {
211 nvidia,pins = 211 nvidia,pins = "gen1_i2c_scl_pc4",
212 212 "gen1_i2c_sda_pc5";
213 nvidia,functio 213 nvidia,function = "i2c1";
214 nvidia,pull = 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristat 215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable- 216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 nvidia,open-dr 217 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
218 }; 218 };
219 219
220 /* Apalis I2C2 (DDC) * 220 /* Apalis I2C2 (DDC) */
221 ddc-scl-pv4 { 221 ddc-scl-pv4 {
222 nvidia,pins = 222 nvidia,pins = "ddc_scl_pv4",
223 223 "ddc_sda_pv5";
224 nvidia,functio 224 nvidia,function = "i2c4";
225 nvidia,pull = 225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristat 226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable- 227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 }; 228 };
229 229
230 /* Apalis I2C3 (CAM) * 230 /* Apalis I2C3 (CAM) */
231 cam-i2c-scl-pbb1 { 231 cam-i2c-scl-pbb1 {
232 nvidia,pins = 232 nvidia,pins = "cam_i2c_scl_pbb1",
233 233 "cam_i2c_sda_pbb2";
234 nvidia,functio 234 nvidia,function = "i2c3";
235 nvidia,pull = 235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236 nvidia,tristat 236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
237 nvidia,enable- 237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238 nvidia,open-dr 238 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
239 }; 239 };
240 240
241 /* Apalis LCD1 */ 241 /* Apalis LCD1 */
242 lcd-d0-pe0 { 242 lcd-d0-pe0 {
243 nvidia,pins = 243 nvidia,pins = "lcd_d0_pe0",
244 244 "lcd_d1_pe1",
245 245 "lcd_d2_pe2",
246 246 "lcd_d3_pe3",
247 247 "lcd_d4_pe4",
248 248 "lcd_d5_pe5",
249 249 "lcd_d6_pe6",
250 250 "lcd_d7_pe7",
251 251 "lcd_d8_pf0",
252 252 "lcd_d9_pf1",
253 253 "lcd_d10_pf2",
254 254 "lcd_d11_pf3",
255 255 "lcd_d12_pf4",
256 256 "lcd_d13_pf5",
257 257 "lcd_d14_pf6",
258 258 "lcd_d15_pf7",
259 259 "lcd_d16_pm0",
260 260 "lcd_d17_pm1",
261 261 "lcd_d18_pm2",
262 262 "lcd_d19_pm3",
263 263 "lcd_d20_pm4",
264 264 "lcd_d21_pm5",
265 265 "lcd_d22_pm6",
266 266 "lcd_d23_pm7",
267 267 "lcd_de_pj1",
268 268 "lcd_hsync_pj3",
269 269 "lcd_pclk_pb3",
270 270 "lcd_vsync_pj4";
271 nvidia,functio 271 nvidia,function = "displaya";
272 nvidia,pull = 272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristat 273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 nvidia,enable- 274 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
275 }; 275 };
276 276
277 /* Apalis MMC1 */ 277 /* Apalis MMC1 */
278 sdmmc3-clk-pa6 { 278 sdmmc3-clk-pa6 {
279 nvidia,pins = 279 nvidia,pins = "sdmmc3_clk_pa6";
280 nvidia,functio 280 nvidia,function = "sdmmc3";
281 nvidia,pull = 281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristat 282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
283 }; 283 };
284 sdmmc3-dat0-pb7 { 284 sdmmc3-dat0-pb7 {
285 nvidia,pins = 285 nvidia,pins = "sdmmc3_cmd_pa7",
286 286 "sdmmc3_dat0_pb7",
287 287 "sdmmc3_dat1_pb6",
288 288 "sdmmc3_dat2_pb5",
289 289 "sdmmc3_dat3_pb4",
290 290 "sdmmc3_dat4_pd1",
291 291 "sdmmc3_dat5_pd0",
292 292 "sdmmc3_dat6_pd3",
293 293 "sdmmc3_dat7_pd4";
294 nvidia,functio 294 nvidia,function = "sdmmc3";
295 nvidia,pull = 295 nvidia,pull = <TEGRA_PIN_PULL_UP>;
296 nvidia,tristat 296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
297 }; 297 };
298 /* Apalis MMC1_CD# */ 298 /* Apalis MMC1_CD# */
299 pv3 { 299 pv3 {
300 nvidia,pins = 300 nvidia,pins = "pv3";
301 nvidia,functio 301 nvidia,function = "rsvd2";
302 nvidia,pull = 302 nvidia,pull = <TEGRA_PIN_PULL_UP>;
303 nvidia,tristat 303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable- 304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 }; 305 };
306 306
307 /* Apalis Parallel Cam 307 /* Apalis Parallel Camera */
308 cam-mclk-pcc0 { 308 cam-mclk-pcc0 {
309 nvidia,pins = 309 nvidia,pins = "cam_mclk_pcc0";
310 nvidia,functio 310 nvidia,function = "vi_alt3";
311 nvidia,pull = 311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristat 312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 nvidia,enable- 313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
314 }; 314 };
315 vi-vsync-pd6 { 315 vi-vsync-pd6 {
316 nvidia,pins = 316 nvidia,pins = "vi_d0_pt4",
317 317 "vi_d1_pd5",
318 318 "vi_d2_pl0",
319 319 "vi_d3_pl1",
320 320 "vi_d4_pl2",
321 321 "vi_d5_pl3",
322 322 "vi_d6_pl4",
323 323 "vi_d7_pl5",
324 324 "vi_d8_pl6",
325 325 "vi_d9_pl7",
326 326 "vi_d10_pt2",
327 327 "vi_d11_pt3",
328 328 "vi_hsync_pd7",
329 329 "vi_pclk_pt0",
330 330 "vi_vsync_pd6";
331 nvidia,functio 331 nvidia,function = "vi";
332 nvidia,pull = 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
333 nvidia,tristat 333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
334 nvidia,enable- 334 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
335 }; 335 };
336 /* Multiplexed and the 336 /* Multiplexed and therefore disabled */
337 kb-col2-pq2 { 337 kb-col2-pq2 {
338 nvidia,pins = 338 nvidia,pins = "kb_col2_pq2",
339 339 "kb_col3_pq3",
340 340 "kb_col4_pq4",
341 341 "kb_row4_pr4";
342 nvidia,functio 342 nvidia,function = "rsvd4";
343 nvidia,pull = 343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
344 nvidia,tristat 344 nvidia,tristate = <TEGRA_PIN_ENABLE>;
345 nvidia,enable- 345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
346 }; 346 };
347 kb-row0-pr0 { 347 kb-row0-pr0 {
348 nvidia,pins = 348 nvidia,pins = "kb_row0_pr0",
349 349 "kb_row1_pr1",
350 350 "kb_row2_pr2",
351 351 "kb_row3_pr3";
352 nvidia,functio 352 nvidia,function = "rsvd3";
353 nvidia,pull = 353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354 nvidia,tristat 354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
355 nvidia,enable- 355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 }; 356 };
357 kb-row5-pr5 { 357 kb-row5-pr5 {
358 nvidia,pins = 358 nvidia,pins = "kb_row5_pr5",
359 359 "kb_row6_pr6",
360 360 "kb_row7_pr7";
361 nvidia,functio 361 nvidia,function = "kbc";
362 nvidia,pull = 362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
363 nvidia,tristat 363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
364 nvidia,enable- 364 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
365 }; 365 };
366 /* 366 /*
367 * VI level-shifter di 367 * VI level-shifter direction
368 * (pull-down => defau 368 * (pull-down => default direction input)
369 */ 369 */
370 vi-mclk-pt1 { 370 vi-mclk-pt1 {
371 nvidia,pins = 371 nvidia,pins = "vi_mclk_pt1";
372 nvidia,functio 372 nvidia,function = "vi_alt3";
373 nvidia,pull = 373 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
374 nvidia,tristat 374 nvidia,tristate = <TEGRA_PIN_ENABLE>;
375 nvidia,enable- 375 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
376 }; 376 };
377 377
378 /* Apalis PWM1 */ 378 /* Apalis PWM1 */
379 pu6 { 379 pu6 {
380 nvidia,pins = 380 nvidia,pins = "pu6";
381 nvidia,functio 381 nvidia,function = "pwm3";
382 nvidia,pull = 382 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
383 nvidia,tristat 383 nvidia,tristate = <TEGRA_PIN_DISABLE>;
384 }; 384 };
385 385
386 /* Apalis PWM2 */ 386 /* Apalis PWM2 */
387 pu5 { 387 pu5 {
388 nvidia,pins = 388 nvidia,pins = "pu5";
389 nvidia,functio 389 nvidia,function = "pwm2";
390 nvidia,pull = 390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
391 nvidia,tristat 391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
392 }; 392 };
393 393
394 /* Apalis PWM3 */ 394 /* Apalis PWM3 */
395 pu4 { 395 pu4 {
396 nvidia,pins = 396 nvidia,pins = "pu4";
397 nvidia,functio 397 nvidia,function = "pwm1";
398 nvidia,pull = 398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristat 399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 }; 400 };
401 401
402 /* Apalis PWM4 */ 402 /* Apalis PWM4 */
403 pu3 { 403 pu3 {
404 nvidia,pins = 404 nvidia,pins = "pu3";
405 nvidia,functio 405 nvidia,function = "pwm0";
406 nvidia,pull = 406 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407 nvidia,tristat 407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 }; 408 };
409 409
410 /* Apalis RESET_MOCI# 410 /* Apalis RESET_MOCI# */
411 gmi-rst-n-pi4 { 411 gmi-rst-n-pi4 {
412 nvidia,pins = 412 nvidia,pins = "gmi_rst_n_pi4";
413 nvidia,functio 413 nvidia,function = "gmi";
414 nvidia,pull = 414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
415 nvidia,tristat 415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
416 }; 416 };
417 417
418 /* Apalis SATA1_ACT# * 418 /* Apalis SATA1_ACT# */
419 pex-l0-prsnt-n-pdd0 { 419 pex-l0-prsnt-n-pdd0 {
420 nvidia,pins = 420 nvidia,pins = "pex_l0_prsnt_n_pdd0";
421 nvidia,functio 421 nvidia,function = "rsvd3";
422 nvidia,pull = 422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
423 nvidia,tristat 423 nvidia,tristate = <TEGRA_PIN_DISABLE>;
424 nvidia,enable- 424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
425 }; 425 };
426 426
427 /* Apalis SD1 */ 427 /* Apalis SD1 */
428 sdmmc1-clk-pz0 { 428 sdmmc1-clk-pz0 {
429 nvidia,pins = 429 nvidia,pins = "sdmmc1_clk_pz0";
430 nvidia,functio 430 nvidia,function = "sdmmc1";
431 nvidia,pull = 431 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
432 nvidia,tristat 432 nvidia,tristate = <TEGRA_PIN_DISABLE>;
433 }; 433 };
434 sdmmc1-cmd-pz1 { 434 sdmmc1-cmd-pz1 {
435 nvidia,pins = 435 nvidia,pins = "sdmmc1_cmd_pz1",
436 436 "sdmmc1_dat0_py7",
437 437 "sdmmc1_dat1_py6",
438 438 "sdmmc1_dat2_py5",
439 439 "sdmmc1_dat3_py4";
440 nvidia,functio 440 nvidia,function = "sdmmc1";
441 nvidia,pull = 441 nvidia,pull = <TEGRA_PIN_PULL_UP>;
442 nvidia,tristat 442 nvidia,tristate = <TEGRA_PIN_DISABLE>;
443 }; 443 };
444 /* Apalis SD1_CD# */ 444 /* Apalis SD1_CD# */
445 clk2-req-pcc5 { 445 clk2-req-pcc5 {
446 nvidia,pins = 446 nvidia,pins = "clk2_req_pcc5";
447 nvidia,functio 447 nvidia,function = "rsvd2";
448 nvidia,pull = 448 nvidia,pull = <TEGRA_PIN_PULL_UP>;
449 nvidia,tristat 449 nvidia,tristate = <TEGRA_PIN_DISABLE>;
450 nvidia,enable- 450 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
451 }; 451 };
452 452
453 /* Apalis SPDIF1 */ 453 /* Apalis SPDIF1 */
454 spdif-out-pk5 { 454 spdif-out-pk5 {
455 nvidia,pins = 455 nvidia,pins = "spdif_out_pk5",
456 456 "spdif_in_pk6";
457 nvidia,functio 457 nvidia,function = "spdif";
458 nvidia,pull = 458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459 nvidia,tristat 459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
460 nvidia,enable- 460 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
461 }; 461 };
462 462
463 /* Apalis SPI1 */ 463 /* Apalis SPI1 */
464 spi1-sck-px5 { 464 spi1-sck-px5 {
465 nvidia,pins = 465 nvidia,pins = "spi1_sck_px5",
466 466 "spi1_mosi_px4",
467 467 "spi1_miso_px7",
468 468 "spi1_cs0_n_px6";
469 nvidia,functio 469 nvidia,function = "spi1";
470 nvidia,pull = 470 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
471 nvidia,tristat 471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
472 }; 472 };
473 473
474 /* Apalis SPI2 */ 474 /* Apalis SPI2 */
475 lcd-sck-pz4 { 475 lcd-sck-pz4 {
476 nvidia,pins = 476 nvidia,pins = "lcd_sck_pz4",
477 477 "lcd_sdout_pn5",
478 478 "lcd_sdin_pz2",
479 479 "lcd_cs0_n_pn4";
480 nvidia,functio 480 nvidia,function = "spi5";
481 nvidia,pull = 481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482 nvidia,tristat 482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
483 }; 483 };
484 484
485 /* 485 /*
486 * Apalis TS (Low-spee 486 * Apalis TS (Low-speed type specific)
487 * pins may be used as 487 * pins may be used as GPIOs
488 */ 488 */
489 kb-col5-pq5 { 489 kb-col5-pq5 {
490 nvidia,pins = 490 nvidia,pins = "kb_col5_pq5";
491 nvidia,functio 491 nvidia,function = "rsvd4";
492 nvidia,pull = 492 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
493 nvidia,tristat 493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
494 nvidia,enable- 494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495 }; 495 };
496 kb-col6-pq6 { 496 kb-col6-pq6 {
497 nvidia,pins = 497 nvidia,pins = "kb_col6_pq6",
498 498 "kb_col7_pq7",
499 499 "kb_row8_ps0",
500 500 "kb_row9_ps1";
501 nvidia,functio 501 nvidia,function = "kbc";
502 nvidia,pull = 502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
503 nvidia,tristat 503 nvidia,tristate = <TEGRA_PIN_DISABLE>;
504 nvidia,enable- 504 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
505 }; 505 };
506 506
507 /* Apalis UART1 */ 507 /* Apalis UART1 */
508 ulpi-data0 { 508 ulpi-data0 {
509 nvidia,pins = 509 nvidia,pins = "ulpi_data0_po1",
510 510 "ulpi_data1_po2",
511 511 "ulpi_data2_po3",
512 512 "ulpi_data3_po4",
513 513 "ulpi_data4_po5",
514 514 "ulpi_data5_po6",
515 515 "ulpi_data6_po7",
516 516 "ulpi_data7_po0";
517 nvidia,functio 517 nvidia,function = "uarta";
518 nvidia,pull = 518 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
519 nvidia,tristat 519 nvidia,tristate = <TEGRA_PIN_DISABLE>;
520 }; 520 };
521 521
522 /* Apalis UART2 */ 522 /* Apalis UART2 */
523 ulpi-clk-py0 { 523 ulpi-clk-py0 {
524 nvidia,pins = 524 nvidia,pins = "ulpi_clk_py0",
525 525 "ulpi_dir_py1",
526 526 "ulpi_nxt_py2",
527 527 "ulpi_stp_py3";
528 nvidia,functio 528 nvidia,function = "uartd";
529 nvidia,pull = 529 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
530 nvidia,tristat 530 nvidia,tristate = <TEGRA_PIN_DISABLE>;
531 }; 531 };
532 532
533 /* Apalis UART3 */ 533 /* Apalis UART3 */
534 uart2-rxd-pc3 { 534 uart2-rxd-pc3 {
535 nvidia,pins = 535 nvidia,pins = "uart2_rxd_pc3",
536 536 "uart2_txd_pc2";
537 nvidia,functio 537 nvidia,function = "uartb";
538 nvidia,pull = 538 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
539 nvidia,tristat 539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
540 }; 540 };
541 541
542 /* Apalis UART4 */ 542 /* Apalis UART4 */
543 uart3-rxd-pw7 { 543 uart3-rxd-pw7 {
544 nvidia,pins = 544 nvidia,pins = "uart3_rxd_pw7",
545 545 "uart3_txd_pw6";
546 nvidia,functio 546 nvidia,function = "uartc";
547 nvidia,pull = 547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548 nvidia,tristat 548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
549 }; 549 };
550 550
551 /* Apalis USBH_EN */ 551 /* Apalis USBH_EN */
552 pex-l0-rst-n-pdd1 { 552 pex-l0-rst-n-pdd1 {
553 nvidia,pins = 553 nvidia,pins = "pex_l0_rst_n_pdd1";
554 nvidia,functio 554 nvidia,function = "rsvd3";
555 nvidia,pull = 555 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
556 nvidia,tristat 556 nvidia,tristate = <TEGRA_PIN_DISABLE>;
557 nvidia,enable- 557 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
558 }; 558 };
559 559
560 /* Apalis USBH_OC# */ 560 /* Apalis USBH_OC# */
561 pex-l0-clkreq-n-pdd2 { 561 pex-l0-clkreq-n-pdd2 {
562 nvidia,pins = 562 nvidia,pins = "pex_l0_clkreq_n_pdd2";
563 nvidia,functio 563 nvidia,function = "rsvd3";
564 nvidia,pull = 564 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565 nvidia,tristat 565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
566 nvidia,enable- 566 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567 }; 567 };
568 568
569 /* Apalis USBO1_EN */ 569 /* Apalis USBO1_EN */
570 gen2-i2c-scl-pt5 { 570 gen2-i2c-scl-pt5 {
571 nvidia,pins = 571 nvidia,pins = "gen2_i2c_scl_pt5";
572 nvidia,functio 572 nvidia,function = "rsvd4";
573 nvidia,open-dr 573 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
574 nvidia,pull = 574 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
575 nvidia,tristat 575 nvidia,tristate = <TEGRA_PIN_DISABLE>;
576 }; 576 };
577 577
578 /* Apalis USBO1_OC# */ 578 /* Apalis USBO1_OC# */
579 gen2-i2c-sda-pt6 { 579 gen2-i2c-sda-pt6 {
580 nvidia,pins = 580 nvidia,pins = "gen2_i2c_sda_pt6";
581 nvidia,functio 581 nvidia,function = "rsvd4";
582 nvidia,open-dr 582 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
583 nvidia,pull = 583 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584 nvidia,tristat 584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
585 nvidia,enable- 585 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586 }; 586 };
587 587
588 /* Apalis VGA1 not sup 588 /* Apalis VGA1 not supported and therefore disabled */
589 crt-hsync-pv6 { 589 crt-hsync-pv6 {
590 nvidia,pins = 590 nvidia,pins = "crt_hsync_pv6",
591 591 "crt_vsync_pv7";
592 nvidia,functio 592 nvidia,function = "rsvd2";
593 nvidia,pull = 593 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
594 nvidia,tristat 594 nvidia,tristate = <TEGRA_PIN_ENABLE>;
595 nvidia,enable- 595 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
596 }; 596 };
597 597
598 /* Apalis WAKE1_MICO * 598 /* Apalis WAKE1_MICO */
599 pv1 { 599 pv1 {
600 nvidia,pins = 600 nvidia,pins = "pv1";
601 nvidia,functio 601 nvidia,function = "rsvd1";
602 nvidia,pull = 602 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
603 nvidia,tristat 603 nvidia,tristate = <TEGRA_PIN_DISABLE>;
604 nvidia,enable- 604 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
605 }; 605 };
606 606
607 /* eMMC (On-module) */ 607 /* eMMC (On-module) */
608 sdmmc4-clk-pcc4 { 608 sdmmc4-clk-pcc4 {
609 nvidia,pins = 609 nvidia,pins = "sdmmc4_clk_pcc4",
610 610 "sdmmc4_cmd_pt7",
611 611 "sdmmc4_rst_n_pcc3";
612 nvidia,functio 612 nvidia,function = "sdmmc4";
613 nvidia,pull = 613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
614 nvidia,tristat 614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable- 615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
616 }; 616 };
617 sdmmc4-dat0-paa0 { 617 sdmmc4-dat0-paa0 {
618 nvidia,pins = 618 nvidia,pins = "sdmmc4_dat0_paa0",
619 619 "sdmmc4_dat1_paa1",
620 620 "sdmmc4_dat2_paa2",
621 621 "sdmmc4_dat3_paa3",
622 622 "sdmmc4_dat4_paa4",
623 623 "sdmmc4_dat5_paa5",
624 624 "sdmmc4_dat6_paa6",
625 625 "sdmmc4_dat7_paa7";
626 nvidia,functio 626 nvidia,function = "sdmmc4";
627 nvidia,pull = 627 nvidia,pull = <TEGRA_PIN_PULL_UP>;
628 nvidia,tristat 628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
629 nvidia,enable- 629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
630 }; 630 };
631 631
632 /* LAN i210/i211 DEV_O 632 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
633 pex-l2-prsnt-n-pdd7 { 633 pex-l2-prsnt-n-pdd7 {
634 nvidia,pins = 634 nvidia,pins = "pex_l2_prsnt_n_pdd7",
635 635 "pex_l2_rst_n_pcc6";
636 nvidia,functio 636 nvidia,function = "pcie";
637 nvidia,pull = 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristat 638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable- 639 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
640 }; 640 };
641 /* LAN i210/i211 PE_WA 641 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
642 pex-wake-n-pdd3 { 642 pex-wake-n-pdd3 {
643 nvidia,pins = 643 nvidia,pins = "pex_wake_n_pdd3",
644 644 "pex_l2_clkreq_n_pcc7";
645 nvidia,functio 645 nvidia,function = "pcie";
646 nvidia,pull = 646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
647 nvidia,tristat 647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
648 nvidia,enable- 648 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
649 }; 649 };
650 /* LAN i210/i211 SMB_A 650 /* LAN i210/i211 SMB_ALERT_N (On-module) */
651 sys-clk-req-pz5 { 651 sys-clk-req-pz5 {
652 nvidia,pins = 652 nvidia,pins = "sys_clk_req_pz5";
653 nvidia,functio 653 nvidia,function = "rsvd2";
654 nvidia,pull = 654 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
655 nvidia,tristat 655 nvidia,tristate = <TEGRA_PIN_DISABLE>;
656 nvidia,enable- 656 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
657 }; 657 };
658 658
659 /* LVDS Transceiver Co 659 /* LVDS Transceiver Configuration */
660 pbb0 { 660 pbb0 {
661 nvidia,pins = 661 nvidia,pins = "pbb0",
662 662 "pbb7",
663 663 "pcc1",
664 664 "pcc2";
665 nvidia,functio 665 nvidia,function = "rsvd2";
666 nvidia,pull = 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
667 nvidia,tristat 667 nvidia,tristate = <TEGRA_PIN_DISABLE>;
668 nvidia,enable- 668 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
669 }; 669 };
670 pbb3 { 670 pbb3 {
671 nvidia,pins = 671 nvidia,pins = "pbb3",
672 672 "pbb4",
673 673 "pbb5",
674 674 "pbb6";
675 nvidia,functio 675 nvidia,function = "displayb";
676 nvidia,pull = 676 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
677 nvidia,tristat 677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
678 nvidia,enable- 678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
679 }; 679 };
680 680
681 /* Not connected and t 681 /* Not connected and therefore disabled */
682 clk-32k-out-pa0 { 682 clk-32k-out-pa0 {
683 nvidia,pins = 683 nvidia,pins = "clk3_out_pee0",
684 684 "clk3_req_pee1",
685 685 "clk_32k_out_pa0",
686 686 "dap4_din_pp5",
687 687 "dap4_dout_pp6",
688 688 "dap4_fs_pp4",
689 689 "dap4_sclk_pp7";
690 nvidia,functio 690 nvidia,function = "rsvd2";
691 nvidia,pull = 691 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
692 nvidia,tristat 692 nvidia,tristate = <TEGRA_PIN_ENABLE>;
693 nvidia,enable- 693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 }; 694 };
695 dap2-fs-pa2 { 695 dap2-fs-pa2 {
696 nvidia,pins = 696 nvidia,pins = "dap2_fs_pa2",
697 697 "dap2_sclk_pa3",
698 698 "dap2_din_pa4",
699 699 "dap2_dout_pa5",
700 700 "lcd_dc0_pn6",
701 701 "lcd_m1_pw1",
702 702 "lcd_pwr1_pc1",
703 703 "pex_l1_clkreq_n_pdd6",
704 704 "pex_l1_prsnt_n_pdd4",
705 705 "pex_l1_rst_n_pdd5";
706 nvidia,functio 706 nvidia,function = "rsvd3";
707 nvidia,pull = 707 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
708 nvidia,tristat 708 nvidia,tristate = <TEGRA_PIN_ENABLE>;
709 nvidia,enable- 709 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
710 }; 710 };
711 gmi-ad0-pg0 { 711 gmi-ad0-pg0 {
712 nvidia,pins = 712 nvidia,pins = "gmi_ad0_pg0",
713 713 "gmi_ad2_pg2",
714 714 "gmi_ad3_pg3",
715 715 "gmi_ad4_pg4",
716 716 "gmi_ad5_pg5",
717 717 "gmi_ad6_pg6",
718 718 "gmi_ad7_pg7",
719 719 "gmi_ad8_ph0",
720 720 "gmi_ad9_ph1",
721 721 "gmi_ad10_ph2",
722 722 "gmi_ad11_ph3",
723 723 "gmi_ad12_ph4",
724 724 "gmi_ad13_ph5",
725 725 "gmi_ad14_ph6",
726 726 "gmi_ad15_ph7",
727 727 "gmi_adv_n_pk0",
728 728 "gmi_clk_pk1",
729 729 "gmi_cs4_n_pk2",
730 730 "gmi_cs2_n_pk3",
731 731 "gmi_dqs_pi2",
732 732 "gmi_iordy_pi5",
733 733 "gmi_oe_n_pi1",
734 734 "gmi_wait_pi7",
735 735 "gmi_wr_n_pi0",
736 736 "lcd_cs1_n_pw0",
737 737 "pu0",
738 738 "pu1",
739 739 "pu2";
740 nvidia,functio 740 nvidia,function = "rsvd4";
741 nvidia,pull = 741 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
742 nvidia,tristat 742 nvidia,tristate = <TEGRA_PIN_ENABLE>;
743 nvidia,enable- 743 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
744 }; 744 };
745 gmi-cs0-n-pj0 { 745 gmi-cs0-n-pj0 {
746 nvidia,pins = 746 nvidia,pins = "gmi_cs0_n_pj0",
747 747 "gmi_cs1_n_pj2",
748 748 "gmi_cs3_n_pk4";
749 nvidia,functio 749 nvidia,function = "rsvd1";
750 nvidia,pull = 750 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
751 nvidia,tristat 751 nvidia,tristate = <TEGRA_PIN_ENABLE>;
752 nvidia,enable- 752 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
753 }; 753 };
754 gmi-cs6-n-pi3 { 754 gmi-cs6-n-pi3 {
755 nvidia,pins = 755 nvidia,pins = "gmi_cs6_n_pi3";
756 nvidia,functio 756 nvidia,function = "sata";
757 nvidia,pull = 757 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
758 nvidia,tristat 758 nvidia,tristate = <TEGRA_PIN_ENABLE>;
759 nvidia,enable- 759 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
760 }; 760 };
761 gmi-cs7-n-pi6 { 761 gmi-cs7-n-pi6 {
762 nvidia,pins = 762 nvidia,pins = "gmi_cs7_n_pi6";
763 nvidia,functio 763 nvidia,function = "gmi_alt";
764 nvidia,pull = 764 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
765 nvidia,tristat 765 nvidia,tristate = <TEGRA_PIN_ENABLE>;
766 nvidia,enable- 766 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
767 }; 767 };
768 lcd-pwr0-pb2 { 768 lcd-pwr0-pb2 {
769 nvidia,pins = 769 nvidia,pins = "lcd_pwr0_pb2",
770 770 "lcd_pwr2_pc6",
771 771 "lcd_wr_n_pz3";
772 nvidia,functio 772 nvidia,function = "hdcp";
773 nvidia,pull = 773 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
774 nvidia,tristat 774 nvidia,tristate = <TEGRA_PIN_ENABLE>;
775 nvidia,enable- 775 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
776 }; 776 };
777 uart2-cts-n-pj5 { 777 uart2-cts-n-pj5 {
778 nvidia,pins = 778 nvidia,pins = "uart2_cts_n_pj5",
779 779 "uart2_rts_n_pj6";
780 nvidia,functio 780 nvidia,function = "gmi";
781 nvidia,pull = 781 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
782 nvidia,tristat 782 nvidia,tristate = <TEGRA_PIN_ENABLE>;
783 nvidia,enable- 783 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
784 }; 784 };
785 785
786 /* Power I2C (On-modul 786 /* Power I2C (On-module) */
787 pwr-i2c-scl-pz6 { 787 pwr-i2c-scl-pz6 {
788 nvidia,pins = 788 nvidia,pins = "pwr_i2c_scl_pz6",
789 789 "pwr_i2c_sda_pz7";
790 nvidia,functio 790 nvidia,function = "i2cpwr";
791 nvidia,pull = 791 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
792 nvidia,tristat 792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
793 nvidia,enable- 793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
794 nvidia,open-dr 794 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
795 }; 795 };
796 796
797 /* 797 /*
798 * THERMD_ALERT#, unla 798 * THERMD_ALERT#, unlatched I2C address pin of LM95245
799 * temperature sensor 799 * temperature sensor therefore requires disabling for
800 * now 800 * now
801 */ 801 */
802 lcd-dc1-pd2 { 802 lcd-dc1-pd2 {
803 nvidia,pins = 803 nvidia,pins = "lcd_dc1_pd2";
804 nvidia,functio 804 nvidia,function = "rsvd3";
805 nvidia,pull = 805 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
806 nvidia,tristat 806 nvidia,tristate = <TEGRA_PIN_ENABLE>;
807 nvidia,enable- 807 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
808 }; 808 };
809 809
810 /* TOUCH_PEN_INT# (On- 810 /* TOUCH_PEN_INT# (On-module) */
811 pv0 { 811 pv0 {
812 nvidia,pins = 812 nvidia,pins = "pv0";
813 nvidia,functio 813 nvidia,function = "rsvd1";
814 nvidia,pull = 814 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
815 nvidia,tristat 815 nvidia,tristate = <TEGRA_PIN_DISABLE>;
816 nvidia,enable- 816 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
817 }; 817 };
818 }; 818 };
819 }; 819 };
820 820
821 serial@70006040 { 821 serial@70006040 {
822 compatible = "nvidia,tegra30-h 822 compatible = "nvidia,tegra30-hsuart";
823 reset-names = "serial"; 823 reset-names = "serial";
824 /delete-property/ reg-shift; 824 /delete-property/ reg-shift;
825 }; 825 };
826 826
827 serial@70006200 { 827 serial@70006200 {
828 compatible = "nvidia,tegra30-h 828 compatible = "nvidia,tegra30-hsuart";
829 reset-names = "serial"; 829 reset-names = "serial";
830 /delete-property/ reg-shift; 830 /delete-property/ reg-shift;
831 }; 831 };
832 832
833 serial@70006300 { 833 serial@70006300 {
834 compatible = "nvidia,tegra30-h 834 compatible = "nvidia,tegra30-hsuart";
835 reset-names = "serial"; 835 reset-names = "serial";
836 /delete-property/ reg-shift; 836 /delete-property/ reg-shift;
837 }; 837 };
838 838
839 hdmi_ddc: i2c@7000c700 { 839 hdmi_ddc: i2c@7000c700 {
840 clock-frequency = <10000>; 840 clock-frequency = <10000>;
841 }; 841 };
842 842
843 /* 843 /*
844 * PWR_I2C: power I2C to audio codec, 844 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
845 * touch screen controller 845 * touch screen controller
846 */ 846 */
847 i2c@7000d000 { 847 i2c@7000d000 {
848 status = "okay"; 848 status = "okay";
849 clock-frequency = <100000>; 849 clock-frequency = <100000>;
850 850
851 /* SGTL5000 audio codec */ 851 /* SGTL5000 audio codec */
852 sgtl5000: codec@a { 852 sgtl5000: codec@a {
853 compatible = "fsl,sgtl 853 compatible = "fsl,sgtl5000";
854 reg = <0x0a>; 854 reg = <0x0a>;
855 #sound-dai-cells = <0> 855 #sound-dai-cells = <0>;
856 VDDA-supply = <®_mo 856 VDDA-supply = <®_module_3v3_audio>;
857 VDDD-supply = <®_1v 857 VDDD-supply = <®_1v8_vio>;
858 VDDIO-supply = <®_m 858 VDDIO-supply = <®_module_3v3>;
859 clocks = <&tegra_car T 859 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
860 }; 860 };
861 861
862 pmic: pmic@2d { 862 pmic: pmic@2d {
863 compatible = "ti,tps65 863 compatible = "ti,tps65911";
864 reg = <0x2d>; 864 reg = <0x2d>;
865 865
866 interrupts = <GIC_SPI 866 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
867 #interrupt-cells = <2> 867 #interrupt-cells = <2>;
868 interrupt-controller; 868 interrupt-controller;
869 wakeup-source; 869 wakeup-source;
870 870
871 ti,system-power-contro 871 ti,system-power-controller;
872 872
873 #gpio-cells = <2>; 873 #gpio-cells = <2>;
874 gpio-controller; 874 gpio-controller;
875 875
876 vcc1-supply = <®_mo 876 vcc1-supply = <®_module_3v3>;
877 vcc2-supply = <®_mo 877 vcc2-supply = <®_module_3v3>;
878 vcc3-supply = <®_1v 878 vcc3-supply = <®_1v8_vio>;
879 vcc4-supply = <®_mo 879 vcc4-supply = <®_module_3v3>;
880 vcc5-supply = <®_mo 880 vcc5-supply = <®_module_3v3>;
881 vcc6-supply = <®_1v 881 vcc6-supply = <®_1v8_vio>;
882 vcc7-supply = <®_5v 882 vcc7-supply = <®_5v0_charge_pump>;
883 vccio-supply = <®_m 883 vccio-supply = <®_module_3v3>;
884 884
885 regulators { 885 regulators {
886 vdd1_reg: vdd1 886 vdd1_reg: vdd1 {
887 regula 887 regulator-name = "+V1.35_VDDIO_DDR";
888 regula 888 regulator-min-microvolt = <1350000>;
889 regula 889 regulator-max-microvolt = <1350000>;
890 regula 890 regulator-always-on;
891 }; 891 };
892 892
893 vdd2_reg: vdd2 893 vdd2_reg: vdd2 {
894 regula 894 regulator-name = "+V1.05";
895 regula 895 regulator-min-microvolt = <1050000>;
896 regula 896 regulator-max-microvolt = <1050000>;
897 }; 897 };
898 898
899 vddctrl_reg: v 899 vddctrl_reg: vddctrl {
900 regula 900 regulator-name = "+V1.0_VDD_CPU";
901 regula 901 regulator-min-microvolt = <1150000>;
902 regula 902 regulator-max-microvolt = <1150000>;
903 regula 903 regulator-always-on;
904 }; 904 };
905 905
906 reg_1v8_vio: v 906 reg_1v8_vio: vio {
907 regula 907 regulator-name = "+V1.8";
908 regula 908 regulator-min-microvolt = <1800000>;
909 regula 909 regulator-max-microvolt = <1800000>;
910 regula 910 regulator-always-on;
911 }; 911 };
912 912
913 /* LDO1: unuse 913 /* LDO1: unused */
914 914
915 /* 915 /*
916 * EN_+V3.3 sw 916 * EN_+V3.3 switching via FET:
917 * +V3.3_AUDIO 917 * +V3.3_AUDIO_AVDD_S, +V3.3
918 * see also +V 918 * see also +V3.3 fixed supply
919 */ 919 */
920 ldo2_reg: ldo2 920 ldo2_reg: ldo2 {
921 regula 921 regulator-name = "EN_+V3.3";
922 regula 922 regulator-min-microvolt = <3300000>;
923 regula 923 regulator-max-microvolt = <3300000>;
924 regula 924 regulator-always-on;
925 }; 925 };
926 926
927 ldo3_reg: ldo3 927 ldo3_reg: ldo3 {
928 regula 928 regulator-name = "+V1.2_CSI";
929 regula 929 regulator-min-microvolt = <1200000>;
930 regula 930 regulator-max-microvolt = <1200000>;
931 }; 931 };
932 932
933 ldo4_reg: ldo4 933 ldo4_reg: ldo4 {
934 regula 934 regulator-name = "+V1.2_VDD_RTC";
935 regula 935 regulator-min-microvolt = <1200000>;
936 regula 936 regulator-max-microvolt = <1200000>;
937 regula 937 regulator-always-on;
938 }; 938 };
939 939
940 /* 940 /*
941 * +V2.8_AVDD_ 941 * +V2.8_AVDD_VDAC:
942 * only requir 942 * only required for (unsupported) analog RGB
943 */ 943 */
944 ldo5_reg: ldo5 944 ldo5_reg: ldo5 {
945 regula 945 regulator-name = "+V2.8_AVDD_VDAC";
946 regula 946 regulator-min-microvolt = <2800000>;
947 regula 947 regulator-max-microvolt = <2800000>;
948 regula 948 regulator-always-on;
949 }; 949 };
950 950
951 /* 951 /*
952 * +V1.05_AVDD 952 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
953 * but LDO6 ca 953 * but LDO6 can't set voltage in 50mV
954 * granularity 954 * granularity
955 */ 955 */
956 ldo6_reg: ldo6 956 ldo6_reg: ldo6 {
957 regula 957 regulator-name = "+V1.05_AVDD_PLLE";
958 regula 958 regulator-min-microvolt = <1100000>;
959 regula 959 regulator-max-microvolt = <1100000>;
960 }; 960 };
961 961
962 ldo7_reg: ldo7 962 ldo7_reg: ldo7 {
963 regula 963 regulator-name = "+V1.2_AVDD_PLL";
964 regula 964 regulator-min-microvolt = <1200000>;
965 regula 965 regulator-max-microvolt = <1200000>;
966 regula 966 regulator-always-on;
967 }; 967 };
968 968
969 ldo8_reg: ldo8 969 ldo8_reg: ldo8 {
970 regula 970 regulator-name = "+V1.0_VDD_DDR_HS";
971 regula 971 regulator-min-microvolt = <1000000>;
972 regula 972 regulator-max-microvolt = <1000000>;
973 regula 973 regulator-always-on;
974 }; 974 };
975 }; 975 };
976 }; 976 };
977 977
978 /* STMPE811 touch screen contr 978 /* STMPE811 touch screen controller */
979 touchscreen@41 { 979 touchscreen@41 {
980 compatible = "st,stmpe 980 compatible = "st,stmpe811";
981 reg = <0x41>; 981 reg = <0x41>;
982 irq-gpio = <&gpio TEGR 982 irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
983 id = <0>; 983 id = <0>;
984 blocks = <0x5>; 984 blocks = <0x5>;
985 irq-trigger = <0x1>; 985 irq-trigger = <0x1>;
986 /* 3.25 MHz ADC clock 986 /* 3.25 MHz ADC clock speed */
987 st,adc-freq = <1>; 987 st,adc-freq = <1>;
988 /* 12-bit ADC */ 988 /* 12-bit ADC */
989 st,mod-12b = <1>; 989 st,mod-12b = <1>;
990 /* internal ADC refere 990 /* internal ADC reference */
991 st,ref-sel = <0>; 991 st,ref-sel = <0>;
992 /* ADC converstion tim 992 /* ADC converstion time: 80 clocks */
993 st,sample-time = <4>; 993 st,sample-time = <4>;
994 994
995 stmpe_adc { 995 stmpe_adc {
996 compatible = " 996 compatible = "st,stmpe-adc";
997 /* forbid to u 997 /* forbid to use ADC channels 3-0 (touch) */
998 st,norequest-m 998 st,norequest-mask = <0x0F>;
999 }; 999 };
1000 1000
1001 stmpe_touchscreen { 1001 stmpe_touchscreen {
1002 compatible = 1002 compatible = "st,stmpe-ts";
1003 /* 8 sample a 1003 /* 8 sample average control */
1004 st,ave-ctrl = 1004 st,ave-ctrl = <3>;
1005 /* 7 length f 1005 /* 7 length fractional part in z */
1006 st,fraction-z 1006 st,fraction-z = <7>;
1007 /* 1007 /*
1008 * 50 mA typi 1008 * 50 mA typical 80 mA max touchscreen drivers
1009 * current li 1009 * current limit value
1010 */ 1010 */
1011 st,i-drive = 1011 st,i-drive = <1>;
1012 /* 1 ms panel 1012 /* 1 ms panel driver settling time */
1013 st,settling = 1013 st,settling = <3>;
1014 /* 5 ms touch 1014 /* 5 ms touch detect interrupt delay */
1015 st,touch-det- 1015 st,touch-det-delay = <5>;
1016 }; 1016 };
1017 }; 1017 };
1018 1018
1019 /* 1019 /*
1020 * LM95245 temperature sensor 1020 * LM95245 temperature sensor
1021 * Note: OVERT1# directly con 1021 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1022 */ 1022 */
1023 temp-sensor@4c { 1023 temp-sensor@4c {
1024 compatible = "nationa 1024 compatible = "national,lm95245";
1025 reg = <0x4c>; 1025 reg = <0x4c>;
1026 }; 1026 };
1027 1027
1028 /* SW: +V1.2_VDD_CORE */ 1028 /* SW: +V1.2_VDD_CORE */
1029 regulator@60 { 1029 regulator@60 {
1030 compatible = "ti,tps6 1030 compatible = "ti,tps62362";
1031 reg = <0x60>; 1031 reg = <0x60>;
1032 1032
1033 regulator-name = "tps 1033 regulator-name = "tps62362-vout";
1034 regulator-min-microvo 1034 regulator-min-microvolt = <900000>;
1035 regulator-max-microvo 1035 regulator-max-microvolt = <1400000>;
1036 regulator-boot-on; 1036 regulator-boot-on;
1037 regulator-always-on; 1037 regulator-always-on;
1038 }; 1038 };
1039 }; 1039 };
1040 1040
1041 /* SPI4: CAN2 */ 1041 /* SPI4: CAN2 */
1042 spi@7000da00 { 1042 spi@7000da00 {
1043 status = "okay"; 1043 status = "okay";
1044 spi-max-frequency = <10000000 1044 spi-max-frequency = <10000000>;
1045 1045
1046 can@1 { 1046 can@1 {
1047 compatible = "microch 1047 compatible = "microchip,mcp2515";
1048 reg = <1>; 1048 reg = <1>;
1049 clocks = <&clk16m>; 1049 clocks = <&clk16m>;
1050 interrupt-parent = <& 1050 interrupt-parent = <&gpio>;
1051 interrupts = <TEGRA_G 1051 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1052 spi-max-frequency = < 1052 spi-max-frequency = <10000000>;
1053 }; 1053 };
1054 }; 1054 };
1055 1055
1056 /* SPI6: CAN1 */ 1056 /* SPI6: CAN1 */
1057 spi@7000de00 { 1057 spi@7000de00 {
1058 status = "okay"; 1058 status = "okay";
1059 spi-max-frequency = <10000000 1059 spi-max-frequency = <10000000>;
1060 1060
1061 can@0 { 1061 can@0 {
1062 compatible = "microch 1062 compatible = "microchip,mcp2515";
1063 reg = <0>; 1063 reg = <0>;
1064 clocks = <&clk16m>; 1064 clocks = <&clk16m>;
1065 interrupt-parent = <& 1065 interrupt-parent = <&gpio>;
1066 interrupts = <TEGRA_G 1066 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1067 spi-max-frequency = < 1067 spi-max-frequency = <10000000>;
1068 }; 1068 };
1069 }; 1069 };
1070 1070
1071 pmc@7000e400 { 1071 pmc@7000e400 {
1072 nvidia,invert-interrupt; 1072 nvidia,invert-interrupt;
1073 nvidia,suspend-mode = <1>; 1073 nvidia,suspend-mode = <1>;
1074 nvidia,cpu-pwr-good-time = <5 1074 nvidia,cpu-pwr-good-time = <5000>;
1075 nvidia,cpu-pwr-off-time = <50 1075 nvidia,cpu-pwr-off-time = <5000>;
1076 nvidia,core-pwr-good-time = < 1076 nvidia,core-pwr-good-time = <3845 3845>;
1077 nvidia,core-pwr-off-time = <0 1077 nvidia,core-pwr-off-time = <0>;
1078 nvidia,core-power-req-active- 1078 nvidia,core-power-req-active-high;
1079 nvidia,sys-clock-req-active-h 1079 nvidia,sys-clock-req-active-high;
1080 1080
1081 /* Set DEV_OFF bit in DCDC co 1081 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1082 i2c-thermtrip { 1082 i2c-thermtrip {
1083 nvidia,i2c-controller 1083 nvidia,i2c-controller-id = <4>;
1084 nvidia,bus-addr = <0x 1084 nvidia,bus-addr = <0x2d>;
1085 nvidia,reg-addr = <0x 1085 nvidia,reg-addr = <0x3f>;
1086 nvidia,reg-data = <0x 1086 nvidia,reg-data = <0x1>;
1087 }; 1087 };
1088 }; 1088 };
1089 1089
1090 hda@70030000 { 1090 hda@70030000 {
1091 status = "okay"; 1091 status = "okay";
1092 }; 1092 };
1093 1093
1094 ahub@70080000 { 1094 ahub@70080000 {
1095 i2s@70080500 { 1095 i2s@70080500 {
1096 status = "okay"; 1096 status = "okay";
1097 }; 1097 };
1098 }; 1098 };
1099 1099
1100 /* eMMC */ 1100 /* eMMC */
1101 mmc@78000600 { 1101 mmc@78000600 {
1102 status = "okay"; 1102 status = "okay";
1103 bus-width = <8>; 1103 bus-width = <8>;
1104 non-removable; 1104 non-removable;
1105 vmmc-supply = <®_module_3v 1105 vmmc-supply = <®_module_3v3>; /* VCC */
1106 vqmmc-supply = <®_1v8_vio> 1106 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
1107 mmc-ddr-1_8v; 1107 mmc-ddr-1_8v;
1108 }; 1108 };
1109 1109
1110 clk16m: clock-osc4 { 1110 clk16m: clock-osc4 {
1111 compatible = "fixed-clock"; 1111 compatible = "fixed-clock";
1112 #clock-cells = <0>; 1112 #clock-cells = <0>;
1113 clock-frequency = <16000000>; 1113 clock-frequency = <16000000>;
1114 }; 1114 };
1115 1115
1116 clk32k_in: clock-xtal1 { 1116 clk32k_in: clock-xtal1 {
1117 compatible = "fixed-clock"; 1117 compatible = "fixed-clock";
1118 #clock-cells = <0>; 1118 #clock-cells = <0>;
1119 clock-frequency = <32768>; 1119 clock-frequency = <32768>;
1120 }; 1120 };
1121 1121
1122 reg_1v8_avdd_hdmi_pll: regulator-1v8- 1122 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1123 compatible = "regulator-fixed 1123 compatible = "regulator-fixed";
1124 regulator-name = "+V1.8_AVDD_ 1124 regulator-name = "+V1.8_AVDD_HDMI_PLL";
1125 regulator-min-microvolt = <18 1125 regulator-min-microvolt = <1800000>;
1126 regulator-max-microvolt = <18 1126 regulator-max-microvolt = <1800000>;
1127 enable-active-high; 1127 enable-active-high;
1128 gpio = <&pmic 6 GPIO_ACTIVE_H 1128 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1129 vin-supply = <®_1v8_vio>; 1129 vin-supply = <®_1v8_vio>;
1130 }; 1130 };
1131 1131
1132 reg_3v3_avdd_hdmi: regulator-3v3-avdd 1132 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1133 compatible = "regulator-fixed 1133 compatible = "regulator-fixed";
1134 regulator-name = "+V3.3_AVDD_ 1134 regulator-name = "+V3.3_AVDD_HDMI";
1135 regulator-min-microvolt = <33 1135 regulator-min-microvolt = <3300000>;
1136 regulator-max-microvolt = <33 1136 regulator-max-microvolt = <3300000>;
1137 enable-active-high; 1137 enable-active-high;
1138 gpio = <&pmic 6 GPIO_ACTIVE_H 1138 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1139 vin-supply = <®_module_3v3 1139 vin-supply = <®_module_3v3>;
1140 }; 1140 };
1141 1141
1142 reg_5v0_charge_pump: regulator-5v0-ch 1142 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1143 compatible = "regulator-fixed 1143 compatible = "regulator-fixed";
1144 regulator-name = "+V5.0"; 1144 regulator-name = "+V5.0";
1145 regulator-min-microvolt = <50 1145 regulator-min-microvolt = <5000000>;
1146 regulator-max-microvolt = <50 1146 regulator-max-microvolt = <5000000>;
1147 regulator-always-on; 1147 regulator-always-on;
1148 }; 1148 };
1149 1149
1150 reg_module_3v3: regulator-module-3v3 1150 reg_module_3v3: regulator-module-3v3 {
1151 compatible = "regulator-fixed 1151 compatible = "regulator-fixed";
1152 regulator-name = "+V3.3"; 1152 regulator-name = "+V3.3";
1153 regulator-min-microvolt = <33 1153 regulator-min-microvolt = <3300000>;
1154 regulator-max-microvolt = <33 1154 regulator-max-microvolt = <3300000>;
1155 regulator-always-on; 1155 regulator-always-on;
1156 }; 1156 };
1157 1157
1158 reg_module_3v3_audio: regulator-modul 1158 reg_module_3v3_audio: regulator-module-3v3-audio {
1159 compatible = "regulator-fixed 1159 compatible = "regulator-fixed";
1160 regulator-name = "+V3.3_AUDIO 1160 regulator-name = "+V3.3_AUDIO_AVDD_S";
1161 regulator-min-microvolt = <33 1161 regulator-min-microvolt = <3300000>;
1162 regulator-max-microvolt = <33 1162 regulator-max-microvolt = <3300000>;
1163 regulator-always-on; 1163 regulator-always-on;
1164 }; 1164 };
1165 1165
1166 sound { 1166 sound {
1167 compatible = "toradex,tegra-a 1167 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1168 "nvidia,tegra-au 1168 "nvidia,tegra-audio-sgtl5000";
1169 nvidia,model = "Toradex Apali 1169 nvidia,model = "Toradex Apalis T30";
1170 nvidia,audio-routing = 1170 nvidia,audio-routing =
1171 "Headphone Jack", "HP 1171 "Headphone Jack", "HP_OUT",
1172 "LINE_IN", "Line In J 1172 "LINE_IN", "Line In Jack",
1173 "MIC_IN", "Mic Jack"; 1173 "MIC_IN", "Mic Jack";
1174 nvidia,i2s-controller = <&teg 1174 nvidia,i2s-controller = <&tegra_i2s2>;
1175 nvidia,audio-codec = <&sgtl50 1175 nvidia,audio-codec = <&sgtl5000>;
1176 clocks = <&tegra_car TEGRA30_ 1176 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1177 <&tegra_car TEGRA30_ 1177 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1178 <&tegra_pmc TEGRA_PM 1178 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1179 clock-names = "pll_a", "pll_a 1179 clock-names = "pll_a", "pll_a_out0", "mclk";
1180 1180
1181 assigned-clocks = <&tegra_car 1181 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1182 <&tegra_pmc 1182 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1183 1183
1184 assigned-clock-parents = <&te 1184 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1185 <&te 1185 <&tegra_car TEGRA30_CLK_EXTERN1>;
1186 }; 1186 };
1187 }; 1187 };
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