1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 #include <dt-bindings/input/gpio-keys.h> 3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/power/summit,smb347-char 5 #include <dt-bindings/power/summit,smb347-charger.h>
6 #include <dt-bindings/thermal/thermal.h> 6 #include <dt-bindings/thermal/thermal.h>
7 7
8 #include "tegra30.dtsi" 8 #include "tegra30.dtsi"
9 #include "tegra30-cpu-opp.dtsi" 9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi" 11 #include "tegra30-asus-lvds-display.dtsi"
12 12
13 / { 13 / {
14 aliases { 14 aliases {
15 mmc0 = &sdmmc4; /* eMMC */ 15 mmc0 = &sdmmc4; /* eMMC */
16 mmc1 = &sdmmc3; /* WiFi */ 16 mmc1 = &sdmmc3; /* WiFi */
17 17
18 rtc0 = &pmic; 18 rtc0 = &pmic;
19 rtc1 = "/rtc@7000e000"; 19 rtc1 = "/rtc@7000e000";
20 20
21 serial1 = &uartc; /* Bluetooth 21 serial1 = &uartc; /* Bluetooth */
22 serial2 = &uartb; /* GPS */ 22 serial2 = &uartb; /* GPS */
23 }; 23 };
24 24
25 /* 25 /*
26 * The decompressor and also some boot 26 * The decompressor and also some bootloaders rely on a
27 * pre-existing /chosen node to be ava 27 * pre-existing /chosen node to be available to insert the
28 * command line and merge other ATAGS 28 * command line and merge other ATAGS info.
29 */ 29 */
30 chosen {}; 30 chosen {};
31 31
32 firmware { 32 firmware {
33 trusted-foundations { 33 trusted-foundations {
34 compatible = "tlm,trus 34 compatible = "tlm,trusted-foundations";
35 tlm,version-major = <0 35 tlm,version-major = <0x0>;
36 tlm,version-minor = <0 36 tlm,version-minor = <0x0>;
37 }; 37 };
38 }; 38 };
39 39
40 memory@80000000 { 40 memory@80000000 {
41 reg = <0x80000000 0x40000000>; 41 reg = <0x80000000 0x40000000>;
42 }; 42 };
43 43
44 reserved-memory { 44 reserved-memory {
45 #address-cells = <1>; 45 #address-cells = <1>;
46 #size-cells = <1>; 46 #size-cells = <1>;
47 ranges; 47 ranges;
48 48
49 linux,cma@80000000 { 49 linux,cma@80000000 {
50 compatible = "shared-d 50 compatible = "shared-dma-pool";
51 alloc-ranges = <0x8000 51 alloc-ranges = <0x80000000 0x30000000>;
52 size = <0x10000000>; / 52 size = <0x10000000>; /* 256MiB */
53 linux,cma-default; 53 linux,cma-default;
54 reusable; 54 reusable;
55 }; 55 };
56 56
57 ramoops@bfdf0000 { 57 ramoops@bfdf0000 {
58 compatible = "ramoops" 58 compatible = "ramoops";
59 reg = <0xbfdf0000 0x10 59 reg = <0xbfdf0000 0x10000>; /* 64kB */
60 console-size = <0x8000 60 console-size = <0x8000>; /* 32kB */
61 record-size = <0x400>; 61 record-size = <0x400>; /* 1kB */
62 ecc-size = <16>; 62 ecc-size = <16>;
63 }; 63 };
64 64
65 trustzone@bfe00000 { 65 trustzone@bfe00000 {
66 reg = <0xbfe00000 0x20 66 reg = <0xbfe00000 0x200000>;
67 no-map; 67 no-map;
68 }; 68 };
69 }; 69 };
70 70
71 gpio@6000d000 { 71 gpio@6000d000 {
72 init-low-power-mode-hog { 72 init-low-power-mode-hog {
73 gpio-hog; 73 gpio-hog;
74 gpios = <TEGRA_GPIO(I, 74 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
75 input; 75 input;
76 }; 76 };
77 77
78 init-mode-hog { 78 init-mode-hog {
79 gpio-hog; 79 gpio-hog;
80 gpios = <TEGRA_GPIO(DD 80 gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
81 <TEGRA_GPIO(CC 81 <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
82 <TEGRA_GPIO(R, 82 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
83 output-low; 83 output-low;
84 }; 84 };
85 }; 85 };
86 86
87 pinmux@70000868 { 87 pinmux@70000868 {
88 pinctrl-names = "default"; 88 pinctrl-names = "default";
89 pinctrl-0 = <&state_default>; 89 pinctrl-0 = <&state_default>;
90 90
91 state_default: pinmux { 91 state_default: pinmux {
92 clk_32k_out_pa0 { 92 clk_32k_out_pa0 {
93 nvidia,pins = 93 nvidia,pins = "clk_32k_out_pa0";
94 nvidia,functio 94 nvidia,function = "blink";
95 nvidia,pull = 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristat 96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 nvidia,enable- 97 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
98 }; 98 };
99 uart3_cts_n_pa1 { 99 uart3_cts_n_pa1 {
100 nvidia,pins = 100 nvidia,pins = "uart3_cts_n_pa1",
101 101 "uart3_rxd_pw7";
102 nvidia,functio 102 nvidia,function = "uartc";
103 nvidia,pull = 103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
104 nvidia,tristat 104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 nvidia,enable- 105 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
106 }; 106 };
107 dap2_fs_pa2 { 107 dap2_fs_pa2 {
108 nvidia,pins = 108 nvidia,pins = "dap2_fs_pa2",
109 109 "dap2_sclk_pa3",
110 110 "dap2_din_pa4",
111 111 "dap2_dout_pa5";
112 nvidia,functio 112 nvidia,function = "i2s1";
113 nvidia,pull = 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristat 114 nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 nvidia,enable- 115 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
116 }; 116 };
117 sdmmc3_clk_pa6 { 117 sdmmc3_clk_pa6 {
118 nvidia,pins = 118 nvidia,pins = "sdmmc3_clk_pa6";
119 nvidia,functio 119 nvidia,function = "sdmmc3";
120 nvidia,pull = 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristat 121 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,enable- 122 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
123 }; 123 };
124 sdmmc3_cmd_pa7 { 124 sdmmc3_cmd_pa7 {
125 nvidia,pins = 125 nvidia,pins = "sdmmc3_cmd_pa7",
126 126 "sdmmc3_dat3_pb4",
127 127 "sdmmc3_dat2_pb5",
128 128 "sdmmc3_dat1_pb6",
129 129 "sdmmc3_dat0_pb7",
130 130 "sdmmc3_dat4_pd1",
131 131 "sdmmc3_dat6_pd3",
132 132 "sdmmc3_dat7_pd4";
133 nvidia,functio 133 nvidia,function = "sdmmc3";
134 nvidia,pull = 134 nvidia,pull = <TEGRA_PIN_PULL_UP>;
135 nvidia,tristat 135 nvidia,tristate = <TEGRA_PIN_DISABLE>;
136 nvidia,enable- 136 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
137 }; 137 };
138 gmi_a17_pb0 { 138 gmi_a17_pb0 {
139 nvidia,pins = 139 nvidia,pins = "gmi_a17_pb0",
140 140 "gmi_a18_pb1";
141 nvidia,functio 141 nvidia,function = "uartd";
142 nvidia,pull = 142 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
143 nvidia,tristat 143 nvidia,tristate = <TEGRA_PIN_DISABLE>;
144 nvidia,enable- 144 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
145 }; 145 };
146 lcd_pwr0_pb2 { 146 lcd_pwr0_pb2 {
147 nvidia,pins = 147 nvidia,pins = "lcd_pwr0_pb2",
148 148 "lcd_pwr1_pc1",
149 149 "lcd_m1_pw1";
150 nvidia,functio 150 nvidia,function = "displaya";
151 nvidia,pull = 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
152 nvidia,tristat 152 nvidia,tristate = <TEGRA_PIN_DISABLE>;
153 nvidia,enable- 153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
154 }; 154 };
155 lcd_pclk_pb3 { 155 lcd_pclk_pb3 {
156 nvidia,pins = 156 nvidia,pins = "lcd_pclk_pb3",
157 157 "lcd_d0_pe0",
158 158 "lcd_d1_pe1",
159 159 "lcd_d2_pe2",
160 160 "lcd_d3_pe3",
161 161 "lcd_d4_pe4",
162 162 "lcd_d5_pe5",
163 163 "lcd_d6_pe6",
164 164 "lcd_d7_pe7",
165 165 "lcd_d8_pf0",
166 166 "lcd_d9_pf1",
167 167 "lcd_d10_pf2",
168 168 "lcd_d11_pf3",
169 169 "lcd_d12_pf4",
170 170 "lcd_d13_pf5",
171 171 "lcd_d14_pf6",
172 172 "lcd_d15_pf7",
173 173 "lcd_de_pj1",
174 174 "lcd_hsync_pj3",
175 175 "lcd_vsync_pj4",
176 176 "lcd_d16_pm0",
177 177 "lcd_d17_pm1",
178 178 "lcd_d18_pm2",
179 179 "lcd_d19_pm3",
180 180 "lcd_d20_pm4",
181 181 "lcd_d21_pm5",
182 182 "lcd_d22_pm6",
183 183 "lcd_d23_pm7",
184 184 "lcd_cs0_n_pn4",
185 185 "lcd_sdout_pn5",
186 186 "lcd_dc0_pn6",
187 187 "lcd_cs1_n_pw0",
188 188 "lcd_sdin_pz2",
189 189 "lcd_sck_pz4";
190 nvidia,functio 190 nvidia,function = "displaya";
191 nvidia,pull = 191 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
192 nvidia,tristat 192 nvidia,tristate = <TEGRA_PIN_DISABLE>;
193 nvidia,enable- 193 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
194 }; 194 };
195 uart3_rts_n_pc0 { 195 uart3_rts_n_pc0 {
196 nvidia,pins = 196 nvidia,pins = "uart3_rts_n_pc0",
197 197 "uart3_txd_pw6";
198 nvidia,functio 198 nvidia,function = "uartc";
199 nvidia,pull = 199 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristat 200 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable- 201 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
202 }; 202 };
203 uart2_txd_pc2 { 203 uart2_txd_pc2 {
204 nvidia,pins = 204 nvidia,pins = "uart2_txd_pc2",
205 205 "uart2_rts_n_pj6";
206 nvidia,functio 206 nvidia,function = "uartb";
207 nvidia,pull = 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristat 208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 nvidia,enable- 209 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
210 }; 210 };
211 uart2_rxd_pc3 { 211 uart2_rxd_pc3 {
212 nvidia,pins = 212 nvidia,pins = "uart2_rxd_pc3",
213 213 "uart2_cts_n_pj5";
214 nvidia,functio 214 nvidia,function = "uartb";
215 nvidia,pull = 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
216 nvidia,tristat 216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 nvidia,enable- 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
218 }; 218 };
219 gen1_i2c_scl_pc4 { 219 gen1_i2c_scl_pc4 {
220 nvidia,pins = 220 nvidia,pins = "gen1_i2c_scl_pc4",
221 221 "gen1_i2c_sda_pc5";
222 nvidia,functio 222 nvidia,function = "i2c1";
223 nvidia,pull = 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224 nvidia,tristat 224 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225 nvidia,enable- 225 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
226 nvidia,open-dr 226 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
227 }; 227 };
228 gmi_wp_n_pc7 { 228 gmi_wp_n_pc7 {
229 nvidia,pins = 229 nvidia,pins = "gmi_wp_n_pc7",
230 230 "gmi_wait_pi7",
231 231 "gmi_cs4_n_pk2",
232 232 "gmi_cs3_n_pk4";
233 nvidia,functio 233 nvidia,function = "rsvd1";
234 nvidia,pull = 234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristat 235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
236 nvidia,enable- 236 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
237 }; 237 };
238 gmi_ad12_ph4 { 238 gmi_ad12_ph4 {
239 nvidia,pins = 239 nvidia,pins = "gmi_ad12_ph4",
240 240 "gmi_cs0_n_pj0",
241 241 "gmi_cs1_n_pj2",
242 242 "gmi_cs2_n_pk3";
243 nvidia,functio 243 nvidia,function = "rsvd1";
244 nvidia,pull = 244 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
245 nvidia,tristat 245 nvidia,tristate = <TEGRA_PIN_ENABLE>;
246 nvidia,enable- 246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247 }; 247 };
248 sdmmc3_dat5_pd0 { 248 sdmmc3_dat5_pd0 {
249 nvidia,pins = 249 nvidia,pins = "sdmmc3_dat5_pd0";
250 nvidia,functio 250 nvidia,function = "sdmmc3";
251 nvidia,pull = 251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
252 nvidia,tristat 252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
253 nvidia,enable- 253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
254 }; 254 };
255 gmi_ad0_pg0 { 255 gmi_ad0_pg0 {
256 nvidia,pins = 256 nvidia,pins = "gmi_ad0_pg0",
257 257 "gmi_ad1_pg1",
258 258 "gmi_ad14_ph6",
259 259 "pu1";
260 nvidia,functio 260 nvidia,function = "rsvd1";
261 nvidia,pull = 261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristat 262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 nvidia,enable- 263 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
264 }; 264 };
265 gmi_ad2_pg2 { 265 gmi_ad2_pg2 {
266 nvidia,pins = 266 nvidia,pins = "gmi_ad2_pg2",
267 267 "gmi_ad3_pg3",
268 268 "gmi_ad6_pg6",
269 269 "gmi_ad7_pg7";
270 nvidia,functio 270 nvidia,function = "rsvd1";
271 nvidia,pull = 271 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
272 nvidia,tristat 272 nvidia,tristate = <TEGRA_PIN_DISABLE>;
273 nvidia,enable- 273 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
274 }; 274 };
275 gmi_ad4_pg4 { 275 gmi_ad4_pg4 {
276 nvidia,pins = 276 nvidia,pins = "gmi_ad4_pg4",
277 277 "gmi_ad5_pg5";
278 nvidia,functio 278 nvidia,function = "nand";
279 nvidia,pull = 279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
280 nvidia,tristat 280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
281 nvidia,enable- 281 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
282 }; 282 };
283 gmi_ad8_ph0 { 283 gmi_ad8_ph0 {
284 nvidia,pins = 284 nvidia,pins = "gmi_ad8_ph0";
285 nvidia,functio 285 nvidia,function = "pwm0";
286 nvidia,pull = 286 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287 nvidia,tristat 287 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 nvidia,enable- 288 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
289 }; 289 };
290 gmi_ad9_ph1 { 290 gmi_ad9_ph1 {
291 nvidia,pins = 291 nvidia,pins = "gmi_ad9_ph1";
292 nvidia,functio 292 nvidia,function = "rsvd4";
293 nvidia,pull = 293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
294 nvidia,tristat 294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
295 nvidia,enable- 295 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
296 }; 296 };
297 gmi_ad10_ph2 { 297 gmi_ad10_ph2 {
298 nvidia,pins = 298 nvidia,pins = "gmi_ad10_ph2";
299 nvidia,functio 299 nvidia,function = "pwm2";
300 nvidia,pull = 300 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
301 nvidia,tristat 301 nvidia,tristate = <TEGRA_PIN_ENABLE>;
302 nvidia,enable- 302 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
303 }; 303 };
304 gmi_ad11_ph3 { 304 gmi_ad11_ph3 {
305 nvidia,pins = 305 nvidia,pins = "gmi_ad11_ph3";
306 nvidia,functio 306 nvidia,function = "pwm3";
307 nvidia,pull = 307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristat 308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 nvidia,enable- 309 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
310 }; 310 };
311 gmi_ad13_ph5 { 311 gmi_ad13_ph5 {
312 nvidia,pins = 312 nvidia,pins = "gmi_ad13_ph5",
313 313 "gmi_wr_n_pi0",
314 314 "gmi_oe_n_pi1",
315 315 "gmi_adv_n_pk0";
316 nvidia,functio 316 nvidia,function = "rsvd1";
317 nvidia,pull = 317 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
318 nvidia,tristat 318 nvidia,tristate = <TEGRA_PIN_ENABLE>;
319 nvidia,enable- 319 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
320 }; 320 };
321 gmi_ad15_ph7 { 321 gmi_ad15_ph7 {
322 nvidia,pins = 322 nvidia,pins = "gmi_ad15_ph7";
323 nvidia,functio 323 nvidia,function = "rsvd1";
324 nvidia,pull = 324 nvidia,pull = <TEGRA_PIN_PULL_UP>;
325 nvidia,tristat 325 nvidia,tristate = <TEGRA_PIN_DISABLE>;
326 nvidia,enable- 326 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
327 }; 327 };
328 gmi_dqs_pi2 { 328 gmi_dqs_pi2 {
329 nvidia,pins = 329 nvidia,pins = "gmi_dqs_pi2",
330 330 "pu2",
331 331 "pv1";
332 nvidia,functio 332 nvidia,function = "rsvd1";
333 nvidia,pull = 333 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334 nvidia,tristat 334 nvidia,tristate = <TEGRA_PIN_DISABLE>;
335 nvidia,enable- 335 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336 }; 336 };
337 gmi_rst_n_pi4 { 337 gmi_rst_n_pi4 {
338 nvidia,pins = 338 nvidia,pins = "gmi_rst_n_pi4";
339 nvidia,functio 339 nvidia,function = "nand";
340 nvidia,pull = 340 nvidia,pull = <TEGRA_PIN_PULL_UP>;
341 nvidia,tristat 341 nvidia,tristate = <TEGRA_PIN_DISABLE>;
342 nvidia,enable- 342 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
343 }; 343 };
344 gmi_iordy_pi5 { 344 gmi_iordy_pi5 {
345 nvidia,pins = 345 nvidia,pins = "gmi_iordy_pi5";
346 nvidia,functio 346 nvidia,function = "rsvd1";
347 nvidia,pull = 347 nvidia,pull = <TEGRA_PIN_PULL_UP>;
348 nvidia,tristat 348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 nvidia,enable- 349 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350 }; 350 };
351 gmi_cs7_n_pi6 { 351 gmi_cs7_n_pi6 {
352 nvidia,pins = 352 nvidia,pins = "gmi_cs7_n_pi6",
353 353 "gmi_clk_pk1";
354 nvidia,functio 354 nvidia,function = "nand";
355 nvidia,pull = 355 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
356 nvidia,tristat 356 nvidia,tristate = <TEGRA_PIN_ENABLE>;
357 nvidia,enable- 357 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
358 }; 358 };
359 gmi_a16_pj7 { 359 gmi_a16_pj7 {
360 nvidia,pins = 360 nvidia,pins = "gmi_a16_pj7",
361 361 "gmi_a19_pk7";
362 nvidia,functio 362 nvidia,function = "uartd";
363 nvidia,pull = 363 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
364 nvidia,tristat 364 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365 nvidia,enable- 365 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
366 }; 366 };
367 spdif_out_pk5 { 367 spdif_out_pk5 {
368 nvidia,pins = 368 nvidia,pins = "spdif_out_pk5";
369 nvidia,functio 369 nvidia,function = "spdif";
370 nvidia,pull = 370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
371 nvidia,tristat 371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable- 372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
373 }; 373 };
374 spdif_in_pk6 { 374 spdif_in_pk6 {
375 nvidia,pins = 375 nvidia,pins = "spdif_in_pk6";
376 nvidia,functio 376 nvidia,function = "spdif";
377 nvidia,pull = 377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378 nvidia,tristat 378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
379 nvidia,enable- 379 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
380 }; 380 };
381 dap1_fs_pn0 { 381 dap1_fs_pn0 {
382 nvidia,pins = 382 nvidia,pins = "dap1_fs_pn0",
383 383 "dap1_din_pn1",
384 384 "dap1_dout_pn2",
385 385 "dap1_sclk_pn3";
386 nvidia,functio 386 nvidia,function = "i2s0";
387 nvidia,pull = 387 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
388 nvidia,tristat 388 nvidia,tristate = <TEGRA_PIN_DISABLE>;
389 nvidia,enable- 389 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
390 }; 390 };
391 hdmi_int_pn7 { 391 hdmi_int_pn7 {
392 nvidia,pins = 392 nvidia,pins = "hdmi_int_pn7";
393 nvidia,functio 393 nvidia,function = "hdmi";
394 nvidia,pull = 394 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
395 nvidia,tristat 395 nvidia,tristate = <TEGRA_PIN_ENABLE>;
396 nvidia,enable- 396 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
397 }; 397 };
398 ulpi_data7_po0 { 398 ulpi_data7_po0 {
399 nvidia,pins = 399 nvidia,pins = "ulpi_data7_po0";
400 nvidia,functio 400 nvidia,function = "uarta";
401 nvidia,pull = 401 nvidia,pull = <TEGRA_PIN_PULL_UP>;
402 nvidia,tristat 402 nvidia,tristate = <TEGRA_PIN_ENABLE>;
403 nvidia,enable- 403 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
404 }; 404 };
405 ulpi_data3_po4 { 405 ulpi_data3_po4 {
406 nvidia,pins = 406 nvidia,pins = "ulpi_data3_po4";
407 nvidia,functio 407 nvidia,function = "ulpi";
408 nvidia,pull = 408 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
409 nvidia,tristat 409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,enable- 410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
411 }; 411 };
412 dap3_fs_pp0 { 412 dap3_fs_pp0 {
413 nvidia,pins = 413 nvidia,pins = "dap3_fs_pp0";
414 nvidia,functio 414 nvidia,function = "i2s2";
415 nvidia,pull = 415 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
416 nvidia,tristat 416 nvidia,tristate = <TEGRA_PIN_DISABLE>;
417 nvidia,enable- 417 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
418 }; 418 };
419 dap4_fs_pp4 { 419 dap4_fs_pp4 {
420 nvidia,pins = 420 nvidia,pins = "dap4_fs_pp4",
421 421 "dap4_din_pp5",
422 422 "dap4_dout_pp6",
423 423 "dap4_sclk_pp7";
424 nvidia,functio 424 nvidia,function = "i2s3";
425 nvidia,pull = 425 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
426 nvidia,tristat 426 nvidia,tristate = <TEGRA_PIN_DISABLE>;
427 nvidia,enable- 427 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
428 }; 428 };
429 kb_col0_pq0 { 429 kb_col0_pq0 {
430 nvidia,pins = 430 nvidia,pins = "kb_col0_pq0",
431 431 "kb_col1_pq1",
432 432 "kb_row1_pr1";
433 nvidia,functio 433 nvidia,function = "kbc";
434 nvidia,pull = 434 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
435 nvidia,tristat 435 nvidia,tristate = <TEGRA_PIN_ENABLE>;
436 nvidia,enable- 436 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
437 }; 437 };
438 kb_col2_pq2 { 438 kb_col2_pq2 {
439 nvidia,pins = 439 nvidia,pins = "kb_col2_pq2",
440 440 "kb_col3_pq3";
441 nvidia,functio 441 nvidia,function = "rsvd4";
442 nvidia,pull = 442 nvidia,pull = <TEGRA_PIN_PULL_UP>;
443 nvidia,tristat 443 nvidia,tristate = <TEGRA_PIN_ENABLE>;
444 nvidia,enable- 444 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445 }; 445 };
446 kb_col4_pq4 { 446 kb_col4_pq4 {
447 nvidia,pins = 447 nvidia,pins = "kb_col4_pq4",
448 448 "kb_col5_pq5",
449 449 "kb_col7_pq7",
450 450 "kb_row2_pr2",
451 451 "kb_row4_pr4",
452 452 "kb_row5_pr5",
453 453 "kb_row14_ps6";
454 nvidia,functio 454 nvidia,function = "kbc";
455 nvidia,pull = 455 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
456 nvidia,tristat 456 nvidia,tristate = <TEGRA_PIN_ENABLE>;
457 nvidia,enable- 457 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
458 }; 458 };
459 kb_row0_pr0 { 459 kb_row0_pr0 {
460 nvidia,pins = 460 nvidia,pins = "kb_row0_pr0";
461 nvidia,functio 461 nvidia,function = "rsvd4";
462 nvidia,pull = 462 nvidia,pull = <TEGRA_PIN_PULL_UP>;
463 nvidia,tristat 463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 nvidia,enable- 464 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
465 }; 465 };
466 kb_row6_pr6 { 466 kb_row6_pr6 {
467 nvidia,pins = 467 nvidia,pins = "kb_row6_pr6",
468 468 "kb_row8_ps0",
469 469 "kb_row9_ps1",
470 470 "kb_row10_ps2";
471 nvidia,functio 471 nvidia,function = "kbc";
472 nvidia,pull = 472 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
473 nvidia,tristat 473 nvidia,tristate = <TEGRA_PIN_DISABLE>;
474 nvidia,enable- 474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
475 }; 475 };
476 kb_row11_ps3 { 476 kb_row11_ps3 {
477 nvidia,pins = 477 nvidia,pins = "kb_row11_ps3",
478 478 "kb_row12_ps4";
479 nvidia,functio 479 nvidia,function = "kbc";
480 nvidia,pull = 480 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
481 nvidia,tristat 481 nvidia,tristate = <TEGRA_PIN_DISABLE>;
482 nvidia,enable- 482 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
483 }; 483 };
484 gen2_i2c_scl_pt5 { 484 gen2_i2c_scl_pt5 {
485 nvidia,pins = 485 nvidia,pins = "gen2_i2c_scl_pt5",
486 486 "gen2_i2c_sda_pt6";
487 nvidia,functio 487 nvidia,function = "i2c2";
488 nvidia,pull = 488 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
489 nvidia,tristat 489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
490 nvidia,enable- 490 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491 nvidia,open-dr 491 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
492 }; 492 };
493 sdmmc4_cmd_pt7 { 493 sdmmc4_cmd_pt7 {
494 nvidia,pins = 494 nvidia,pins = "sdmmc4_cmd_pt7",
495 495 "sdmmc4_dat0_paa0",
496 496 "sdmmc4_dat1_paa1",
497 497 "sdmmc4_dat2_paa2",
498 498 "sdmmc4_dat3_paa3",
499 499 "sdmmc4_dat4_paa4",
500 500 "sdmmc4_dat5_paa5",
501 501 "sdmmc4_dat6_paa6",
502 502 "sdmmc4_dat7_paa7";
503 nvidia,functio 503 nvidia,function = "sdmmc4";
504 nvidia,pull = 504 nvidia,pull = <TEGRA_PIN_PULL_UP>;
505 nvidia,tristat 505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable- 506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 }; 507 };
508 pu0 { 508 pu0 {
509 nvidia,pins = 509 nvidia,pins = "pu0",
510 510 "pu6";
511 nvidia,functio 511 nvidia,function = "rsvd4";
512 nvidia,pull = 512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristat 513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable- 514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 }; 515 };
516 jtag_rtck_pu7 { 516 jtag_rtck_pu7 {
517 nvidia,pins = 517 nvidia,pins = "jtag_rtck_pu7";
518 nvidia,functio 518 nvidia,function = "rtck";
519 nvidia,pull = 519 nvidia,pull = <TEGRA_PIN_PULL_UP>;
520 nvidia,tristat 520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 nvidia,enable- 521 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522 }; 522 };
523 pv0 { 523 pv0 {
524 nvidia,pins = 524 nvidia,pins = "pv0";
525 nvidia,functio 525 nvidia,function = "rsvd1";
526 nvidia,pull = 526 nvidia,pull = <TEGRA_PIN_PULL_UP>;
527 nvidia,tristat 527 nvidia,tristate = <TEGRA_PIN_ENABLE>;
528 nvidia,enable- 528 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
529 }; 529 };
530 ddc_scl_pv4 { 530 ddc_scl_pv4 {
531 nvidia,pins = 531 nvidia,pins = "ddc_scl_pv4",
532 532 "ddc_sda_pv5";
533 nvidia,functio 533 nvidia,function = "i2c4";
534 nvidia,pull = 534 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
535 nvidia,tristat 535 nvidia,tristate = <TEGRA_PIN_DISABLE>;
536 nvidia,enable- 536 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
537 }; 537 };
538 crt_hsync_pv6 { 538 crt_hsync_pv6 {
539 nvidia,pins = 539 nvidia,pins = "crt_hsync_pv6",
540 540 "crt_vsync_pv7";
541 nvidia,functio 541 nvidia,function = "crt";
542 nvidia,pull = 542 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543 nvidia,tristat 543 nvidia,tristate = <TEGRA_PIN_DISABLE>;
544 nvidia,enable- 544 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
545 }; 545 };
546 spi2_cs1_n_pw2 { 546 spi2_cs1_n_pw2 {
547 nvidia,pins = 547 nvidia,pins = "spi2_cs1_n_pw2",
548 548 "spi2_miso_px1",
549 549 "spi2_sck_px2";
550 nvidia,functio 550 nvidia,function = "spi2";
551 nvidia,pull = 551 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
552 nvidia,tristat 552 nvidia,tristate = <TEGRA_PIN_DISABLE>;
553 nvidia,enable- 553 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
554 }; 554 };
555 clk1_out_pw4 { 555 clk1_out_pw4 {
556 nvidia,pins = 556 nvidia,pins = "clk1_out_pw4";
557 nvidia,functio 557 nvidia,function = "extperiph1";
558 nvidia,pull = 558 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
559 nvidia,tristat 559 nvidia,tristate = <TEGRA_PIN_DISABLE>;
560 nvidia,enable- 560 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
561 }; 561 };
562 clk2_out_pw5 { 562 clk2_out_pw5 {
563 nvidia,pins = 563 nvidia,pins = "clk2_out_pw5";
564 nvidia,functio 564 nvidia,function = "extperiph2";
565 nvidia,pull = 565 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
566 nvidia,tristat 566 nvidia,tristate = <TEGRA_PIN_DISABLE>;
567 nvidia,enable- 567 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
568 }; 568 };
569 spi2_cs0_n_px3 { 569 spi2_cs0_n_px3 {
570 nvidia,pins = 570 nvidia,pins = "spi2_cs0_n_px3";
571 nvidia,functio 571 nvidia,function = "spi6";
572 nvidia,pull = 572 nvidia,pull = <TEGRA_PIN_PULL_UP>;
573 nvidia,tristat 573 nvidia,tristate = <TEGRA_PIN_DISABLE>;
574 nvidia,enable- 574 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
575 }; 575 };
576 spi1_mosi_px4 { 576 spi1_mosi_px4 {
577 nvidia,pins = 577 nvidia,pins = "spi1_mosi_px4",
578 578 "spi1_cs0_n_px6";
579 nvidia,functio 579 nvidia,function = "spi1";
580 nvidia,pull = 580 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
581 nvidia,tristat 581 nvidia,tristate = <TEGRA_PIN_DISABLE>;
582 nvidia,enable- 582 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
583 }; 583 };
584 ulpi_clk_py0 { 584 ulpi_clk_py0 {
585 nvidia,pins = 585 nvidia,pins = "ulpi_clk_py0",
586 586 "ulpi_dir_py1";
587 nvidia,functio 587 nvidia,function = "ulpi";
588 nvidia,pull = 588 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
589 nvidia,tristat 589 nvidia,tristate = <TEGRA_PIN_ENABLE>;
590 nvidia,enable- 590 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
591 }; 591 };
592 sdmmc1_dat3_py4 { 592 sdmmc1_dat3_py4 {
593 nvidia,pins = 593 nvidia,pins = "sdmmc1_dat3_py4",
594 594 "sdmmc1_dat2_py5",
595 595 "sdmmc1_dat1_py6",
596 596 "sdmmc1_dat0_py7",
597 597 "sdmmc1_cmd_pz1";
598 nvidia,functio 598 nvidia,function = "sdmmc1";
599 nvidia,pull = 599 nvidia,pull = <TEGRA_PIN_PULL_UP>;
600 nvidia,tristat 600 nvidia,tristate = <TEGRA_PIN_DISABLE>;
601 nvidia,enable- 601 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
602 }; 602 };
603 sdmmc1_clk_pz0 { 603 sdmmc1_clk_pz0 {
604 nvidia,pins = 604 nvidia,pins = "sdmmc1_clk_pz0";
605 nvidia,functio 605 nvidia,function = "sdmmc1";
606 nvidia,pull = 606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
607 nvidia,tristat 607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
608 nvidia,enable- 608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
609 }; 609 };
610 lcd_wr_n_pz3 { 610 lcd_wr_n_pz3 {
611 nvidia,pins = 611 nvidia,pins = "lcd_wr_n_pz3";
612 nvidia,functio 612 nvidia,function = "displaya";
613 nvidia,pull = 613 nvidia,pull = <TEGRA_PIN_PULL_UP>;
614 nvidia,tristat 614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
615 nvidia,enable- 615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
616 }; 616 };
617 sys_clk_req_pz5 { 617 sys_clk_req_pz5 {
618 nvidia,pins = 618 nvidia,pins = "sys_clk_req_pz5";
619 nvidia,functio 619 nvidia,function = "sysclk";
620 nvidia,pull = 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
621 nvidia,tristat 621 nvidia,tristate = <TEGRA_PIN_DISABLE>;
622 nvidia,enable- 622 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
623 }; 623 };
624 pwr_i2c_scl_pz6 { 624 pwr_i2c_scl_pz6 {
625 nvidia,pins = 625 nvidia,pins = "pwr_i2c_scl_pz6",
626 626 "pwr_i2c_sda_pz7";
627 nvidia,functio 627 nvidia,function = "i2cpwr";
628 nvidia,pull = 628 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
629 nvidia,tristat 629 nvidia,tristate = <TEGRA_PIN_DISABLE>;
630 nvidia,enable- 630 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
631 nvidia,open-dr 631 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
632 }; 632 };
633 pbb0 { 633 pbb0 {
634 nvidia,pins = 634 nvidia,pins = "pbb0",
635 635 "pcc1";
636 nvidia,functio 636 nvidia,function = "rsvd2";
637 nvidia,pull = 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristat 638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable- 639 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
640 }; 640 };
641 cam_i2c_scl_pbb1 { 641 cam_i2c_scl_pbb1 {
642 nvidia,pins = 642 nvidia,pins = "cam_i2c_scl_pbb1",
643 643 "cam_i2c_sda_pbb2";
644 nvidia,functio 644 nvidia,function = "i2c3";
645 nvidia,pull = 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
646 nvidia,tristat 646 nvidia,tristate = <TEGRA_PIN_DISABLE>;
647 nvidia,enable- 647 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
648 nvidia,open-dr 648 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
649 }; 649 };
650 pbb3 { 650 pbb3 {
651 nvidia,pins = 651 nvidia,pins = "pbb3";
652 nvidia,functio 652 nvidia,function = "vgp3";
653 nvidia,pull = 653 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
654 nvidia,tristat 654 nvidia,tristate = <TEGRA_PIN_DISABLE>;
655 nvidia,enable- 655 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
656 }; 656 };
657 pbb4 { 657 pbb4 {
658 nvidia,pins = 658 nvidia,pins = "pbb4";
659 nvidia,functio 659 nvidia,function = "vgp4";
660 nvidia,pull = 660 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
661 nvidia,tristat 661 nvidia,tristate = <TEGRA_PIN_DISABLE>;
662 nvidia,enable- 662 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
663 }; 663 };
664 pbb5 { 664 pbb5 {
665 nvidia,pins = 665 nvidia,pins = "pbb5";
666 nvidia,functio 666 nvidia,function = "vgp5";
667 nvidia,pull = 667 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
668 nvidia,tristat 668 nvidia,tristate = <TEGRA_PIN_DISABLE>;
669 nvidia,enable- 669 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
670 }; 670 };
671 pbb6 { 671 pbb6 {
672 nvidia,pins = 672 nvidia,pins = "pbb6";
673 nvidia,functio 673 nvidia,function = "vgp6";
674 nvidia,pull = 674 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
675 nvidia,tristat 675 nvidia,tristate = <TEGRA_PIN_DISABLE>;
676 nvidia,enable- 676 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
677 }; 677 };
678 pbb7 { 678 pbb7 {
679 nvidia,pins = 679 nvidia,pins = "pbb7",
680 680 "pcc2";
681 nvidia,functio 681 nvidia,function = "i2s4";
682 nvidia,pull = 682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683 nvidia,tristat 683 nvidia,tristate = <TEGRA_PIN_DISABLE>;
684 nvidia,enable- 684 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
685 }; 685 };
686 cam_mclk_pcc0 { 686 cam_mclk_pcc0 {
687 nvidia,pins = 687 nvidia,pins = "cam_mclk_pcc0";
688 nvidia,functio 688 nvidia,function = "vi_alt3";
689 nvidia,pull = 689 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
690 nvidia,tristat 690 nvidia,tristate = <TEGRA_PIN_DISABLE>;
691 nvidia,enable- 691 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
692 }; 692 };
693 sdmmc4_rst_n_pcc3 { 693 sdmmc4_rst_n_pcc3 {
694 nvidia,pins = 694 nvidia,pins = "sdmmc4_rst_n_pcc3";
695 nvidia,functio 695 nvidia,function = "rsvd2";
696 nvidia,pull = 696 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
697 nvidia,tristat 697 nvidia,tristate = <TEGRA_PIN_DISABLE>;
698 nvidia,enable- 698 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
699 }; 699 };
700 sdmmc4_clk_pcc4 { 700 sdmmc4_clk_pcc4 {
701 nvidia,pins = 701 nvidia,pins = "sdmmc4_clk_pcc4";
702 nvidia,functio 702 nvidia,function = "sdmmc4";
703 nvidia,pull = 703 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
704 nvidia,tristat 704 nvidia,tristate = <TEGRA_PIN_DISABLE>;
705 nvidia,enable- 705 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
706 }; 706 };
707 clk2_req_pcc5 { 707 clk2_req_pcc5 {
708 nvidia,pins = 708 nvidia,pins = "clk2_req_pcc5";
709 nvidia,functio 709 nvidia,function = "dap";
710 nvidia,pull = 710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristat 711 nvidia,tristate = <TEGRA_PIN_DISABLE>;
712 nvidia,enable- 712 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713 }; 713 };
714 pex_l2_rst_n_pcc6 { 714 pex_l2_rst_n_pcc6 {
715 nvidia,pins = 715 nvidia,pins = "pex_l2_rst_n_pcc6",
716 716 "pex_l2_clkreq_n_pcc7";
717 nvidia,functio 717 nvidia,function = "pcie";
718 nvidia,pull = 718 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
719 nvidia,tristat 719 nvidia,tristate = <TEGRA_PIN_DISABLE>;
720 nvidia,enable- 720 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
721 }; 721 };
722 pex_wake_n_pdd3 { 722 pex_wake_n_pdd3 {
723 nvidia,pins = 723 nvidia,pins = "pex_wake_n_pdd3",
724 724 "pex_l2_prsnt_n_pdd7";
725 nvidia,functio 725 nvidia,function = "pcie";
726 nvidia,pull = 726 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
727 nvidia,tristat 727 nvidia,tristate = <TEGRA_PIN_DISABLE>;
728 nvidia,enable- 728 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
729 }; 729 };
730 clk3_out_pee0 { 730 clk3_out_pee0 {
731 nvidia,pins = 731 nvidia,pins = "clk3_out_pee0";
732 nvidia,functio 732 nvidia,function = "extperiph3";
733 nvidia,pull = 733 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
734 nvidia,tristat 734 nvidia,tristate = <TEGRA_PIN_DISABLE>;
735 nvidia,enable- 735 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
736 }; 736 };
737 clk1_req_pee2 { 737 clk1_req_pee2 {
738 nvidia,pins = 738 nvidia,pins = "clk1_req_pee2";
739 nvidia,functio 739 nvidia,function = "dap";
740 nvidia,pull = 740 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
741 nvidia,tristat 741 nvidia,tristate = <TEGRA_PIN_ENABLE>;
742 nvidia,enable- 742 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
743 }; 743 };
744 hdmi_cec_pee3 { 744 hdmi_cec_pee3 {
745 nvidia,pins = 745 nvidia,pins = "hdmi_cec_pee3";
746 nvidia,functio 746 nvidia,function = "cec";
747 nvidia,pull = 747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748 nvidia,tristat 748 nvidia,tristate = <TEGRA_PIN_DISABLE>;
749 nvidia,enable- 749 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
750 nvidia,open-dr 750 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
751 }; 751 };
752 owr { 752 owr {
753 nvidia,pins = 753 nvidia,pins = "owr";
754 nvidia,functio 754 nvidia,function = "owr";
755 nvidia,pull = 755 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756 nvidia,tristat 756 nvidia,tristate = <TEGRA_PIN_DISABLE>;
757 nvidia,enable- 757 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
758 }; 758 };
759 drive_dap1 { 759 drive_dap1 {
760 nvidia,pins = 760 nvidia,pins = "drive_dap1",
761 761 "drive_dap2",
762 762 "drive_dbg",
763 763 "drive_at5",
764 764 "drive_gme",
765 765 "drive_ddc",
766 766 "drive_ao1",
767 767 "drive_uart3";
768 nvidia,high-sp 768 nvidia,high-speed-mode = <0>;
769 nvidia,schmitt 769 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
770 nvidia,low-pow 770 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
771 nvidia,pull-do 771 nvidia,pull-down-strength = <31>;
772 nvidia,pull-up 772 nvidia,pull-up-strength = <31>;
773 nvidia,slew-ra 773 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
774 nvidia,slew-ra 774 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
775 }; 775 };
776 drive_sdio1 { 776 drive_sdio1 {
777 nvidia,pins = 777 nvidia,pins = "drive_sdio1",
778 778 "drive_sdio3";
779 nvidia,high-sp 779 nvidia,high-speed-mode = <0>;
780 nvidia,schmitt 780 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
781 nvidia,pull-do 781 nvidia,pull-down-strength = <46>;
782 nvidia,pull-up 782 nvidia,pull-up-strength = <42>;
783 nvidia,slew-ra 783 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
784 nvidia,slew-ra 784 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
785 }; 785 };
786 drive_gma { 786 drive_gma {
787 nvidia,pins = 787 nvidia,pins = "drive_gma",
788 788 "drive_gmb",
789 789 "drive_gmc",
790 790 "drive_gmd";
791 nvidia,pull-do 791 nvidia,pull-down-strength = <9>;
792 nvidia,pull-up 792 nvidia,pull-up-strength = <9>;
793 nvidia,slew-ra 793 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
794 nvidia,slew-ra 794 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
795 }; 795 };
796 }; 796 };
797 }; 797 };
798 798
799 uartb: serial@70006040 { 799 uartb: serial@70006040 {
800 compatible = "nvidia,tegra30-h 800 compatible = "nvidia,tegra30-hsuart";
801 reset-names = "serial"; 801 reset-names = "serial";
802 /delete-property/ reg-shift; 802 /delete-property/ reg-shift;
803 /* GPS BCM4751 */ 803 /* GPS BCM4751 */
804 }; 804 };
805 805
806 uartc: serial@70006200 { 806 uartc: serial@70006200 {
807 compatible = "nvidia,tegra30-h 807 compatible = "nvidia,tegra30-hsuart";
808 reset-names = "serial"; 808 reset-names = "serial";
809 /delete-property/ reg-shift; 809 /delete-property/ reg-shift;
810 status = "okay"; 810 status = "okay";
811 811
812 nvidia,adjust-baud-rates = <0 812 nvidia,adjust-baud-rates = <0 9600 100>,
813 <96 813 <9600 115200 200>,
814 <10 814 <1000000 4000000 136>;
815 815
816 /* Azurewave AW-NH665 BCM4330B 816 /* Azurewave AW-NH665 BCM4330B1 */
817 bluetooth { 817 bluetooth {
818 compatible = "brcm,bcm 818 compatible = "brcm,bcm4330-bt";
819 819
820 interrupt-parent = <&g 820 interrupt-parent = <&gpio>;
821 interrupts = <TEGRA_GP 821 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
822 interrupt-names = "hos 822 interrupt-names = "host-wakeup";
823 823
824 max-speed = <4000000>; 824 max-speed = <4000000>;
825 825
826 clocks = <&tegra_pmc T 826 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
827 clock-names = "txco"; 827 clock-names = "txco";
828 828
829 vbat-supply = <&vdd_3 829 vbat-supply = <&vdd_3v3_sys>;
830 vddio-supply = <&vdd_1 830 vddio-supply = <&vdd_1v8>;
831 831
832 device-wakeup-gpios = 832 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
833 shutdown-gpios = <&gpi 833 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
834 }; 834 };
835 }; 835 };
836 836
837 pwm: pwm@7000a000 { 837 pwm: pwm@7000a000 {
838 status = "okay"; 838 status = "okay";
839 }; 839 };
840 840
841 i2c@7000c400 { 841 i2c@7000c400 {
842 clock-frequency = <400000>; 842 clock-frequency = <400000>;
843 status = "okay"; 843 status = "okay";
844 844
845 touchscreen@10 { 845 touchscreen@10 {
846 compatible = "elan,ekt 846 compatible = "elan,ektf3624";
847 reg = <0x10>; 847 reg = <0x10>;
848 848
849 interrupt-parent = <&g 849 interrupt-parent = <&gpio>;
850 interrupts = <TEGRA_GP 850 interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>;
851 851
852 reset-gpios = <&gpio T 852 reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
853 853
854 vcc33-supply = <&vcc_3 854 vcc33-supply = <&vcc_3v3_ts>;
855 vccio-supply = <&vcc_3 855 vccio-supply = <&vcc_3v3_ts>;
856 856
857 touchscreen-size-x = < 857 touchscreen-size-x = <2112>;
858 touchscreen-size-y = < 858 touchscreen-size-y = <1280>;
859 touchscreen-swapped-x- 859 touchscreen-swapped-x-y;
860 touchscreen-inverted-x 860 touchscreen-inverted-x;
861 }; 861 };
862 }; 862 };
863 863
864 i2c@7000c500 { 864 i2c@7000c500 {
865 clock-frequency = <100000>; 865 clock-frequency = <100000>;
866 status = "okay"; 866 status = "okay";
867 867
868 compass@e { 868 compass@e {
869 compatible = "asahi-ka 869 compatible = "asahi-kasei,ak8974";
870 reg = <0x0e>; 870 reg = <0x0e>;
871 871
872 interrupt-parent = <&g 872 interrupt-parent = <&gpio>;
873 interrupts = <TEGRA_GP 873 interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>;
874 874
875 avdd-supply = <&vdd_3v 875 avdd-supply = <&vdd_3v3_sys>;
876 dvdd-supply = <&vdd_1v 876 dvdd-supply = <&vdd_1v8>;
877 877
878 mount-matrix = "0", 878 mount-matrix = "0", "-1", "0",
879 "-1", 879 "-1", "0", "0",
880 "0", 880 "0", "0", "-1";
881 }; 881 };
882 882
883 light-sensor@1c { 883 light-sensor@1c {
884 compatible = "dynaimag 884 compatible = "dynaimage,al3010";
885 reg = <0x1c>; 885 reg = <0x1c>;
886 886
887 interrupt-parent = <&g 887 interrupt-parent = <&gpio>;
888 interrupts = <TEGRA_GP 888 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
889 889
890 vdd-supply = <&vdd_3v3 890 vdd-supply = <&vdd_3v3_sys>;
891 }; 891 };
892 892
893 accelerometer@68 { 893 accelerometer@68 {
894 compatible = "invensen 894 compatible = "invensense,mpu6050";
895 reg = <0x68>; 895 reg = <0x68>;
896 896
897 interrupt-parent = <&g 897 interrupt-parent = <&gpio>;
898 interrupts = <TEGRA_GP 898 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
899 899
900 vdd-supply = <&vdd_3 900 vdd-supply = <&vdd_3v3_sys>;
901 vddio-supply = <&vdd_1 901 vddio-supply = <&vdd_1v8>;
902 902
903 mount-matrix = "0", 903 mount-matrix = "0", "-1", "0",
904 "-1", 904 "-1", "0", "0",
905 "0", 905 "0", "0", "-1";
906 }; 906 };
907 }; 907 };
908 908
909 i2c@7000d000 { 909 i2c@7000d000 {
910 clock-frequency = <100000>; 910 clock-frequency = <100000>;
911 status = "okay"; 911 status = "okay";
912 912
913 rt5640: audio-codec@1c { 913 rt5640: audio-codec@1c {
914 compatible = "realtek, 914 compatible = "realtek,rt5640";
915 reg = <0x1c>; 915 reg = <0x1c>;
916 916
917 realtek,dmic1-data-pin 917 realtek,dmic1-data-pin = <1>;
918 <<
919 clocks = <&tegra_pmc T <<
920 clock-names = "mclk"; <<
921 }; 918 };
922 919
923 nct72: temperature-sensor@4c { 920 nct72: temperature-sensor@4c {
924 compatible = "onnn,nct 921 compatible = "onnn,nct1008";
925 reg = <0x4c>; 922 reg = <0x4c>;
926 vcc-supply = <&vdd_3v3 923 vcc-supply = <&vdd_3v3_sys>;
927 924
928 interrupt-parent = <&g 925 interrupt-parent = <&gpio>;
929 interrupts = <TEGRA_GP 926 interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>;
930 927
931 #thermal-sensor-cells 928 #thermal-sensor-cells = <1>;
932 }; 929 };
933 930
934 fuel-gauge@55 { 931 fuel-gauge@55 {
935 compatible = "ti,bq275 932 compatible = "ti,bq27541";
936 reg = <0x55>; 933 reg = <0x55>;
937 power-supplies = <&pow 934 power-supplies = <&power_supply>;
938 }; 935 };
939 936
940 power_supply: charger@6a { 937 power_supply: charger@6a {
941 compatible = "summit,s 938 compatible = "summit,smb347";
942 reg = <0x6a>; 939 reg = <0x6a>;
943 940
944 interrupt-parent = <&g 941 interrupt-parent = <&gpio>;
945 interrupts = <TEGRA_GP 942 interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;
946 943
947 summit,enable-charge-c 944 summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
948 summit,inok-polarity = 945 summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
949 summit,enable-usb-char 946 summit,enable-usb-charging;
950 947
951 monitored-battery = <& 948 monitored-battery = <&battery_cell>;
952 949
953 usb_vbus: usb-vbus { 950 usb_vbus: usb-vbus {
954 regulator-name 951 regulator-name = "usb_vbus";
955 regulator-min- 952 regulator-min-microvolt = <5000000>;
956 regulator-max- 953 regulator-max-microvolt = <5000000>;
957 regulator-min- 954 regulator-min-microamp = <750000>;
958 regulator-max- 955 regulator-max-microamp = <750000>;
959 956
960 /* 957 /*
961 * SMB347 INOK 958 * SMB347 INOK input pin is connected to PMIC's
962 * ACOK output 959 * ACOK output, which is fixed to ACTIVE_LOW as
963 * long as bat 960 * long as battery voltage is in a good range.
964 * 961 *
965 * Active INOK 962 * Active INOK disables SMB347 output, so polarity
966 * needs to be 963 * needs to be toggled when we want to get the
967 * output. 964 * output.
968 */ 965 */
969 summit,needs-i 966 summit,needs-inok-toggle;
970 }; 967 };
971 }; 968 };
972 }; 969 };
973 970
974 pmc@7000e400 { 971 pmc@7000e400 {
975 status = "okay"; 972 status = "okay";
976 nvidia,invert-interrupt; 973 nvidia,invert-interrupt;
977 nvidia,suspend-mode = <1>; 974 nvidia,suspend-mode = <1>;
978 nvidia,cpu-pwr-good-time = <20 975 nvidia,cpu-pwr-good-time = <2000>;
979 nvidia,cpu-pwr-off-time = <200 976 nvidia,cpu-pwr-off-time = <200>;
980 nvidia,core-pwr-good-time = <3 977 nvidia,core-pwr-good-time = <3845 3845>;
981 nvidia,core-pwr-off-time = <0> 978 nvidia,core-pwr-off-time = <0>;
982 nvidia,core-power-req-active-h 979 nvidia,core-power-req-active-high;
983 nvidia,sys-clock-req-active-hi 980 nvidia,sys-clock-req-active-high;
984 core-supply = <&vdd_core>; 981 core-supply = <&vdd_core>;
985 }; 982 };
986 983
987 ahub@70080000 { 984 ahub@70080000 {
988 i2s@70080400 { 985 i2s@70080400 {
989 status = "okay"; 986 status = "okay";
990 }; 987 };
991 }; 988 };
992 989
993 sdmmc3: mmc@78000400 { 990 sdmmc3: mmc@78000400 {
994 status = "okay"; 991 status = "okay";
995 992
996 #address-cells = <1>; 993 #address-cells = <1>;
997 #size-cells = <0>; 994 #size-cells = <0>;
998 995
999 assigned-clocks = <&tegra_car 996 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1000 assigned-clock-parents = <&te 997 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1001 assigned-clock-rates = <50000 998 assigned-clock-rates = <50000000>;
1002 999
1003 max-frequency = <50000000>; 1000 max-frequency = <50000000>;
1004 keep-power-in-suspend; 1001 keep-power-in-suspend;
1005 bus-width = <4>; 1002 bus-width = <4>;
1006 non-removable; 1003 non-removable;
1007 1004
1008 mmc-pwrseq = <&brcm_wifi_pwrs 1005 mmc-pwrseq = <&brcm_wifi_pwrseq>;
1009 vmmc-supply = <&vdd_3v3_sys>; 1006 vmmc-supply = <&vdd_3v3_sys>;
1010 vqmmc-supply = <&vdd_1v8>; 1007 vqmmc-supply = <&vdd_1v8>;
1011 1008
1012 /* Azurewave AW-NH665 BCM4330 1009 /* Azurewave AW-NH665 BCM4330 */
1013 wifi@1 { 1010 wifi@1 {
1014 reg = <1>; 1011 reg = <1>;
1015 compatible = "brcm,bc 1012 compatible = "brcm,bcm4329-fmac";
1016 interrupt-parent = <& 1013 interrupt-parent = <&gpio>;
1017 interrupts = <TEGRA_G 1014 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1018 interrupt-names = "ho 1015 interrupt-names = "host-wake";
1019 }; 1016 };
1020 }; 1017 };
1021 1018
1022 sdmmc4: mmc@78000600 { 1019 sdmmc4: mmc@78000600 {
1023 status = "okay"; 1020 status = "okay";
1024 bus-width = <8>; 1021 bus-width = <8>;
1025 vmmc-supply = <&vcore_emmc>; 1022 vmmc-supply = <&vcore_emmc>;
1026 vqmmc-supply = <&vdd_1v8>; 1023 vqmmc-supply = <&vdd_1v8>;
1027 non-removable; 1024 non-removable;
1028 }; 1025 };
1029 1026
1030 usb@7d000000 { 1027 usb@7d000000 {
1031 compatible = "nvidia,tegra30- 1028 compatible = "nvidia,tegra30-udc";
1032 status = "okay"; 1029 status = "okay";
1033 dr_mode = "otg"; 1030 dr_mode = "otg";
1034 vbus-supply = <&usb_vbus>; 1031 vbus-supply = <&usb_vbus>;
1035 }; 1032 };
1036 1033
1037 usb-phy@7d000000 { 1034 usb-phy@7d000000 {
1038 status = "okay"; 1035 status = "okay";
1039 dr_mode = "otg"; 1036 dr_mode = "otg";
1040 nvidia,hssync-start-delay = < 1037 nvidia,hssync-start-delay = <0>;
1041 nvidia,xcvr-lsfslew = <2>; 1038 nvidia,xcvr-lsfslew = <2>;
1042 nvidia,xcvr-lsrslew = <2>; 1039 nvidia,xcvr-lsrslew = <2>;
1043 }; 1040 };
1044 1041
1045 backlight: backlight { 1042 backlight: backlight {
1046 compatible = "pwm-backlight"; 1043 compatible = "pwm-backlight";
1047 1044
1048 power-supply = <&vdd_5v0_sys> 1045 power-supply = <&vdd_5v0_sys>;
1049 pwms = <&pwm 0 50000>; 1046 pwms = <&pwm 0 50000>;
1050 1047
1051 brightness-levels = <1 255>; 1048 brightness-levels = <1 255>;
1052 num-interpolated-steps = <254 1049 num-interpolated-steps = <254>;
1053 default-brightness-level = <1 1050 default-brightness-level = <15>;
1054 }; 1051 };
1055 1052
1056 battery_cell: battery-cell { 1053 battery_cell: battery-cell {
1057 compatible = "simple-battery" 1054 compatible = "simple-battery";
1058 constant-charge-current-max-m 1055 constant-charge-current-max-microamp = <1800000>;
1059 operating-range-celsius = <0 1056 operating-range-celsius = <0 45>;
1060 }; 1057 };
1061 1058
1062 /* PMIC has a built-in 32KHz oscillat 1059 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
1063 clk32k_in: clock-32k { 1060 clk32k_in: clock-32k {
1064 compatible = "fixed-clock"; 1061 compatible = "fixed-clock";
1065 #clock-cells = <0>; 1062 #clock-cells = <0>;
1066 clock-frequency = <32768>; 1063 clock-frequency = <32768>;
1067 clock-output-names = "pmic-os 1064 clock-output-names = "pmic-oscillator";
1068 }; 1065 };
1069 1066
1070 cpus { 1067 cpus {
1071 cpu0: cpu@0 { 1068 cpu0: cpu@0 {
1072 cpu-supply = <&vdd_cp 1069 cpu-supply = <&vdd_cpu>;
1073 operating-points-v2 = 1070 operating-points-v2 = <&cpu0_opp_table>;
1074 #cooling-cells = <2>; 1071 #cooling-cells = <2>;
1075 }; 1072 };
1076 1073
1077 cpu1: cpu@1 { 1074 cpu1: cpu@1 {
1078 cpu-supply = <&vdd_cp 1075 cpu-supply = <&vdd_cpu>;
1079 operating-points-v2 = 1076 operating-points-v2 = <&cpu0_opp_table>;
1080 #cooling-cells = <2>; 1077 #cooling-cells = <2>;
1081 }; 1078 };
1082 1079
1083 cpu2: cpu@2 { 1080 cpu2: cpu@2 {
1084 cpu-supply = <&vdd_cp 1081 cpu-supply = <&vdd_cpu>;
1085 operating-points-v2 = 1082 operating-points-v2 = <&cpu0_opp_table>;
1086 #cooling-cells = <2>; 1083 #cooling-cells = <2>;
1087 }; 1084 };
1088 1085
1089 cpu3: cpu@3 { 1086 cpu3: cpu@3 {
1090 cpu-supply = <&vdd_cp 1087 cpu-supply = <&vdd_cpu>;
1091 operating-points-v2 = 1088 operating-points-v2 = <&cpu0_opp_table>;
1092 #cooling-cells = <2>; 1089 #cooling-cells = <2>;
1093 }; 1090 };
1094 }; 1091 };
1095 1092
1096 display-panel { 1093 display-panel {
1097 /* 1094 /*
1098 * Some device variants come 1095 * Some device variants come with a Hydis HV070WX2-1E0, but
1099 * since they are all largely 1096 * since they are all largely compatible, we'll go with the
1100 * Chunghwa one here. 1097 * Chunghwa one here.
1101 */ 1098 */
1102 compatible = "chunghwa,claa07 1099 compatible = "chunghwa,claa070wp03xg", "panel-lvds";
1103 1100
1104 width-mm = <94>; 1101 width-mm = <94>;
1105 height-mm = <150>; 1102 height-mm = <150>;
1106 rotation = <180>; 1103 rotation = <180>;
1107 1104
1108 data-mapping = "jeida-24"; 1105 data-mapping = "jeida-24";
1109 1106
1110 /* DDC unconnected on Nexus 7 1107 /* DDC unconnected on Nexus 7 */
1111 /delete-property/ ddc-i2c-bus 1108 /delete-property/ ddc-i2c-bus;
1112 }; 1109 };
1113 1110
1114 gpio-keys { 1111 gpio-keys {
1115 compatible = "gpio-keys"; 1112 compatible = "gpio-keys";
1116 1113
1117 key-power { 1114 key-power {
1118 label = "Power"; 1115 label = "Power";
1119 gpios = <&gpio TEGRA_ 1116 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1120 linux,code = <KEY_POW 1117 linux,code = <KEY_POWER>;
1121 debounce-interval = < 1118 debounce-interval = <10>;
1122 wakeup-event-action = 1119 wakeup-event-action = <EV_ACT_ASSERTED>;
1123 wakeup-source; 1120 wakeup-source;
1124 }; 1121 };
1125 1122
1126 key-volume-down { 1123 key-volume-down {
1127 label = "Volume Down" 1124 label = "Volume Down";
1128 gpios = <&gpio TEGRA_ 1125 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1129 linux,code = <KEY_VOL 1126 linux,code = <KEY_VOLUMEDOWN>;
1130 debounce-interval = < 1127 debounce-interval = <10>;
1131 wakeup-event-action = 1128 wakeup-event-action = <EV_ACT_ASSERTED>;
1132 wakeup-source; 1129 wakeup-source;
1133 }; 1130 };
1134 1131
1135 key-volume-up { 1132 key-volume-up {
1136 label = "Volume Up"; 1133 label = "Volume Up";
1137 gpios = <&gpio TEGRA_ 1134 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1138 linux,code = <KEY_VOL 1135 linux,code = <KEY_VOLUMEUP>;
1139 debounce-interval = < 1136 debounce-interval = <10>;
1140 wakeup-event-action = 1137 wakeup-event-action = <EV_ACT_ASSERTED>;
1141 wakeup-source; 1138 wakeup-source;
1142 }; 1139 };
1143 1140
1144 switch-hall-sensor { 1141 switch-hall-sensor {
1145 label = "Lid"; 1142 label = "Lid";
1146 gpios = <&gpio TEGRA_ 1143 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1147 linux,input-type = <E 1144 linux,input-type = <EV_SW>;
1148 linux,code = <SW_LID> 1145 linux,code = <SW_LID>;
1149 debounce-interval = < 1146 debounce-interval = <500>;
1150 wakeup-event-action = 1147 wakeup-event-action = <EV_ACT_DEASSERTED>;
1151 wakeup-source; 1148 wakeup-source;
1152 }; 1149 };
1153 }; 1150 };
1154 1151
1155 brcm_wifi_pwrseq: pwrseq-wifi { 1152 brcm_wifi_pwrseq: pwrseq-wifi {
1156 compatible = "mmc-pwrseq-simp 1153 compatible = "mmc-pwrseq-simple";
1157 1154
1158 clocks = <&tegra_pmc TEGRA_PM 1155 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1159 clock-names = "ext_clock"; 1156 clock-names = "ext_clock";
1160 1157
1161 reset-gpios = <&gpio TEGRA_GP 1158 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1162 post-power-on-delay-ms = <300 1159 post-power-on-delay-ms = <300>;
1163 power-off-delay-us = <300>; 1160 power-off-delay-us = <300>;
1164 }; 1161 };
1165 1162
1166 vdd_5v0_sys: regulator-5v0 { 1163 vdd_5v0_sys: regulator-5v0 {
1167 compatible = "regulator-fixed 1164 compatible = "regulator-fixed";
1168 regulator-name = "vdd_5v0"; 1165 regulator-name = "vdd_5v0";
1169 regulator-min-microvolt = <50 1166 regulator-min-microvolt = <5000000>;
1170 regulator-max-microvolt = <50 1167 regulator-max-microvolt = <5000000>;
1171 regulator-always-on; 1168 regulator-always-on;
1172 regulator-boot-on; 1169 regulator-boot-on;
1173 }; 1170 };
1174 1171
1175 vdd_3v3_sys: regulator-3v3 { 1172 vdd_3v3_sys: regulator-3v3 {
1176 compatible = "regulator-fixed 1173 compatible = "regulator-fixed";
1177 regulator-name = "vdd_3v3"; 1174 regulator-name = "vdd_3v3";
1178 regulator-min-microvolt = <33 1175 regulator-min-microvolt = <3300000>;
1179 regulator-max-microvolt = <33 1176 regulator-max-microvolt = <3300000>;
1180 regulator-always-on; 1177 regulator-always-on;
1181 regulator-boot-on; 1178 regulator-boot-on;
1182 vin-supply = <&vdd_5v0_sys>; 1179 vin-supply = <&vdd_5v0_sys>;
1183 }; 1180 };
1184 1181
1185 vdd_pnl: regulator-panel { 1182 vdd_pnl: regulator-panel {
1186 compatible = "regulator-fixed 1183 compatible = "regulator-fixed";
1187 regulator-name = "vdd_panel"; 1184 regulator-name = "vdd_panel";
1188 regulator-min-microvolt = <33 1185 regulator-min-microvolt = <3300000>;
1189 regulator-max-microvolt = <33 1186 regulator-max-microvolt = <3300000>;
1190 regulator-enable-ramp-delay = 1187 regulator-enable-ramp-delay = <300000>;
1191 gpio = <&gpio TEGRA_GPIO(W, 1 1188 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1192 enable-active-high; 1189 enable-active-high;
1193 vin-supply = <&vdd_3v3_sys>; 1190 vin-supply = <&vdd_3v3_sys>;
1194 }; 1191 };
1195 1192
1196 vcc_3v3_ts: regulator-ts { 1193 vcc_3v3_ts: regulator-ts {
1197 compatible = "regulator-fixed 1194 compatible = "regulator-fixed";
1198 regulator-name = "ldo_s-1167_ 1195 regulator-name = "ldo_s-1167_3v3";
1199 regulator-min-microvolt = <33 1196 regulator-min-microvolt = <3300000>;
1200 regulator-max-microvolt = <33 1197 regulator-max-microvolt = <3300000>;
1201 regulator-always-on; 1198 regulator-always-on;
1202 regulator-boot-on; 1199 regulator-boot-on;
1203 vin-supply = <&vdd_5v0_sys>; 1200 vin-supply = <&vdd_5v0_sys>;
1204 }; 1201 };
1205 1202
1206 sound { 1203 sound {
1207 compatible = "nvidia,tegra-au 1204 compatible = "nvidia,tegra-audio-rt5640-grouper",
1208 "nvidia,tegra-au 1205 "nvidia,tegra-audio-rt5640";
1209 nvidia,model = "ASUS Google N 1206 nvidia,model = "ASUS Google Nexus 7 ALC5642";
1210 1207
1211 nvidia,audio-routing = 1208 nvidia,audio-routing =
1212 "Headphones", "HPOR", 1209 "Headphones", "HPOR",
1213 "Headphones", "HPOL", 1210 "Headphones", "HPOL",
1214 "Speakers", "SPORP", 1211 "Speakers", "SPORP",
1215 "Speakers", "SPORN", 1212 "Speakers", "SPORN",
1216 "Speakers", "SPOLP", 1213 "Speakers", "SPOLP",
1217 "Speakers", "SPOLN", 1214 "Speakers", "SPOLN",
1218 "DMIC1", "Mic Jack"; 1215 "DMIC1", "Mic Jack";
1219 1216
1220 nvidia,i2s-controller = <&teg 1217 nvidia,i2s-controller = <&tegra_i2s1>;
1221 nvidia,audio-codec = <&rt5640 1218 nvidia,audio-codec = <&rt5640>;
1222 1219
1223 nvidia,hp-det-gpios = <&gpio 1220 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1224 1221
1225 clocks = <&tegra_car TEGRA30_ 1222 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1226 <&tegra_car TEGRA30_ 1223 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1227 <&tegra_pmc TEGRA_PM 1224 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1228 clock-names = "pll_a", "pll_a 1225 clock-names = "pll_a", "pll_a_out0", "mclk";
1229 1226
1230 assigned-clocks = <&tegra_car 1227 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1231 <&tegra_pmc 1228 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1232 1229
1233 assigned-clock-parents = <&te 1230 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1234 <&te 1231 <&tegra_car TEGRA30_CLK_EXTERN1>;
1235 }; 1232 };
1236 1233
1237 thermal-zones { 1234 thermal-zones {
1238 /* 1235 /*
1239 * NCT72 has two sensors: 1236 * NCT72 has two sensors:
1240 * 1237 *
1241 * 0: internal that moni 1238 * 0: internal that monitors ambient/skin temperature
1242 * 1: external that is c 1239 * 1: external that is connected to the CPU's diode
1243 * 1240 *
1244 * Ideally we should use user 1241 * Ideally we should use userspace thermal governor,
1245 * but it's a much more compl 1242 * but it's a much more complex solution. The "skin"
1246 * zone is a simpler solution 1243 * zone is a simpler solution which prevents Nexus 7
1247 * from getting too hot from 1244 * from getting too hot from a user's tactile perspective.
1248 * The CPU zone is intended t 1245 * The CPU zone is intended to protect silicon from damage.
1249 */ 1246 */
1250 1247
1251 skin-thermal { 1248 skin-thermal {
1252 polling-delay-passive 1249 polling-delay-passive = <1000>; /* milliseconds */
1253 polling-delay = <5000 1250 polling-delay = <5000>; /* milliseconds */
1254 1251
1255 thermal-sensors = <&n 1252 thermal-sensors = <&nct72 0>;
1256 1253
1257 trips { 1254 trips {
1258 trip0: skin-a 1255 trip0: skin-alert {
1259 /* th 1256 /* throttle at 57C until temperature drops to 56.8C */
1260 tempe 1257 temperature = <57000>;
1261 hyste 1258 hysteresis = <200>;
1262 type 1259 type = "passive";
1263 }; 1260 };
1264 1261
1265 trip1: skin-c 1262 trip1: skin-crit {
1266 /* sh 1263 /* shut down at 65C */
1267 tempe 1264 temperature = <65000>;
1268 hyste 1265 hysteresis = <2000>;
1269 type 1266 type = "critical";
1270 }; 1267 };
1271 }; 1268 };
1272 1269
1273 cooling-maps { 1270 cooling-maps {
1274 map0 { 1271 map0 {
1275 trip 1272 trip = <&trip0>;
1276 cooli 1273 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1277 1274 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1278 1275 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1279 1276 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1280 1277 <&actmon THERMAL_NO_LIMIT
1281 1278 THERMAL_NO_LIMIT>;
1282 }; 1279 };
1283 }; 1280 };
1284 }; 1281 };
1285 1282
1286 cpu-thermal { 1283 cpu-thermal {
1287 polling-delay-passive 1284 polling-delay-passive = <1000>; /* milliseconds */
1288 polling-delay = <5000 1285 polling-delay = <5000>; /* milliseconds */
1289 1286
1290 thermal-sensors = <&n 1287 thermal-sensors = <&nct72 1>;
1291 1288
1292 trips { 1289 trips {
1293 trip2: cpu-al 1290 trip2: cpu-alert {
1294 /* th 1291 /* throttle at 85C until temperature drops to 84.8C */
1295 tempe 1292 temperature = <85000>;
1296 hyste 1293 hysteresis = <200>;
1297 type 1294 type = "passive";
1298 }; 1295 };
1299 1296
1300 trip3: cpu-cr 1297 trip3: cpu-crit {
1301 /* sh 1298 /* shut down at 90C */
1302 tempe 1299 temperature = <90000>;
1303 hyste 1300 hysteresis = <2000>;
1304 type 1301 type = "critical";
1305 }; 1302 };
1306 }; 1303 };
1307 1304
1308 cooling-maps { 1305 cooling-maps {
1309 map1 { 1306 map1 {
1310 trip 1307 trip = <&trip2>;
1311 cooli 1308 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1312 1309 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1313 1310 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1314 1311 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1315 1312 <&actmon THERMAL_NO_LIMIT
1316 1313 THERMAL_NO_LIMIT>;
1317 }; 1314 };
1318 }; 1315 };
1319 }; 1316 };
1320 }; 1317 };
1321 }; 1318 };
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