1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 2
3 #include <dt-bindings/input/gpio-keys.h> 3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h> 5 #include <dt-bindings/thermal/thermal.h>
6 6
7 #include "tegra30.dtsi" 7 #include "tegra30.dtsi"
8 #include "tegra30-cpu-opp.dtsi" 8 #include "tegra30-cpu-opp.dtsi"
9 #include "tegra30-cpu-opp-microvolt.dtsi" 9 #include "tegra30-cpu-opp-microvolt.dtsi"
10 10
11 / { 11 / {
12 chassis-type = "convertible"; 12 chassis-type = "convertible";
13 13
14 aliases { 14 aliases {
15 mmc0 = "/mmc@78000600"; /* eMM 15 mmc0 = "/mmc@78000600"; /* eMMC */
16 mmc1 = "/mmc@78000000"; /* uSD 16 mmc1 = "/mmc@78000000"; /* uSD slot */
17 mmc2 = "/mmc@78000400"; /* WiF 17 mmc2 = "/mmc@78000400"; /* WiFi */
18 18
19 rtc0 = &pmic; 19 rtc0 = &pmic;
20 rtc1 = "/rtc@7000e000"; 20 rtc1 = "/rtc@7000e000";
21 21
22 display0 = &lcd; 22 display0 = &lcd;
23 display1 = &hdmi; 23 display1 = &hdmi;
24 24
25 serial1 = &uartc; /* Bluetooth 25 serial1 = &uartc; /* Bluetooth */
26 serial2 = &uartb; /* GPS */ 26 serial2 = &uartb; /* GPS */
27 }; 27 };
28 28
29 /* 29 /*
30 * The decompressor and also some boot 30 * The decompressor and also some bootloaders rely on a
31 * pre-existing /chosen node to be ava 31 * pre-existing /chosen node to be available to insert the
32 * command line and merge other ATAGS 32 * command line and merge other ATAGS info.
33 */ 33 */
34 chosen {}; 34 chosen {};
35 35
36 firmware { 36 firmware {
37 trusted-foundations { 37 trusted-foundations {
38 compatible = "tlm,trus 38 compatible = "tlm,trusted-foundations";
39 tlm,version-major = <2 39 tlm,version-major = <2>;
40 tlm,version-minor = <8 40 tlm,version-minor = <8>;
41 }; 41 };
42 }; 42 };
43 43
44 memory@80000000 { 44 memory@80000000 {
45 reg = <0x80000000 0x40000000>; 45 reg = <0x80000000 0x40000000>;
46 }; 46 };
47 47
48 reserved-memory { 48 reserved-memory {
49 #address-cells = <1>; 49 #address-cells = <1>;
50 #size-cells = <1>; 50 #size-cells = <1>;
51 ranges; 51 ranges;
52 52
53 linux,cma@80000000 { 53 linux,cma@80000000 {
54 compatible = "shared-d 54 compatible = "shared-dma-pool";
55 alloc-ranges = <0x8000 55 alloc-ranges = <0x80000000 0x30000000>;
56 size = <0x10000000>; 56 size = <0x10000000>; /* 256MiB */
57 linux,cma-default; 57 linux,cma-default;
58 reusable; 58 reusable;
59 }; 59 };
60 60
61 ramoops@beb00000 { 61 ramoops@beb00000 {
62 compatible = "ramoops" 62 compatible = "ramoops";
63 reg = <0xbeb00000 0x10 63 reg = <0xbeb00000 0x10000>; /* 64kB */
64 console-size = <0x8000 64 console-size = <0x8000>; /* 32kB */
65 record-size = <0x400>; 65 record-size = <0x400>; /* 1kB */
66 ecc-size = <16>; 66 ecc-size = <16>;
67 }; 67 };
68 68
69 trustzone@bfe00000 { 69 trustzone@bfe00000 {
70 reg = <0xbfe00000 0x20 70 reg = <0xbfe00000 0x200000>; /* 2MB */
71 no-map; 71 no-map;
72 }; 72 };
73 }; 73 };
74 74
75 host1x@50000000 { 75 host1x@50000000 {
76 hdmi: hdmi@54280000 { 76 hdmi: hdmi@54280000 {
77 status = "okay"; 77 status = "okay";
78 78
79 hdmi-supply = <&hdmi_5 79 hdmi-supply = <&hdmi_5v0_sys>;
80 pll-supply = <&vdd_1v8 80 pll-supply = <&vdd_1v8_vio>;
81 vdd-supply = <&vdd_3v3 81 vdd-supply = <&vdd_3v3_sys>;
82 82
83 nvidia,hpd-gpio = <&gp 83 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
84 nvidia,ddc-i2c-bus = < 84 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85 }; 85 };
86 }; 86 };
87 87
88 gpio@6000d000 { 88 gpio@6000d000 {
89 init-lpm-in-hog { 89 init-lpm-in-hog {
90 gpio-hog; 90 gpio-hog;
91 gpios = <TEGRA_GPIO(I, 91 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
92 <TEGRA_GPIO(B, 92 <TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
93 input; 93 input;
94 }; 94 };
95 95
96 init-lpm-out-hog { 96 init-lpm-out-hog {
97 gpio-hog; 97 gpio-hog;
98 gpios = <TEGRA_GPIO(K, 98 gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
99 <TEGRA_GPIO(R, 99 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
100 output-low; 100 output-low;
101 }; 101 };
102 102
103 usb-charge-limit-hog { 103 usb-charge-limit-hog {
104 gpio-hog; 104 gpio-hog;
105 gpios = <TEGRA_GPIO(R, 105 gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
106 output-high; 106 output-high;
107 }; 107 };
108 }; 108 };
109 109
110 vde@6001a000 { 110 vde@6001a000 {
111 assigned-clocks = <&tegra_car 111 assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
112 assigned-clock-parents = <&teg 112 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
113 assigned-clock-rates = <408000 113 assigned-clock-rates = <408000000>;
114 }; 114 };
115 115
116 pinmux@70000868 { 116 pinmux@70000868 {
117 pinctrl-names = "default"; 117 pinctrl-names = "default";
118 pinctrl-0 = <&state_default>; 118 pinctrl-0 = <&state_default>;
119 119
120 state_default: pinmux { 120 state_default: pinmux {
121 /* SDMMC1 pinmux */ 121 /* SDMMC1 pinmux */
122 sdmmc1_clk { 122 sdmmc1_clk {
123 nvidia,pins = 123 nvidia,pins = "sdmmc1_clk_pz0";
124 nvidia,functio 124 nvidia,function = "sdmmc1";
125 nvidia,pull = 125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126 nvidia,tristat 126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
127 nvidia,enable- 127 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128 }; 128 };
129 129
130 sdmmc1_cmd { 130 sdmmc1_cmd {
131 nvidia,pins = 131 nvidia,pins = "sdmmc1_dat3_py4",
132 132 "sdmmc1_dat2_py5",
133 133 "sdmmc1_dat1_py6",
134 134 "sdmmc1_dat0_py7",
135 135 "sdmmc1_cmd_pz1";
136 nvidia,functio 136 nvidia,function = "sdmmc1";
137 nvidia,pull = 137 nvidia,pull = <TEGRA_PIN_PULL_UP>;
138 nvidia,tristat 138 nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 nvidia,enable- 139 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140 }; 140 };
141 141
142 sdmmc1_cd { 142 sdmmc1_cd {
143 nvidia,pins = 143 nvidia,pins = "gmi_iordy_pi5";
144 nvidia,functio 144 nvidia,function = "rsvd1";
145 nvidia,pull = 145 nvidia,pull = <TEGRA_PIN_PULL_UP>;
146 nvidia,tristat 146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 nvidia,enable- 147 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148 }; 148 };
149 149
150 sdmmc1_wp { 150 sdmmc1_wp {
151 nvidia,pins = 151 nvidia,pins = "vi_d11_pt3";
152 nvidia,functio 152 nvidia,function = "rsvd2";
153 nvidia,pull = 153 nvidia,pull = <TEGRA_PIN_PULL_UP>;
154 nvidia,tristat 154 nvidia,tristate = <TEGRA_PIN_DISABLE>;
155 nvidia,enable- 155 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156 }; 156 };
157 157
158 /* SDMMC2 pinmux */ 158 /* SDMMC2 pinmux */
159 vi_d1_pd5 { 159 vi_d1_pd5 {
160 nvidia,pins = 160 nvidia,pins = "vi_d1_pd5",
161 161 "vi_d2_pl0",
162 162 "vi_d3_pl1",
163 163 "vi_d5_pl3",
164 164 "vi_d7_pl5";
165 nvidia,functio 165 nvidia,function = "sdmmc2";
166 nvidia,pull = 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristat 167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 nvidia,enable- 168 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169 }; 169 };
170 170
171 vi_d8_pl6 { 171 vi_d8_pl6 {
172 nvidia,pins = 172 nvidia,pins = "vi_d8_pl6",
173 173 "vi_d9_pl7";
174 nvidia,functio 174 nvidia,function = "sdmmc2";
175 nvidia,pull = 175 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176 nvidia,tristat 176 nvidia,tristate = <TEGRA_PIN_DISABLE>;
177 nvidia,enable- 177 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178 nvidia,lock = 178 nvidia,lock = <0>;
179 nvidia,io-rese 179 nvidia,io-reset = <0>;
180 }; 180 };
181 181
182 /* SDMMC3 pinmux */ 182 /* SDMMC3 pinmux */
183 sdmmc3_clk { 183 sdmmc3_clk {
184 nvidia,pins = 184 nvidia,pins = "sdmmc3_clk_pa6";
185 nvidia,functio 185 nvidia,function = "sdmmc3";
186 nvidia,pull = 186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 nvidia,tristat 187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
188 nvidia,enable- 188 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189 }; 189 };
190 190
191 sdmmc3_cmd { 191 sdmmc3_cmd {
192 nvidia,pins = 192 nvidia,pins = "sdmmc3_cmd_pa7",
193 193 "sdmmc3_dat0_pb7",
194 194 "sdmmc3_dat1_pb6",
195 195 "sdmmc3_dat2_pb5",
196 196 "sdmmc3_dat3_pb4",
197 197 "sdmmc3_dat4_pd1",
198 198 "sdmmc3_dat5_pd0",
199 199 "sdmmc3_dat6_pd3",
200 200 "sdmmc3_dat7_pd4";
201 nvidia,functio 201 nvidia,function = "sdmmc3";
202 nvidia,pull = 202 nvidia,pull = <TEGRA_PIN_PULL_UP>;
203 nvidia,tristat 203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 nvidia,enable- 204 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
205 }; 205 };
206 206
207 /* SDMMC4 pinmux */ 207 /* SDMMC4 pinmux */
208 sdmmc4_clk { 208 sdmmc4_clk {
209 nvidia,pins = 209 nvidia,pins = "sdmmc4_clk_pcc4";
210 nvidia,functio 210 nvidia,function = "sdmmc4";
211 nvidia,pull = 211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212 nvidia,tristat 212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
213 nvidia,enable- 213 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214 }; 214 };
215 215
216 sdmmc4_cmd { 216 sdmmc4_cmd {
217 nvidia,pins = 217 nvidia,pins = "sdmmc4_cmd_pt7",
218 218 "sdmmc4_dat0_paa0",
219 219 "sdmmc4_dat1_paa1",
220 220 "sdmmc4_dat2_paa2",
221 221 "sdmmc4_dat3_paa3",
222 222 "sdmmc4_dat4_paa4",
223 223 "sdmmc4_dat5_paa5",
224 224 "sdmmc4_dat6_paa6",
225 225 "sdmmc4_dat7_paa7";
226 nvidia,functio 226 nvidia,function = "sdmmc4";
227 nvidia,pull = 227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
228 nvidia,tristat 228 nvidia,tristate = <TEGRA_PIN_DISABLE>;
229 nvidia,enable- 229 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230 }; 230 };
231 231
232 sdmmc4_rst_n { 232 sdmmc4_rst_n {
233 nvidia,pins = 233 nvidia,pins = "sdmmc4_rst_n_pcc3";
234 nvidia,functio 234 nvidia,function = "rsvd2";
235 nvidia,pull = 235 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
236 nvidia,tristat 236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
237 nvidia,enable- 237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238 }; 238 };
239 239
240 cam_mclk { 240 cam_mclk {
241 nvidia,pins = 241 nvidia,pins = "cam_mclk_pcc0";
242 nvidia,functio 242 nvidia,function = "vi_alt3";
243 nvidia,pull = 243 nvidia,pull = <TEGRA_PIN_PULL_UP>;
244 nvidia,tristat 244 nvidia,tristate = <TEGRA_PIN_DISABLE>;
245 nvidia,enable- 245 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246 }; 246 };
247 247
248 drive_sdmmc4 { 248 drive_sdmmc4 {
249 nvidia,pins = 249 nvidia,pins = "drive_gma",
250 250 "drive_gmb",
251 251 "drive_gmc",
252 252 "drive_gmd";
253 nvidia,pull-do 253 nvidia,pull-down-strength = <9>;
254 nvidia,pull-up 254 nvidia,pull-up-strength = <9>;
255 nvidia,slew-ra 255 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
256 nvidia,slew-ra 256 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
257 }; 257 };
258 258
259 /* I2C pinmux */ 259 /* I2C pinmux */
260 gen1_i2c { 260 gen1_i2c {
261 nvidia,pins = 261 nvidia,pins = "gen1_i2c_scl_pc4",
262 262 "gen1_i2c_sda_pc5";
263 nvidia,functio 263 nvidia,function = "i2c1";
264 nvidia,pull = 264 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265 nvidia,tristat 265 nvidia,tristate = <TEGRA_PIN_DISABLE>;
266 nvidia,enable- 266 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267 nvidia,open-dr 267 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
268 nvidia,lock = 268 nvidia,lock = <0>;
269 }; 269 };
270 270
271 gen2_i2c { 271 gen2_i2c {
272 nvidia,pins = 272 nvidia,pins = "gen2_i2c_scl_pt5",
273 273 "gen2_i2c_sda_pt6";
274 nvidia,functio 274 nvidia,function = "i2c2";
275 nvidia,pull = 275 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276 nvidia,tristat 276 nvidia,tristate = <TEGRA_PIN_DISABLE>;
277 nvidia,enable- 277 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278 nvidia,open-dr 278 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
279 nvidia,lock = 279 nvidia,lock = <0>;
280 }; 280 };
281 281
282 cam_i2c { 282 cam_i2c {
283 nvidia,pins = 283 nvidia,pins = "cam_i2c_scl_pbb1",
284 284 "cam_i2c_sda_pbb2";
285 nvidia,functio 285 nvidia,function = "i2c3";
286 nvidia,pull = 286 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287 nvidia,tristat 287 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 nvidia,enable- 288 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289 nvidia,open-dr 289 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
290 nvidia,lock = 290 nvidia,lock = <0>;
291 }; 291 };
292 292
293 ddc_i2c { 293 ddc_i2c {
294 nvidia,pins = 294 nvidia,pins = "ddc_scl_pv4",
295 295 "ddc_sda_pv5";
296 nvidia,functio 296 nvidia,function = "i2c4";
297 nvidia,pull = 297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristat 298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
299 nvidia,enable- 299 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
300 nvidia,lock = 300 nvidia,lock = <0>;
301 }; 301 };
302 302
303 pwr_i2c { 303 pwr_i2c {
304 nvidia,pins = 304 nvidia,pins = "pwr_i2c_scl_pz6",
305 305 "pwr_i2c_sda_pz7";
306 nvidia,functio 306 nvidia,function = "i2cpwr";
307 nvidia,pull = 307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristat 308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 nvidia,enable- 309 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310 nvidia,open-dr 310 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
311 nvidia,lock = 311 nvidia,lock = <0>;
312 }; 312 };
313 313
314 hotplug_i2c { 314 hotplug_i2c {
315 nvidia,pins = 315 nvidia,pins = "pu4";
316 nvidia,functio 316 nvidia,function = "rsvd4";
317 nvidia,pull = 317 nvidia,pull = <TEGRA_PIN_PULL_UP>;
318 nvidia,tristat 318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
319 nvidia,enable- 319 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
320 }; 320 };
321 321
322 /* HDMI pinmux */ 322 /* HDMI pinmux */
323 hdmi_cec { 323 hdmi_cec {
324 nvidia,pins = 324 nvidia,pins = "hdmi_cec_pee3";
325 nvidia,functio 325 nvidia,function = "cec";
326 nvidia,pull = 326 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327 nvidia,tristat 327 nvidia,tristate = <TEGRA_PIN_DISABLE>;
328 nvidia,enable- 328 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329 nvidia,open-dr 329 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330 nvidia,lock = 330 nvidia,lock = <0>;
331 }; 331 };
332 332
333 hdmi_hpd { 333 hdmi_hpd {
334 nvidia,pins = 334 nvidia,pins = "hdmi_int_pn7";
335 nvidia,functio 335 nvidia,function = "hdmi";
336 nvidia,pull = 336 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
337 nvidia,tristat 337 nvidia,tristate = <TEGRA_PIN_ENABLE>;
338 nvidia,enable- 338 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
339 }; 339 };
340 340
341 /* UART-A */ 341 /* UART-A */
342 ulpi_data0_po1 { 342 ulpi_data0_po1 {
343 nvidia,pins = 343 nvidia,pins = "ulpi_data0_po1";
344 nvidia,functio 344 nvidia,function = "uarta";
345 nvidia,pull = 345 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346 nvidia,tristat 346 nvidia,tristate = <TEGRA_PIN_DISABLE>;
347 nvidia,enable- 347 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348 }; 348 };
349 349
350 ulpi_data1_po2 { 350 ulpi_data1_po2 {
351 nvidia,pins = 351 nvidia,pins = "ulpi_data1_po2";
352 nvidia,functio 352 nvidia,function = "uarta";
353 nvidia,pull = 353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354 nvidia,tristat 354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
355 nvidia,enable- 355 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356 }; 356 };
357 357
358 ulpi_data5_po6 { 358 ulpi_data5_po6 {
359 nvidia,pins = 359 nvidia,pins = "ulpi_data5_po6";
360 nvidia,functio 360 nvidia,function = "uarta";
361 nvidia,pull = 361 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362 nvidia,tristat 362 nvidia,tristate = <TEGRA_PIN_ENABLE>;
363 nvidia,enable- 363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364 }; 364 };
365 365
366 ulpi_data7_po0 { 366 ulpi_data7_po0 {
367 nvidia,pins = 367 nvidia,pins = "ulpi_data7_po0",
368 368 "ulpi_data2_po3",
369 369 "ulpi_data3_po4",
370 370 "ulpi_data4_po5",
371 371 "ulpi_data6_po7";
372 nvidia,functio 372 nvidia,function = "uarta";
373 nvidia,pull = 373 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374 nvidia,tristat 374 nvidia,tristate = <TEGRA_PIN_DISABLE>;
375 nvidia,enable- 375 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376 }; 376 };
377 377
378 /* UART-B */ 378 /* UART-B */
379 uartb_txd_rts { 379 uartb_txd_rts {
380 nvidia,pins = 380 nvidia,pins = "uart2_txd_pc2",
381 381 "uart2_rts_n_pj6";
382 nvidia,functio 382 nvidia,function = "uartb";
383 nvidia,pull = 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384 nvidia,tristat 384 nvidia,tristate = <TEGRA_PIN_DISABLE>;
385 nvidia,enable- 385 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386 }; 386 };
387 387
388 uartb_rxd_cts { 388 uartb_rxd_cts {
389 nvidia,pins = 389 nvidia,pins = "uart2_rxd_pc3",
390 390 "uart2_cts_n_pj5";
391 nvidia,functio 391 nvidia,function = "uartb";
392 nvidia,pull = 392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristat 393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 nvidia,enable- 394 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395 }; 395 };
396 396
397 /* UART-C */ 397 /* UART-C */
398 uartc_rxd_cts { 398 uartc_rxd_cts {
399 nvidia,pins = 399 nvidia,pins = "uart3_cts_n_pa1",
400 400 "uart3_rxd_pw7";
401 nvidia,functio 401 nvidia,function = "uartc";
402 nvidia,pull = 402 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403 nvidia,tristat 403 nvidia,tristate = <TEGRA_PIN_DISABLE>;
404 nvidia,enable- 404 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
405 }; 405 };
406 406
407 uartc_txd_rts { 407 uartc_txd_rts {
408 nvidia,pins = 408 nvidia,pins = "uart3_rts_n_pc0",
409 409 "uart3_txd_pw6";
410 nvidia,functio 410 nvidia,function = "uartc";
411 nvidia,pull = 411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristat 412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 nvidia,enable- 413 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414 }; 414 };
415 415
416 /* UART-D */ 416 /* UART-D */
417 ulpi_nxt_py2 { 417 ulpi_nxt_py2 {
418 nvidia,pins = 418 nvidia,pins = "ulpi_nxt_py2";
419 nvidia,functio 419 nvidia,function = "uartd";
420 nvidia,pull = 420 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristat 421 nvidia,tristate = <TEGRA_PIN_ENABLE>;
422 nvidia,enable- 422 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423 }; 423 };
424 424
425 ulpi_clk_py0 { 425 ulpi_clk_py0 {
426 nvidia,pins = 426 nvidia,pins = "ulpi_clk_py0",
427 427 "ulpi_dir_py1",
428 428 "ulpi_stp_py3";
429 nvidia,functio 429 nvidia,function = "uartd";
430 nvidia,pull = 430 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431 nvidia,tristat 431 nvidia,tristate = <TEGRA_PIN_ENABLE>;
432 nvidia,enable- 432 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433 }; 433 };
434 434
435 /* I2S pinmux */ 435 /* I2S pinmux */
436 dap_i2s0 { 436 dap_i2s0 {
437 nvidia,pins = 437 nvidia,pins = "dap1_fs_pn0",
438 438 "dap1_din_pn1",
439 439 "dap1_dout_pn2",
440 440 "dap1_sclk_pn3";
441 nvidia,functio 441 nvidia,function = "i2s0";
442 nvidia,pull = 442 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443 nvidia,tristat 443 nvidia,tristate = <TEGRA_PIN_ENABLE>;
444 nvidia,enable- 444 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445 }; 445 };
446 446
447 dap_i2s1 { 447 dap_i2s1 {
448 nvidia,pins = 448 nvidia,pins = "dap2_fs_pa2",
449 449 "dap2_sclk_pa3",
450 450 "dap2_din_pa4",
451 451 "dap2_dout_pa5";
452 nvidia,functio 452 nvidia,function = "i2s1";
453 nvidia,pull = 453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454 nvidia,tristat 454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
455 nvidia,enable- 455 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456 }; 456 };
457 457
458 dap3_fs { 458 dap3_fs {
459 nvidia,pins = 459 nvidia,pins = "dap3_fs_pp0",
460 460 "dap3_din_pp1";
461 nvidia,functio 461 nvidia,function = "i2s2";
462 nvidia,pull = 462 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463 nvidia,tristat 463 nvidia,tristate = <TEGRA_PIN_ENABLE>;
464 nvidia,enable- 464 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465 }; 465 };
466 466
467 dap3_dout { 467 dap3_dout {
468 nvidia,pins = 468 nvidia,pins = "dap3_dout_pp2",
469 469 "dap3_sclk_pp3";
470 nvidia,functio 470 nvidia,function = "i2s2";
471 nvidia,pull = 471 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472 nvidia,tristat 472 nvidia,tristate = <TEGRA_PIN_DISABLE>;
473 nvidia,enable- 473 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474 }; 474 };
475 475
476 dap_i2s3 { 476 dap_i2s3 {
477 nvidia,pins = 477 nvidia,pins = "dap4_fs_pp4",
478 478 "dap4_din_pp5",
479 479 "dap4_dout_pp6",
480 480 "dap4_sclk_pp7";
481 nvidia,functio 481 nvidia,function = "i2s3";
482 nvidia,pull = 482 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483 nvidia,tristat 483 nvidia,tristate = <TEGRA_PIN_DISABLE>;
484 nvidia,enable- 484 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
485 }; 485 };
486 486
487 /* Sensors pinmux */ 487 /* Sensors pinmux */
488 nct_irq { 488 nct_irq {
489 nvidia,pins = 489 nvidia,pins = "pcc2";
490 nvidia,functio 490 nvidia,function = "i2s4";
491 nvidia,pull = 491 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
492 nvidia,tristat 492 nvidia,tristate = <TEGRA_PIN_DISABLE>;
493 nvidia,enable- 493 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494 }; 494 };
495 495
496 /* Asus EC pinmux */ 496 /* Asus EC pinmux */
497 ec_irqs { 497 ec_irqs {
498 nvidia,pins = 498 nvidia,pins = "kb_row10_ps2",
499 499 "kb_row15_ps7";
500 nvidia,functio 500 nvidia,function = "kbc";
501 nvidia,pull = 501 nvidia,pull = <TEGRA_PIN_PULL_UP>;
502 nvidia,tristat 502 nvidia,tristate = <TEGRA_PIN_DISABLE>;
503 nvidia,enable- 503 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504 }; 504 };
505 505
506 ec_reqs { 506 ec_reqs {
507 nvidia,pins = 507 nvidia,pins = "kb_col1_pq1";
508 nvidia,functio 508 nvidia,function = "kbc";
509 nvidia,pull = 509 nvidia,pull = <TEGRA_PIN_PULL_UP>;
510 nvidia,tristat 510 nvidia,tristate = <TEGRA_PIN_DISABLE>;
511 nvidia,enable- 511 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512 }; 512 };
513 513
514 /* Memory type bootstr 514 /* Memory type bootstrap */
515 mem_boostraps { 515 mem_boostraps {
516 nvidia,pins = 516 nvidia,pins = "gmi_ad4_pg4",
517 517 "gmi_ad5_pg5";
518 nvidia,functio 518 nvidia,function = "nand";
519 nvidia,pull = 519 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520 nvidia,tristat 520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 nvidia,enable- 521 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522 }; 522 };
523 523
524 /* PCI-e pinmux */ 524 /* PCI-e pinmux */
525 pex_l2_rst_n { 525 pex_l2_rst_n {
526 nvidia,pins = 526 nvidia,pins = "pex_l2_rst_n_pcc6",
527 527 "pex_l0_rst_n_pdd1",
528 528 "pex_l1_rst_n_pdd5";
529 nvidia,functio 529 nvidia,function = "pcie";
530 nvidia,pull = 530 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531 nvidia,tristat 531 nvidia,tristate = <TEGRA_PIN_DISABLE>;
532 nvidia,enable- 532 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533 }; 533 };
534 534
535 pex_l2_clkreq_n { 535 pex_l2_clkreq_n {
536 nvidia,pins = 536 nvidia,pins = "pex_l2_clkreq_n_pcc7",
537 537 "pex_l0_prsnt_n_pdd0",
538 538 "pex_l0_clkreq_n_pdd2",
539 539 "pex_wake_n_pdd3",
540 540 "pex_l1_prsnt_n_pdd4",
541 541 "pex_l1_clkreq_n_pdd6",
542 542 "pex_l2_prsnt_n_pdd7";
543 nvidia,functio 543 nvidia,function = "pcie";
544 nvidia,pull = 544 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545 nvidia,tristat 545 nvidia,tristate = <TEGRA_PIN_DISABLE>;
546 nvidia,enable- 546 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547 }; 547 };
548 548
549 /* SPI pinmux */ 549 /* SPI pinmux */
550 spi1_mosi_px4 { 550 spi1_mosi_px4 {
551 nvidia,pins = 551 nvidia,pins = "spi1_mosi_px4",
552 552 "spi1_sck_px5",
553 553 "spi1_cs0_n_px6",
554 554 "spi1_miso_px7";
555 nvidia,functio 555 nvidia,function = "spi1";
556 nvidia,pull = 556 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557 nvidia,tristat 557 nvidia,tristate = <TEGRA_PIN_ENABLE>;
558 nvidia,enable- 558 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
559 }; 559 };
560 560
561 hp_detect { 561 hp_detect {
562 nvidia,pins = 562 nvidia,pins = "spi2_cs1_n_pw2";
563 nvidia,functio 563 nvidia,function = "spi2";
564 nvidia,pull = 564 nvidia,pull = <TEGRA_PIN_PULL_UP>;
565 nvidia,tristat 565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
566 nvidia,enable- 566 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567 }; 567 };
568 568
569 mic_detect { 569 mic_detect {
570 nvidia,pins = 570 nvidia,pins = "spi2_sck_px2";
571 nvidia,functio 571 nvidia,function = "spi2";
572 nvidia,pull = 572 nvidia,pull = <TEGRA_PIN_PULL_UP>;
573 nvidia,tristat 573 nvidia,tristate = <TEGRA_PIN_DISABLE>;
574 nvidia,enable- 574 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
575 }; 575 };
576 576
577 gmi_a17_pb0 { 577 gmi_a17_pb0 {
578 nvidia,pins = 578 nvidia,pins = "gmi_a17_pb0",
579 579 "gmi_a16_pj7";
580 nvidia,functio 580 nvidia,function = "spi4";
581 nvidia,pull = 581 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582 nvidia,tristat 582 nvidia,tristate = <TEGRA_PIN_ENABLE>;
583 nvidia,enable- 583 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
584 }; 584 };
585 585
586 gmi_a18_pb1 { 586 gmi_a18_pb1 {
587 nvidia,pins = 587 nvidia,pins = "gmi_a18_pb1";
588 nvidia,functio 588 nvidia,function = "spi4";
589 nvidia,pull = 589 nvidia,pull = <TEGRA_PIN_PULL_UP>;
590 nvidia,tristat 590 nvidia,tristate = <TEGRA_PIN_DISABLE>;
591 nvidia,enable- 591 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592 }; 592 };
593 593
594 gmi_a19_pk7 { 594 gmi_a19_pk7 {
595 nvidia,pins = 595 nvidia,pins = "gmi_a19_pk7";
596 nvidia,functio 596 nvidia,function = "spi4";
597 nvidia,pull = 597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598 nvidia,tristat 598 nvidia,tristate = <TEGRA_PIN_DISABLE>;
599 nvidia,enable- 599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600 }; 600 };
601 601
602 /* Display A pinmux */ 602 /* Display A pinmux */
603 lcd_pwr0_pb2 { 603 lcd_pwr0_pb2 {
604 nvidia,pins = 604 nvidia,pins = "lcd_pwr0_pb2",
605 605 "lcd_pclk_pb3",
606 606 "lcd_pwr1_pc1",
607 607 "lcd_d0_pe0",
608 608 "lcd_d1_pe1",
609 609 "lcd_d2_pe2",
610 610 "lcd_d3_pe3",
611 611 "lcd_d4_pe4",
612 612 "lcd_d5_pe5",
613 613 "lcd_d6_pe6",
614 614 "lcd_d7_pe7",
615 615 "lcd_d8_pf0",
616 616 "lcd_d9_pf1",
617 617 "lcd_d10_pf2",
618 618 "lcd_d11_pf3",
619 619 "lcd_d12_pf4",
620 620 "lcd_d13_pf5",
621 621 "lcd_d14_pf6",
622 622 "lcd_d15_pf7",
623 623 "lcd_de_pj1",
624 624 "lcd_hsync_pj3",
625 625 "lcd_vsync_pj4",
626 626 "lcd_d16_pm0",
627 627 "lcd_d17_pm1",
628 628 "lcd_d18_pm2",
629 629 "lcd_d19_pm3",
630 630 "lcd_d20_pm4",
631 631 "lcd_d21_pm5",
632 632 "lcd_d22_pm6",
633 633 "lcd_d23_pm7",
634 634 "lcd_dc0_pn6",
635 635 "lcd_sdin_pz2";
636 nvidia,functio 636 nvidia,function = "displaya";
637 nvidia,pull = 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638 nvidia,tristat 638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
639 nvidia,enable- 639 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
640 }; 640 };
641 641
642 lcd_cs0_n_pn4 { 642 lcd_cs0_n_pn4 {
643 nvidia,pins = 643 nvidia,pins = "lcd_cs0_n_pn4",
644 644 "lcd_sdout_pn5",
645 645 "lcd_wr_n_pz3";
646 nvidia,functio 646 nvidia,function = "displaya";
647 nvidia,pull = 647 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648 nvidia,tristat 648 nvidia,tristate = <TEGRA_PIN_ENABLE>;
649 nvidia,enable- 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
650 }; 650 };
651 651
652 blink { 652 blink {
653 nvidia,pins = 653 nvidia,pins = "clk_32k_out_pa0";
654 nvidia,functio 654 nvidia,function = "blink";
655 nvidia,pull = 655 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656 nvidia,tristat 656 nvidia,tristate = <TEGRA_PIN_DISABLE>;
657 nvidia,enable- 657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658 }; 658 };
659 659
660 /* KBC keys */ 660 /* KBC keys */
661 kb_col0_pq0 { 661 kb_col0_pq0 {
662 nvidia,pins = 662 nvidia,pins = "kb_col0_pq0";
663 nvidia,functio 663 nvidia,function = "kbc";
664 nvidia,pull = 664 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665 nvidia,tristat 665 nvidia,tristate = <TEGRA_PIN_ENABLE>;
666 nvidia,enable- 666 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
667 }; 667 };
668 668
669 kb_col1_pq1 { 669 kb_col1_pq1 {
670 nvidia,pins = 670 nvidia,pins = "kb_row1_pr1",
671 671 "kb_row3_pr3",
672 672 "kb_row8_ps0",
673 673 "kb_row14_ps6";
674 nvidia,functio 674 nvidia,function = "kbc";
675 nvidia,pull = 675 nvidia,pull = <TEGRA_PIN_PULL_UP>;
676 nvidia,tristat 676 nvidia,tristate = <TEGRA_PIN_DISABLE>;
677 nvidia,enable- 677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 }; 678 };
679 679
680 kb_col4_pq4 { 680 kb_col4_pq4 {
681 nvidia,pins = 681 nvidia,pins = "kb_col4_pq4",
682 682 "kb_col5_pq5",
683 683 "kb_col7_pq7",
684 684 "kb_row2_pr2",
685 685 "kb_row4_pr4",
686 686 "kb_row5_pr5",
687 687 "kb_row12_ps4",
688 688 "kb_row13_ps5";
689 nvidia,functio 689 nvidia,function = "kbc";
690 nvidia,pull = 690 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
691 nvidia,tristat 691 nvidia,tristate = <TEGRA_PIN_ENABLE>;
692 nvidia,enable- 692 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
693 }; 693 };
694 694
695 gmi_wp_n_pc7 { 695 gmi_wp_n_pc7 {
696 nvidia,pins = 696 nvidia,pins = "gmi_wp_n_pc7",
697 697 "gmi_wait_pi7",
698 698 "gmi_cs3_n_pk4";
699 nvidia,functio 699 nvidia,function = "rsvd1";
700 nvidia,pull = 700 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701 nvidia,tristat 701 nvidia,tristate = <TEGRA_PIN_ENABLE>;
702 nvidia,enable- 702 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703 }; 703 };
704 704
705 gmi_cs0_n_pj0 { 705 gmi_cs0_n_pj0 {
706 nvidia,pins = 706 nvidia,pins = "gmi_cs0_n_pj0",
707 707 "gmi_cs1_n_pj2",
708 708 "gmi_cs2_n_pk3";
709 nvidia,functio 709 nvidia,function = "rsvd1";
710 nvidia,pull = 710 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711 nvidia,tristat 711 nvidia,tristate = <TEGRA_PIN_ENABLE>;
712 nvidia,enable- 712 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713 }; 713 };
714 714
715 vi_pclk_pt0 { 715 vi_pclk_pt0 {
716 nvidia,pins = 716 nvidia,pins = "vi_pclk_pt0";
717 nvidia,functio 717 nvidia,function = "rsvd1";
718 nvidia,pull = 718 nvidia,pull = <TEGRA_PIN_PULL_UP>;
719 nvidia,tristat 719 nvidia,tristate = <TEGRA_PIN_ENABLE>;
720 nvidia,enable- 720 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721 nvidia,lock = 721 nvidia,lock = <0>;
722 nvidia,io-rese 722 nvidia,io-reset = <0>;
723 }; 723 };
724 724
725 /* GPIO keys pinmux */ 725 /* GPIO keys pinmux */
726 power_key { 726 power_key {
727 nvidia,pins = 727 nvidia,pins = "pv0";
728 nvidia,functio 728 nvidia,function = "rsvd1";
729 nvidia,pull = 729 nvidia,pull = <TEGRA_PIN_PULL_UP>;
730 nvidia,tristat 730 nvidia,tristate = <TEGRA_PIN_ENABLE>;
731 nvidia,enable- 731 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
732 }; 732 };
733 733
734 vol_keys { 734 vol_keys {
735 nvidia,pins = 735 nvidia,pins = "kb_col2_pq2",
736 736 "kb_col3_pq3";
737 nvidia,functio 737 nvidia,function = "rsvd4";
738 nvidia,pull = 738 nvidia,pull = <TEGRA_PIN_PULL_UP>;
739 nvidia,tristat 739 nvidia,tristate = <TEGRA_PIN_ENABLE>;
740 nvidia,enable- 740 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741 }; 741 };
742 742
743 /* Bluetooth */ 743 /* Bluetooth */
744 bt_shutdown { 744 bt_shutdown {
745 nvidia,pins = 745 nvidia,pins = "pu0";
746 nvidia,functio 746 nvidia,function = "rsvd4";
747 nvidia,pull = 747 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748 nvidia,tristat 748 nvidia,tristate = <TEGRA_PIN_DISABLE>;
749 nvidia,enable- 749 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
750 }; 750 };
751 751
752 bt_dev_wake { 752 bt_dev_wake {
753 nvidia,pins = 753 nvidia,pins = "pu1";
754 nvidia,functio 754 nvidia,function = "rsvd1";
755 nvidia,pull = 755 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756 nvidia,tristat 756 nvidia,tristate = <TEGRA_PIN_DISABLE>;
757 nvidia,enable- 757 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758 }; 758 };
759 759
760 bt_host_wake { 760 bt_host_wake {
761 nvidia,pins = 761 nvidia,pins = "pu6";
762 nvidia,functio 762 nvidia,function = "rsvd4";
763 nvidia,pull = 763 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764 nvidia,tristat 764 nvidia,tristate = <TEGRA_PIN_DISABLE>;
765 nvidia,enable- 765 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766 }; 766 };
767 767
768 pu2 { 768 pu2 {
769 nvidia,pins = 769 nvidia,pins = "pu2";
770 nvidia,functio 770 nvidia,function = "rsvd1";
771 nvidia,pull = 771 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772 nvidia,tristat 772 nvidia,tristate = <TEGRA_PIN_DISABLE>;
773 nvidia,enable- 773 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774 }; 774 };
775 775
776 pu3 { 776 pu3 {
777 nvidia,pins = 777 nvidia,pins = "pu3";
778 nvidia,functio 778 nvidia,function = "rsvd4";
779 nvidia,pull = 779 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780 nvidia,tristat 780 nvidia,tristate = <TEGRA_PIN_DISABLE>;
781 nvidia,enable- 781 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782 }; 782 };
783 783
784 pcc1 { 784 pcc1 {
785 nvidia,pins = 785 nvidia,pins = "pcc1";
786 nvidia,functio 786 nvidia,function = "rsvd2";
787 nvidia,pull = 787 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
788 nvidia,tristat 788 nvidia,tristate = <TEGRA_PIN_ENABLE>;
789 nvidia,enable- 789 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
790 }; 790 };
791 791
792 pv2 { 792 pv2 {
793 nvidia,pins = 793 nvidia,pins = "pv2";
794 nvidia,functio 794 nvidia,function = "rsvd2";
795 nvidia,pull = 795 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796 nvidia,tristat 796 nvidia,tristate = <TEGRA_PIN_DISABLE>;
797 nvidia,enable- 797 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798 }; 798 };
799 799
800 pv3 { 800 pv3 {
801 nvidia,pins = 801 nvidia,pins = "pv3";
802 nvidia,functio 802 nvidia,function = "rsvd2";
803 nvidia,pull = 803 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804 nvidia,tristat 804 nvidia,tristate = <TEGRA_PIN_ENABLE>;
805 nvidia,enable- 805 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806 }; 806 };
807 807
808 vi_vsync_pd6 { 808 vi_vsync_pd6 {
809 nvidia,pins = 809 nvidia,pins = "vi_vsync_pd6",
810 810 "vi_hsync_pd7";
811 nvidia,functio 811 nvidia,function = "rsvd2";
812 nvidia,pull = 812 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813 nvidia,tristat 813 nvidia,tristate = <TEGRA_PIN_DISABLE>;
814 nvidia,enable- 814 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815 nvidia,lock = 815 nvidia,lock = <0>;
816 nvidia,io-rese 816 nvidia,io-reset = <0>;
817 }; 817 };
818 818
819 vi_d10_pt2 { 819 vi_d10_pt2 {
820 nvidia,pins = 820 nvidia,pins = "vi_d10_pt2",
821 821 "vi_d0_pt4", "pbb0";
822 nvidia,functio 822 nvidia,function = "rsvd2";
823 nvidia,pull = 823 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824 nvidia,tristat 824 nvidia,tristate = <TEGRA_PIN_DISABLE>;
825 nvidia,enable- 825 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826 }; 826 };
827 827
828 kb_row0_pr0 { 828 kb_row0_pr0 {
829 nvidia,pins = 829 nvidia,pins = "kb_row0_pr0";
830 nvidia,functio 830 nvidia,function = "rsvd4";
831 nvidia,pull = 831 nvidia,pull = <TEGRA_PIN_PULL_UP>;
832 nvidia,tristat 832 nvidia,tristate = <TEGRA_PIN_DISABLE>;
833 nvidia,enable- 833 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
834 }; 834 };
835 835
836 gmi_ad0_pg0 { 836 gmi_ad0_pg0 {
837 nvidia,pins = 837 nvidia,pins = "gmi_ad0_pg0",
838 838 "gmi_ad1_pg1",
839 839 "gmi_ad2_pg2",
840 840 "gmi_ad3_pg3",
841 841 "gmi_ad6_pg6",
842 842 "gmi_ad7_pg7",
843 843 "gmi_wr_n_pi0",
844 844 "gmi_oe_n_pi1",
845 845 "gmi_dqs_pi2",
846 846 "gmi_adv_n_pk0",
847 847 "gmi_clk_pk1";
848 nvidia,functio 848 nvidia,function = "nand";
849 nvidia,pull = 849 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850 nvidia,tristat 850 nvidia,tristate = <TEGRA_PIN_ENABLE>;
851 nvidia,enable- 851 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
852 }; 852 };
853 853
854 gmi_ad13_ph5 { 854 gmi_ad13_ph5 {
855 nvidia,pins = 855 nvidia,pins = "gmi_ad13_ph5";
856 nvidia,functio 856 nvidia,function = "nand";
857 nvidia,pull = 857 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
858 nvidia,tristat 858 nvidia,tristate = <TEGRA_PIN_DISABLE>;
859 nvidia,enable- 859 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
860 }; 860 };
861 861
862 gmi_ad10_ph2 { 862 gmi_ad10_ph2 {
863 nvidia,pins = 863 nvidia,pins = "gmi_ad10_ph2",
864 864 "gmi_ad11_ph3",
865 865 "gmi_ad14_ph6";
866 nvidia,functio 866 nvidia,function = "nand";
867 nvidia,pull = 867 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
868 nvidia,tristat 868 nvidia,tristate = <TEGRA_PIN_DISABLE>;
869 nvidia,enable- 869 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
870 }; 870 };
871 871
872 gmi_ad12_ph4 { 872 gmi_ad12_ph4 {
873 nvidia,pins = 873 nvidia,pins = "gmi_ad12_ph4",
874 874 "gmi_rst_n_pi4",
875 875 "gmi_cs7_n_pi6";
876 nvidia,functio 876 nvidia,function = "nand";
877 nvidia,pull = 877 nvidia,pull = <TEGRA_PIN_PULL_UP>;
878 nvidia,tristat 878 nvidia,tristate = <TEGRA_PIN_DISABLE>;
879 nvidia,enable- 879 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
880 }; 880 };
881 881
882 /* Vibrator control */ 882 /* Vibrator control */
883 vibrator { 883 vibrator {
884 nvidia,pins = 884 nvidia,pins = "gmi_ad15_ph7";
885 nvidia,functio 885 nvidia,function = "nand";
886 nvidia,pull = 886 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
887 nvidia,tristat 887 nvidia,tristate = <TEGRA_PIN_DISABLE>;
888 nvidia,enable- 888 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
889 }; 889 };
890 890
891 /* PWM pimnmux */ 891 /* PWM pimnmux */
892 pwm_0 { 892 pwm_0 {
893 nvidia,pins = 893 nvidia,pins = "gmi_ad8_ph0";
894 nvidia,functio 894 nvidia,function = "pwm0";
895 nvidia,pull = 895 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896 nvidia,tristat 896 nvidia,tristate = <TEGRA_PIN_DISABLE>;
897 nvidia,enable- 897 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
898 }; 898 };
899 899
900 pwm_2 { 900 pwm_2 {
901 nvidia,pins = 901 nvidia,pins = "pu5";
902 nvidia,functio 902 nvidia,function = "pwm2";
903 nvidia,pull = 903 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904 nvidia,tristat 904 nvidia,tristate = <TEGRA_PIN_DISABLE>;
905 nvidia,enable- 905 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906 }; 906 };
907 907
908 gmi_cs6_n_pi3 { 908 gmi_cs6_n_pi3 {
909 nvidia,pins = 909 nvidia,pins = "gmi_cs6_n_pi3";
910 nvidia,functio 910 nvidia,function = "gmi";
911 nvidia,pull = 911 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
912 nvidia,tristat 912 nvidia,tristate = <TEGRA_PIN_ENABLE>;
913 nvidia,enable- 913 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
914 }; 914 };
915 915
916 /* Spdif pinmux */ 916 /* Spdif pinmux */
917 spdif_out { 917 spdif_out {
918 nvidia,pins = 918 nvidia,pins = "spdif_out_pk5";
919 nvidia,functio 919 nvidia,function = "spdif";
920 nvidia,pull = 920 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
921 nvidia,tristat 921 nvidia,tristate = <TEGRA_PIN_ENABLE>;
922 nvidia,enable- 922 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
923 }; 923 };
924 924
925 spdif_in { 925 spdif_in {
926 nvidia,pins = 926 nvidia,pins = "spdif_in_pk6";
927 nvidia,functio 927 nvidia,function = "spdif";
928 nvidia,pull = 928 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
929 nvidia,tristat 929 nvidia,tristate = <TEGRA_PIN_ENABLE>;
930 nvidia,enable- 930 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
931 }; 931 };
932 932
933 vi_d4_pl2 { 933 vi_d4_pl2 {
934 nvidia,pins = 934 nvidia,pins = "vi_d4_pl2";
935 nvidia,functio 935 nvidia,function = "vi";
936 nvidia,pull = 936 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937 nvidia,tristat 937 nvidia,tristate = <TEGRA_PIN_DISABLE>;
938 nvidia,enable- 938 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939 }; 939 };
940 940
941 vi_d6_pl4 { 941 vi_d6_pl4 {
942 nvidia,pins = 942 nvidia,pins = "vi_d6_pl4";
943 nvidia,functio 943 nvidia,function = "vi";
944 nvidia,pull = 944 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945 nvidia,tristat 945 nvidia,tristate = <TEGRA_PIN_DISABLE>;
946 nvidia,enable- 946 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
947 nvidia,lock = 947 nvidia,lock = <0>;
948 nvidia,io-rese 948 nvidia,io-reset = <0>;
949 }; 949 };
950 950
951 vi_mclk_pt1 { 951 vi_mclk_pt1 {
952 nvidia,pins = 952 nvidia,pins = "vi_mclk_pt1";
953 nvidia,functio 953 nvidia,function = "vi";
954 nvidia,pull = 954 nvidia,pull = <TEGRA_PIN_PULL_UP>;
955 nvidia,tristat 955 nvidia,tristate = <TEGRA_PIN_DISABLE>;
956 nvidia,enable- 956 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
957 }; 957 };
958 958
959 jtag_rtck { 959 jtag_rtck {
960 nvidia,pins = 960 nvidia,pins = "jtag_rtck_pu7";
961 nvidia,functio 961 nvidia,function = "rtck";
962 nvidia,pull = 962 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963 nvidia,tristat 963 nvidia,tristate = <TEGRA_PIN_DISABLE>;
964 nvidia,enable- 964 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
965 }; 965 };
966 966
967 crt_hsync_pv6 { 967 crt_hsync_pv6 {
968 nvidia,pins = 968 nvidia,pins = "crt_hsync_pv6",
969 969 "crt_vsync_pv7";
970 nvidia,functio 970 nvidia,function = "crt";
971 nvidia,pull = 971 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972 nvidia,tristat 972 nvidia,tristate = <TEGRA_PIN_ENABLE>;
973 nvidia,enable- 973 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974 }; 974 };
975 975
976 clk1_out { 976 clk1_out {
977 nvidia,pins = 977 nvidia,pins = "clk1_out_pw4";
978 nvidia,functio 978 nvidia,function = "extperiph1";
979 nvidia,pull = 979 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980 nvidia,tristat 980 nvidia,tristate = <TEGRA_PIN_DISABLE>;
981 nvidia,enable- 981 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982 }; 982 };
983 983
984 clk2_out { 984 clk2_out {
985 nvidia,pins = 985 nvidia,pins = "clk2_out_pw5";
986 nvidia,functio 986 nvidia,function = "extperiph2";
987 nvidia,pull = 987 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988 nvidia,tristat 988 nvidia,tristate = <TEGRA_PIN_DISABLE>;
989 nvidia,enable- 989 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
990 }; 990 };
991 991
992 clk3_out { 992 clk3_out {
993 nvidia,pins = 993 nvidia,pins = "clk3_out_pee0";
994 nvidia,functio 994 nvidia,function = "extperiph3";
995 nvidia,pull = 995 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
996 nvidia,tristat 996 nvidia,tristate = <TEGRA_PIN_ENABLE>;
997 nvidia,enable- 997 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
998 }; 998 };
999 999
1000 sys_clk_req { 1000 sys_clk_req {
1001 nvidia,pins = 1001 nvidia,pins = "sys_clk_req_pz5";
1002 nvidia,functi 1002 nvidia,function = "sysclk";
1003 nvidia,pull = 1003 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004 nvidia,trista 1004 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005 nvidia,enable 1005 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006 }; 1006 };
1007 1007
1008 pbb4 { 1008 pbb4 {
1009 nvidia,pins = 1009 nvidia,pins = "pbb4";
1010 nvidia,functi 1010 nvidia,function = "vgp4";
1011 nvidia,pull = 1011 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1012 nvidia,trista 1012 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1013 nvidia,enable 1013 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1014 }; 1014 };
1015 1015
1016 pbb5 { 1016 pbb5 {
1017 nvidia,pins = 1017 nvidia,pins = "pbb5";
1018 nvidia,functi 1018 nvidia,function = "vgp5";
1019 nvidia,pull = 1019 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1020 nvidia,trista 1020 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1021 nvidia,enable 1021 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1022 }; 1022 };
1023 1023
1024 pbb6 { 1024 pbb6 {
1025 nvidia,pins = 1025 nvidia,pins = "pbb6";
1026 nvidia,functi 1026 nvidia,function = "vgp6";
1027 nvidia,pull = 1027 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1028 nvidia,trista 1028 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1029 nvidia,enable 1029 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1030 }; 1030 };
1031 1031
1032 clk2_req_pcc5 { 1032 clk2_req_pcc5 {
1033 nvidia,pins = 1033 nvidia,pins = "clk2_req_pcc5",
1034 1034 "clk1_req_pee2";
1035 nvidia,functi 1035 nvidia,function = "dap";
1036 nvidia,pull = 1036 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1037 nvidia,trista 1037 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1038 nvidia,enable 1038 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1039 }; 1039 };
1040 1040
1041 clk3_req_pee1 { 1041 clk3_req_pee1 {
1042 nvidia,pins = 1042 nvidia,pins = "clk3_req_pee1";
1043 nvidia,functi 1043 nvidia,function = "dev3";
1044 nvidia,pull = 1044 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1045 nvidia,trista 1045 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1046 nvidia,enable 1046 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047 }; 1047 };
1048 1048
1049 owr { 1049 owr {
1050 nvidia,pins = 1050 nvidia,pins = "owr";
1051 nvidia,functi 1051 nvidia,function = "owr";
1052 nvidia,pull = 1052 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1053 nvidia,trista 1053 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1054 nvidia,enable 1054 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1055 }; 1055 };
1056 1056
1057 /* GPIO power/drive c 1057 /* GPIO power/drive control */
1058 drive_dap1 { 1058 drive_dap1 {
1059 nvidia,pins = 1059 nvidia,pins = "drive_dap1",
1060 1060 "drive_dap2",
1061 1061 "drive_dbg",
1062 1062 "drive_at5",
1063 1063 "drive_gme",
1064 1064 "drive_ddc",
1065 1065 "drive_ao1",
1066 1066 "drive_uart3";
1067 nvidia,high-s 1067 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1068 nvidia,schmit 1068 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1069 nvidia,low-po 1069 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1070 nvidia,pull-d 1070 nvidia,pull-down-strength = <31>;
1071 nvidia,pull-u 1071 nvidia,pull-up-strength = <31>;
1072 nvidia,slew-r 1072 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1073 nvidia,slew-r 1073 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1074 }; 1074 };
1075 1075
1076 drive_sdio1 { 1076 drive_sdio1 {
1077 nvidia,pins = 1077 nvidia,pins = "drive_sdio1",
1078 1078 "drive_sdio3";
1079 nvidia,high-s 1079 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1080 nvidia,schmit 1080 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1081 nvidia,pull-d 1081 nvidia,pull-down-strength = <46>;
1082 nvidia,pull-u 1082 nvidia,pull-up-strength = <42>;
1083 nvidia,slew-r 1083 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1084 nvidia,slew-r 1084 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1085 }; 1085 };
1086 }; 1086 };
1087 }; 1087 };
1088 1088
1089 serial@70006040 { 1089 serial@70006040 {
1090 compatible = "nvidia,tegra30- 1090 compatible = "nvidia,tegra30-hsuart";
1091 reset-names = "serial"; 1091 reset-names = "serial";
1092 /delete-property/ reg-shift; 1092 /delete-property/ reg-shift;
1093 status = "okay"; 1093 status = "okay";
1094 1094
1095 /* Broadcom GPS BCM47511 */ 1095 /* Broadcom GPS BCM47511 */
1096 }; 1096 };
1097 1097
1098 serial@70006200 { 1098 serial@70006200 {
1099 compatible = "nvidia,tegra30- 1099 compatible = "nvidia,tegra30-hsuart";
1100 reset-names = "serial"; 1100 reset-names = "serial";
1101 /delete-property/ reg-shift; 1101 /delete-property/ reg-shift;
1102 status = "okay"; 1102 status = "okay";
1103 1103
1104 nvidia,adjust-baud-rates = <0 1104 nvidia,adjust-baud-rates = <0 9600 100>,
1105 <9 1105 <9600 115200 200>,
1106 <1 1106 <1000000 4000000 136>;
1107 1107
1108 bluetooth { 1108 bluetooth {
1109 max-speed = <4000000> 1109 max-speed = <4000000>;
1110 1110
1111 clocks = <&tegra_pmc 1111 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1112 clock-names = "txco"; 1112 clock-names = "txco";
1113 1113
1114 interrupt-parent = <& 1114 interrupt-parent = <&gpio>;
1115 interrupts = <TEGRA_G 1115 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
1116 interrupt-names = "ho 1116 interrupt-names = "host-wakeup";
1117 1117
1118 device-wakeup-gpios = 1118 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
1119 shutdown-gpios = 1119 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
1120 1120
1121 vbat-supply = <&vdd_ 1121 vbat-supply = <&vdd_3v3_com>;
1122 vddio-supply = <&vdd_ 1122 vddio-supply = <&vdd_1v8_vio>;
1123 }; 1123 };
1124 }; 1124 };
1125 1125
1126 pwm@7000a000 { 1126 pwm@7000a000 {
1127 status = "okay"; 1127 status = "okay";
1128 }; 1128 };
1129 1129
1130 lcd_ddc: i2c@7000c000 { 1130 lcd_ddc: i2c@7000c000 {
1131 status = "okay"; 1131 status = "okay";
1132 clock-frequency = <100000>; 1132 clock-frequency = <100000>;
1133 }; 1133 };
1134 1134
1135 i2c@7000c400 { 1135 i2c@7000c400 {
1136 status = "okay"; 1136 status = "okay";
1137 clock-frequency = <400000>; 1137 clock-frequency = <400000>;
1138 }; 1138 };
1139 1139
1140 i2c@7000c500 { 1140 i2c@7000c500 {
1141 status = "okay"; 1141 status = "okay";
1142 1142
1143 /* Aichi AMI306 digital compa 1143 /* Aichi AMI306 digital compass */
1144 magnetometer@e { 1144 magnetometer@e {
1145 compatible = "asahi-k 1145 compatible = "asahi-kasei,ak8974";
1146 reg = <0x0e>; 1146 reg = <0x0e>;
1147 1147
1148 avdd-supply = <&vdd_3 1148 avdd-supply = <&vdd_3v3_sys>;
1149 dvdd-supply = <&vdd_1 1149 dvdd-supply = <&vdd_1v8_vio>;
1150 }; 1150 };
1151 1151
1152 /* Dynaimage ambient light se 1152 /* Dynaimage ambient light sensor */
1153 light-sensor@1c { 1153 light-sensor@1c {
1154 compatible = "dynaima 1154 compatible = "dynaimage,al3010";
1155 reg = <0x1c>; 1155 reg = <0x1c>;
1156 1156
1157 interrupt-parent = <& 1157 interrupt-parent = <&gpio>;
1158 interrupts = <TEGRA_G 1158 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
1159 1159
1160 vdd-supply = <&vdd_3v 1160 vdd-supply = <&vdd_3v3_sys>;
1161 }; 1161 };
1162 1162
1163 gyroscope@68 { 1163 gyroscope@68 {
1164 compatible = "invense 1164 compatible = "invensense,mpu3050";
1165 reg = <0x68>; 1165 reg = <0x68>;
1166 1166
1167 interrupt-parent = <& 1167 interrupt-parent = <&gpio>;
1168 interrupts = <TEGRA_G 1168 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1169 1169
1170 vdd-supply = <&vdd 1170 vdd-supply = <&vdd_3v3_sys>;
1171 vlogic-supply = <&vdd 1171 vlogic-supply = <&vdd_1v8_vio>;
1172 1172
1173 i2c-gate { 1173 i2c-gate {
1174 #address-cell 1174 #address-cells = <1>;
1175 #size-cells = 1175 #size-cells = <0>;
1176 1176
1177 accelerometer 1177 accelerometer@f {
1178 compa 1178 compatible = "kionix,kxtf9";
1179 reg = 1179 reg = <0x0f>;
1180 1180
1181 inter 1181 interrupt-parent = <&gpio>;
1182 inter 1182 interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1183 1183
1184 vdd-s 1184 vdd-supply = <&vdd_1v8_vio>;
1185 vddio 1185 vddio-supply = <&vdd_1v8_vio>;
1186 }; 1186 };
1187 }; 1187 };
1188 }; 1188 };
1189 }; 1189 };
1190 1190
1191 hdmi_ddc: i2c@7000c700 { 1191 hdmi_ddc: i2c@7000c700 {
1192 status = "okay"; 1192 status = "okay";
1193 clock-frequency = <93750>; 1193 clock-frequency = <93750>;
1194 }; 1194 };
1195 1195
1196 i2c@7000d000 { 1196 i2c@7000d000 {
1197 status = "okay"; 1197 status = "okay";
1198 clock-frequency = <400000>; 1198 clock-frequency = <400000>;
1199 1199
1200 /* Texas Instruments TPS65911 1200 /* Texas Instruments TPS659110 PMIC */
1201 pmic: pmic@2d { 1201 pmic: pmic@2d {
1202 compatible = "ti,tps6 1202 compatible = "ti,tps65911";
1203 reg = <0x2d>; 1203 reg = <0x2d>;
1204 1204
1205 interrupts = <GIC_SPI 1205 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1206 #interrupt-cells = <2 1206 #interrupt-cells = <2>;
1207 interrupt-controller; 1207 interrupt-controller;
1208 wakeup-source; 1208 wakeup-source;
1209 1209
1210 ti,en-gpio-sleep = <0 1210 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1211 ti,system-power-contr 1211 ti,system-power-controller;
1212 ti,sleep-keep-ck32k; 1212 ti,sleep-keep-ck32k;
1213 ti,sleep-enable; 1213 ti,sleep-enable;
1214 1214
1215 #gpio-cells = <2>; 1215 #gpio-cells = <2>;
1216 gpio-controller; 1216 gpio-controller;
1217 1217
1218 vcc1-supply = <&vdd_5 1218 vcc1-supply = <&vdd_5v0_bat>;
1219 vcc2-supply = <&vdd_5 1219 vcc2-supply = <&vdd_5v0_bat>;
1220 vcc3-supply = <&vdd_1 1220 vcc3-supply = <&vdd_1v8_vio>;
1221 vcc4-supply = <&vdd_5 1221 vcc4-supply = <&vdd_5v0_sys>;
1222 vcc5-supply = <&vdd_5 1222 vcc5-supply = <&vdd_5v0_bat>;
1223 vcc6-supply = <&vdd_3 1223 vcc6-supply = <&vdd_3v3_sys>;
1224 vcc7-supply = <&vdd_5 1224 vcc7-supply = <&vdd_5v0_bat>;
1225 vccio-supply = <&vdd_ 1225 vccio-supply = <&vdd_5v0_bat>;
1226 1226
1227 pmic-sleep-hog { 1227 pmic-sleep-hog {
1228 gpio-hog; 1228 gpio-hog;
1229 gpios = <2 GP 1229 gpios = <2 GPIO_ACTIVE_HIGH>;
1230 output-high; 1230 output-high;
1231 }; 1231 };
1232 1232
1233 regulators { 1233 regulators {
1234 /* VDD1 is no 1234 /* VDD1 is not used by Transformers */
1235 1235
1236 vddio_ddr: vd 1236 vddio_ddr: vdd2 {
1237 regul 1237 regulator-name = "vddio_ddr";
1238 regul 1238 regulator-min-microvolt = <1200000>;
1239 regul 1239 regulator-max-microvolt = <1200000>;
1240 regul 1240 regulator-always-on;
1241 regul 1241 regulator-boot-on;
1242 }; 1242 };
1243 1243
1244 vdd_cpu: vddc 1244 vdd_cpu: vddctrl {
1245 regul 1245 regulator-name = "vdd_cpu,vdd_sys";
1246 regul 1246 regulator-min-microvolt = <600000>;
1247 regul 1247 regulator-max-microvolt = <1400000>;
1248 regul 1248 regulator-coupled-with = <&vdd_core>;
1249 regul 1249 regulator-coupled-max-spread = <300000>;
1250 regul 1250 regulator-max-step-microvolt = <100000>;
1251 regul 1251 regulator-always-on;
1252 regul 1252 regulator-boot-on;
1253 ti,re 1253 ti,regulator-ext-sleep-control = <1>;
1254 1254
1255 nvidi 1255 nvidia,tegra-cpu-regulator;
1256 }; 1256 };
1257 1257
1258 vdd_1v8_vio: 1258 vdd_1v8_vio: vio {
1259 regul 1259 regulator-name = "vdd_1v8_gen";
1260 /* FI 1260 /* FIXME: eMMC won't work, if set to 1.8 V */
1261 regul 1261 regulator-min-microvolt = <1500000>;
1262 regul 1262 regulator-max-microvolt = <3300000>;
1263 regul 1263 regulator-always-on;
1264 regul 1264 regulator-boot-on;
1265 }; 1265 };
1266 1266
1267 /* eMMC VDD * 1267 /* eMMC VDD */
1268 vcore_emmc: l 1268 vcore_emmc: ldo1 {
1269 regul 1269 regulator-name = "vdd_emmc_core";
1270 regul 1270 regulator-min-microvolt = <3300000>;
1271 regul 1271 regulator-max-microvolt = <3300000>;
1272 regul 1272 regulator-always-on;
1273 }; 1273 };
1274 1274
1275 /* uSD slot V 1275 /* uSD slot VDD */
1276 vdd_usd: ldo2 1276 vdd_usd: ldo2 {
1277 regul 1277 regulator-name = "vdd_usd";
1278 regul 1278 regulator-min-microvolt = <3100000>;
1279 regul 1279 regulator-max-microvolt = <3100000>;
1280 /* FI 1280 /* FIXME: Without this, voltage switching fails */
1281 regul 1281 regulator-always-on;
1282 }; 1282 };
1283 1283
1284 /* uSD slot V 1284 /* uSD slot VDDIO */
1285 vddio_usd: ld 1285 vddio_usd: ldo3 {
1286 regul 1286 regulator-name = "vddio_usd";
1287 regul 1287 regulator-min-microvolt = <1800000>;
1288 regul 1288 regulator-max-microvolt = <3100000>;
1289 }; 1289 };
1290 1290
1291 ldo4 { 1291 ldo4 {
1292 regul 1292 regulator-name = "vdd_rtc";
1293 regul 1293 regulator-min-microvolt = <1200000>;
1294 regul 1294 regulator-max-microvolt = <1200000>;
1295 regul 1295 regulator-always-on;
1296 }; 1296 };
1297 1297
1298 /* LDO5 is no 1298 /* LDO5 is not used by Transformers */
1299 1299
1300 ldo6 { 1300 ldo6 {
1301 regul 1301 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1302 regul 1302 regulator-min-microvolt = <1200000>;
1303 regul 1303 regulator-max-microvolt = <1200000>;
1304 }; 1304 };
1305 1305
1306 ldo7 { 1306 ldo7 {
1307 regul 1307 regulator-name = "vdd_pllm,x,u,a_p_c_s";
1308 regul 1308 regulator-min-microvolt = <1200000>;
1309 regul 1309 regulator-max-microvolt = <1200000>;
1310 regul 1310 regulator-always-on;
1311 regul 1311 regulator-boot-on;
1312 ti,re 1312 ti,regulator-ext-sleep-control = <8>;
1313 }; 1313 };
1314 1314
1315 ldo8 { 1315 ldo8 {
1316 regul 1316 regulator-name = "vdd_ddr_hs";
1317 regul 1317 regulator-min-microvolt = <1000000>;
1318 regul 1318 regulator-max-microvolt = <1000000>;
1319 regul 1319 regulator-always-on;
1320 ti,re 1320 ti,regulator-ext-sleep-control = <8>;
1321 }; 1321 };
1322 }; 1322 };
1323 }; 1323 };
1324 1324
1325 nct72: temperature-sensor@4c 1325 nct72: temperature-sensor@4c {
1326 compatible = "onnn,nc 1326 compatible = "onnn,nct1008";
1327 reg = <0x4c>; 1327 reg = <0x4c>;
1328 1328
1329 interrupt-parent = <& 1329 interrupt-parent = <&gpio>;
1330 interrupts = <TEGRA_G 1330 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1331 1331
1332 vcc-supply = <&vdd_3v 1332 vcc-supply = <&vdd_3v3_sys>;
1333 #thermal-sensor-cells 1333 #thermal-sensor-cells = <1>;
1334 }; 1334 };
1335 1335
1336 vdd_core: core-regulator@60 { 1336 vdd_core: core-regulator@60 {
1337 compatible = "ti,tps6 1337 compatible = "ti,tps62361";
1338 reg = <0x60>; 1338 reg = <0x60>;
1339 1339
1340 regulator-name = "tps 1340 regulator-name = "tps62361-vout";
1341 regulator-min-microvo 1341 regulator-min-microvolt = <500000>;
1342 regulator-max-microvo 1342 regulator-max-microvolt = <1770000>;
1343 regulator-coupled-wit 1343 regulator-coupled-with = <&vdd_cpu>;
1344 regulator-coupled-max 1344 regulator-coupled-max-spread = <300000>;
1345 regulator-max-step-mi 1345 regulator-max-step-microvolt = <100000>;
1346 regulator-boot-on; 1346 regulator-boot-on;
1347 regulator-always-on; 1347 regulator-always-on;
1348 ti,enable-vout-discha 1348 ti,enable-vout-discharge;
1349 ti,vsel0-state-high; 1349 ti,vsel0-state-high;
1350 ti,vsel1-state-high; 1350 ti,vsel1-state-high;
1351 1351
1352 nvidia,tegra-core-reg 1352 nvidia,tegra-core-regulator;
1353 }; 1353 };
1354 }; 1354 };
1355 1355
1356 pmc@7000e400 { 1356 pmc@7000e400 {
1357 status = "okay"; 1357 status = "okay";
1358 nvidia,invert-interrupt; 1358 nvidia,invert-interrupt;
1359 /* FIXME: LP1 doesn't work at 1359 /* FIXME: LP1 doesn't work at the moment */
1360 nvidia,suspend-mode = <2>; 1360 nvidia,suspend-mode = <2>;
1361 nvidia,cpu-pwr-good-time = <2 1361 nvidia,cpu-pwr-good-time = <2000>;
1362 nvidia,cpu-pwr-off-time = <20 1362 nvidia,cpu-pwr-off-time = <200>;
1363 nvidia,core-pwr-good-time = < 1363 nvidia,core-pwr-good-time = <3845 3845>;
1364 nvidia,core-pwr-off-time = <0 1364 nvidia,core-pwr-off-time = <0>;
1365 nvidia,core-power-req-active- 1365 nvidia,core-power-req-active-high;
1366 nvidia,sys-clock-req-active-h 1366 nvidia,sys-clock-req-active-high;
1367 core-supply = <&vdd_core>; 1367 core-supply = <&vdd_core>;
1368 1368
1369 /* Set DEV_OFF + PWR_OFF_SET 1369 /* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC */
1370 i2c-thermtrip { 1370 i2c-thermtrip {
1371 nvidia,i2c-controller 1371 nvidia,i2c-controller-id = <4>;
1372 nvidia,bus-addr = <0x 1372 nvidia,bus-addr = <0x2d>;
1373 nvidia,reg-addr = <0x 1373 nvidia,reg-addr = <0x3f>;
1374 nvidia,reg-data = <0x 1374 nvidia,reg-data = <0x81>;
1375 }; 1375 };
1376 }; 1376 };
1377 1377
1378 hda@70030000 { 1378 hda@70030000 {
1379 status = "okay"; 1379 status = "okay";
1380 }; 1380 };
1381 1381
1382 ahub@70080000 { 1382 ahub@70080000 {
1383 i2s@70080400 { /* i2 1383 i2s@70080400 { /* i2s1 */
1384 status = "okay"; 1384 status = "okay";
1385 }; 1385 };
1386 1386
1387 /* BT SCO */ 1387 /* BT SCO */
1388 i2s@70080600 { /* i2 1388 i2s@70080600 { /* i2s3 */
1389 status = "okay"; 1389 status = "okay";
1390 }; 1390 };
1391 }; 1391 };
1392 1392
1393 mmc@78000000 { 1393 mmc@78000000 {
1394 status = "okay"; 1394 status = "okay";
1395 1395
1396 /* FIXME: Full 208Mhz clock r 1396 /* FIXME: Full 208Mhz clock rate doesn't work reliably */
1397 max-frequency = <104000000>; 1397 max-frequency = <104000000>;
1398 1398
1399 cd-gpios = <&gpio TEGRA_GPIO( 1399 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1400 bus-width = <4>; 1400 bus-width = <4>;
1401 1401
1402 vmmc-supply = <&vdd_usd>; 1402 vmmc-supply = <&vdd_usd>; /* ldo2 */
1403 vqmmc-supply = <&vddio_usd>; 1403 vqmmc-supply = <&vddio_usd>; /* ldo3 */
1404 }; 1404 };
1405 1405
1406 mmc@78000400 { 1406 mmc@78000400 {
1407 status = "okay"; 1407 status = "okay";
1408 1408
1409 #address-cells = <1>; 1409 #address-cells = <1>;
1410 #size-cells = <0>; 1410 #size-cells = <0>;
1411 1411
1412 assigned-clocks = <&tegra_car 1412 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1413 assigned-clock-parents = <&te 1413 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1414 assigned-clock-rates = <50000 1414 assigned-clock-rates = <50000000>;
1415 1415
1416 max-frequency = <50000000>; 1416 max-frequency = <50000000>;
1417 keep-power-in-suspend; 1417 keep-power-in-suspend;
1418 bus-width = <4>; 1418 bus-width = <4>;
1419 non-removable; 1419 non-removable;
1420 1420
1421 mmc-pwrseq = <&brcm_wifi_pwrs 1421 mmc-pwrseq = <&brcm_wifi_pwrseq>;
1422 vmmc-supply = <&vdd_3v3_com>; 1422 vmmc-supply = <&vdd_3v3_com>;
1423 vqmmc-supply = <&vdd_1v8_vio> 1423 vqmmc-supply = <&vdd_1v8_vio>;
1424 1424
1425 /* Azurewave AW-NH615 BCM4329 1425 /* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
1426 wifi@1 { 1426 wifi@1 {
1427 compatible = "brcm,bc 1427 compatible = "brcm,bcm4329-fmac";
1428 reg = <1>; 1428 reg = <1>;
1429 1429
1430 interrupt-parent = <& 1430 interrupt-parent = <&gpio>;
1431 interrupts = <TEGRA_G 1431 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-names = "ho 1432 interrupt-names = "host-wake";
1433 }; 1433 };
1434 }; 1434 };
1435 1435
1436 mmc@78000600 { 1436 mmc@78000600 {
1437 status = "okay"; 1437 status = "okay";
1438 bus-width = <8>; 1438 bus-width = <8>;
1439 vmmc-supply = <&vcore_emmc>; 1439 vmmc-supply = <&vcore_emmc>;
1440 vqmmc-supply = <&vdd_1v8_vio> 1440 vqmmc-supply = <&vdd_1v8_vio>;
1441 mmc-ddr-3_3v; 1441 mmc-ddr-3_3v;
1442 non-removable; 1442 non-removable;
1443 }; 1443 };
1444 1444
1445 /* USB via ASUS connector */ 1445 /* USB via ASUS connector */
1446 usb@7d000000 { 1446 usb@7d000000 {
1447 compatible = "nvidia,tegra30- 1447 compatible = "nvidia,tegra30-udc";
1448 status = "okay"; 1448 status = "okay";
1449 dr_mode = "peripheral"; 1449 dr_mode = "peripheral";
1450 }; 1450 };
1451 1451
1452 usb-phy@7d000000 { 1452 usb-phy@7d000000 {
1453 status = "okay"; 1453 status = "okay";
1454 dr_mode = "peripheral"; 1454 dr_mode = "peripheral";
1455 nvidia,hssync-start-delay = < 1455 nvidia,hssync-start-delay = <0>;
1456 nvidia,xcvr-lsfslew = <2>; 1456 nvidia,xcvr-lsfslew = <2>;
1457 nvidia,xcvr-lsrslew = <2>; 1457 nvidia,xcvr-lsrslew = <2>;
1458 vbus-supply = <&vdd_5v0_sys>; 1458 vbus-supply = <&vdd_5v0_sys>;
1459 }; 1459 };
1460 1460
1461 /* Dock's USB port */ 1461 /* Dock's USB port */
1462 usb@7d008000 { 1462 usb@7d008000 {
1463 status = "okay"; 1463 status = "okay";
1464 }; 1464 };
1465 1465
1466 usb-phy@7d008000 { 1466 usb-phy@7d008000 {
1467 status = "okay"; 1467 status = "okay";
1468 vbus-supply = <&vdd_5v0_bat>; 1468 vbus-supply = <&vdd_5v0_bat>;
1469 }; 1469 };
1470 1470
1471 mains: ac-adapter-detect { 1471 mains: ac-adapter-detect {
1472 compatible = "gpio-charger"; 1472 compatible = "gpio-charger";
1473 charger-type = "mains"; 1473 charger-type = "mains";
1474 gpios = <&gpio TEGRA_GPIO(H, 1474 gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1475 }; 1475 };
1476 1476
1477 backlight: backlight { 1477 backlight: backlight {
1478 compatible = "pwm-backlight"; 1478 compatible = "pwm-backlight";
1479 1479
1480 enable-gpios = <&gpio TEGRA_G 1480 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1481 power-supply = <&vdd_5v0_bl>; 1481 power-supply = <&vdd_5v0_bl>;
1482 pwms = <&pwm 0 4000000>; 1482 pwms = <&pwm 0 4000000>;
1483 1483
1484 brightness-levels = <1 255>; 1484 brightness-levels = <1 255>;
1485 num-interpolated-steps = <254 1485 num-interpolated-steps = <254>;
1486 default-brightness-level = <4 1486 default-brightness-level = <40>;
1487 }; 1487 };
1488 1488
1489 /* PMIC has a built-in 32KHz oscillat 1489 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
1490 clk32k_in: clock-32k { 1490 clk32k_in: clock-32k {
1491 compatible = "fixed-clock"; 1491 compatible = "fixed-clock";
1492 #clock-cells = <0>; 1492 #clock-cells = <0>;
1493 clock-frequency = <32768>; 1493 clock-frequency = <32768>;
1494 clock-output-names = "pmic-os 1494 clock-output-names = "pmic-oscillator";
1495 }; 1495 };
1496 1496
1497 cpus { 1497 cpus {
1498 cpu0: cpu@0 { 1498 cpu0: cpu@0 {
1499 cpu-supply = <&vdd_cp 1499 cpu-supply = <&vdd_cpu>;
1500 operating-points-v2 = 1500 operating-points-v2 = <&cpu0_opp_table>;
1501 #cooling-cells = <2>; 1501 #cooling-cells = <2>;
1502 }; 1502 };
1503 cpu1: cpu@1 { 1503 cpu1: cpu@1 {
1504 cpu-supply = <&vdd_cp 1504 cpu-supply = <&vdd_cpu>;
1505 operating-points-v2 = 1505 operating-points-v2 = <&cpu0_opp_table>;
1506 #cooling-cells = <2>; 1506 #cooling-cells = <2>;
1507 }; 1507 };
1508 cpu2: cpu@2 { 1508 cpu2: cpu@2 {
1509 cpu-supply = <&vdd_cp 1509 cpu-supply = <&vdd_cpu>;
1510 operating-points-v2 = 1510 operating-points-v2 = <&cpu0_opp_table>;
1511 #cooling-cells = <2>; 1511 #cooling-cells = <2>;
1512 }; 1512 };
1513 cpu3: cpu@3 { 1513 cpu3: cpu@3 {
1514 cpu-supply = <&vdd_cp 1514 cpu-supply = <&vdd_cpu>;
1515 operating-points-v2 = 1515 operating-points-v2 = <&cpu0_opp_table>;
1516 #cooling-cells = <2>; 1516 #cooling-cells = <2>;
1517 }; 1517 };
1518 }; 1518 };
1519 1519
1520 extcon-keys { 1520 extcon-keys {
1521 compatible = "gpio-keys"; 1521 compatible = "gpio-keys";
1522 1522
1523 switch-dock-hall-sensor { 1523 switch-dock-hall-sensor {
1524 label = "Lid sensor"; 1524 label = "Lid sensor";
1525 gpios = <&gpio TEGRA_ 1525 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1526 linux,input-type = <E 1526 linux,input-type = <EV_SW>;
1527 linux,code = <SW_LID> 1527 linux,code = <SW_LID>;
1528 debounce-interval = < 1528 debounce-interval = <500>;
1529 wakeup-event-action = 1529 wakeup-event-action = <EV_ACT_ASSERTED>;
1530 wakeup-source; 1530 wakeup-source;
1531 }; 1531 };
1532 1532
1533 switch-lineout-detect { 1533 switch-lineout-detect {
1534 label = "Audio dock l 1534 label = "Audio dock line-out detect";
1535 gpios = <&gpio TEGRA_ 1535 gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
1536 linux,input-type = <E 1536 linux,input-type = <EV_SW>;
1537 linux,code = <SW_LINE 1537 linux,code = <SW_LINEOUT_INSERT>;
1538 debounce-interval = < 1538 debounce-interval = <10>;
1539 wakeup-event-action = 1539 wakeup-event-action = <EV_ACT_ASSERTED>;
1540 wakeup-source; 1540 wakeup-source;
1541 }; 1541 };
1542 }; 1542 };
1543 1543
1544 gpio-keys { 1544 gpio-keys {
1545 compatible = "gpio-keys"; 1545 compatible = "gpio-keys";
1546 1546
1547 key-power { 1547 key-power {
1548 label = "Power"; 1548 label = "Power";
1549 gpios = <&gpio TEGRA_ 1549 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1550 linux,code = <KEY_POW 1550 linux,code = <KEY_POWER>;
1551 debounce-interval = < 1551 debounce-interval = <10>;
1552 wakeup-event-action = 1552 wakeup-event-action = <EV_ACT_ASSERTED>;
1553 wakeup-source; 1553 wakeup-source;
1554 }; 1554 };
1555 1555
1556 key-volume-down { 1556 key-volume-down {
1557 label = "Volume Down" 1557 label = "Volume Down";
1558 gpios = <&gpio TEGRA_ 1558 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1559 linux,code = <KEY_VOL 1559 linux,code = <KEY_VOLUMEDOWN>;
1560 debounce-interval = < 1560 debounce-interval = <10>;
1561 wakeup-event-action = 1561 wakeup-event-action = <EV_ACT_ASSERTED>;
1562 wakeup-source; 1562 wakeup-source;
1563 }; 1563 };
1564 1564
1565 key-volume-up { 1565 key-volume-up {
1566 label = "Volume Up"; 1566 label = "Volume Up";
1567 gpios = <&gpio TEGRA_ 1567 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1568 linux,code = <KEY_VOL 1568 linux,code = <KEY_VOLUMEUP>;
1569 debounce-interval = < 1569 debounce-interval = <10>;
1570 wakeup-event-action = 1570 wakeup-event-action = <EV_ACT_ASSERTED>;
1571 wakeup-source; 1571 wakeup-source;
1572 }; 1572 };
1573 }; 1573 };
1574 1574
1575 vdd_5v0_bat: regulator-bat { 1575 vdd_5v0_bat: regulator-bat {
1576 compatible = "regulator-fixed 1576 compatible = "regulator-fixed";
1577 regulator-name = "vdd_ac_bat" 1577 regulator-name = "vdd_ac_bat";
1578 regulator-min-microvolt = <50 1578 regulator-min-microvolt = <5000000>;
1579 regulator-max-microvolt = <50 1579 regulator-max-microvolt = <5000000>;
1580 regulator-always-on; 1580 regulator-always-on;
1581 regulator-boot-on; 1581 regulator-boot-on;
1582 }; 1582 };
1583 1583
1584 vdd_5v0_cp: regulator-sby { 1584 vdd_5v0_cp: regulator-sby {
1585 compatible = "regulator-fixed 1585 compatible = "regulator-fixed";
1586 regulator-name = "vdd_5v0_sby 1586 regulator-name = "vdd_5v0_sby";
1587 regulator-min-microvolt = <50 1587 regulator-min-microvolt = <5000000>;
1588 regulator-max-microvolt = <50 1588 regulator-max-microvolt = <5000000>;
1589 regulator-always-on; 1589 regulator-always-on;
1590 regulator-boot-on; 1590 regulator-boot-on;
1591 gpio = <&pmic 0 GPIO_ACTIVE_H 1591 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1592 enable-active-high; 1592 enable-active-high;
1593 vin-supply = <&vdd_5v0_bat>; 1593 vin-supply = <&vdd_5v0_bat>;
1594 }; 1594 };
1595 1595
1596 vdd_5v0_sys: regulator-5v { 1596 vdd_5v0_sys: regulator-5v {
1597 compatible = "regulator-fixed 1597 compatible = "regulator-fixed";
1598 regulator-name = "vdd_5v0_sys 1598 regulator-name = "vdd_5v0_sys";
1599 regulator-min-microvolt = <50 1599 regulator-min-microvolt = <5000000>;
1600 regulator-max-microvolt = <50 1600 regulator-max-microvolt = <5000000>;
1601 regulator-always-on; 1601 regulator-always-on;
1602 regulator-boot-on; 1602 regulator-boot-on;
1603 gpio = <&pmic 8 GPIO_ACTIVE_H 1603 gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1604 enable-active-high; 1604 enable-active-high;
1605 vin-supply = <&vdd_5v0_bat>; 1605 vin-supply = <&vdd_5v0_bat>;
1606 }; 1606 };
1607 1607
1608 vdd_1v5_ddr: regulator-ddr { 1608 vdd_1v5_ddr: regulator-ddr {
1609 compatible = "regulator-fixed 1609 compatible = "regulator-fixed";
1610 regulator-name = "vdd_ddr"; 1610 regulator-name = "vdd_ddr";
1611 regulator-min-microvolt = <15 1611 regulator-min-microvolt = <1500000>;
1612 regulator-max-microvolt = <15 1612 regulator-max-microvolt = <1500000>;
1613 regulator-always-on; 1613 regulator-always-on;
1614 regulator-boot-on; 1614 regulator-boot-on;
1615 gpio = <&pmic 7 GPIO_ACTIVE_H 1615 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1616 enable-active-high; 1616 enable-active-high;
1617 vin-supply = <&vdd_5v0_bat>; 1617 vin-supply = <&vdd_5v0_bat>;
1618 }; 1618 };
1619 1619
1620 vdd_3v3_sys: regulator-3v { 1620 vdd_3v3_sys: regulator-3v {
1621 compatible = "regulator-fixed 1621 compatible = "regulator-fixed";
1622 regulator-name = "vdd_3v3_sys 1622 regulator-name = "vdd_3v3_sys";
1623 regulator-min-microvolt = <33 1623 regulator-min-microvolt = <3300000>;
1624 regulator-max-microvolt = <33 1624 regulator-max-microvolt = <3300000>;
1625 regulator-always-on; 1625 regulator-always-on;
1626 regulator-boot-on; 1626 regulator-boot-on;
1627 gpio = <&pmic 6 GPIO_ACTIVE_H 1627 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1628 enable-active-high; 1628 enable-active-high;
1629 vin-supply = <&vdd_5v0_bat>; 1629 vin-supply = <&vdd_5v0_bat>;
1630 }; 1630 };
1631 1631
1632 vdd_pnl: regulator-panel { 1632 vdd_pnl: regulator-panel {
1633 compatible = "regulator-fixed 1633 compatible = "regulator-fixed";
1634 regulator-name = "vdd_panel"; 1634 regulator-name = "vdd_panel";
1635 regulator-min-microvolt = <33 1635 regulator-min-microvolt = <3300000>;
1636 regulator-max-microvolt = <33 1636 regulator-max-microvolt = <3300000>;
1637 regulator-enable-ramp-delay = 1637 regulator-enable-ramp-delay = <20000>;
1638 gpio = <&gpio TEGRA_GPIO(W, 1 1638 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1639 enable-active-high; 1639 enable-active-high;
1640 vin-supply = <&vdd_3v3_sys>; 1640 vin-supply = <&vdd_3v3_sys>;
1641 }; 1641 };
1642 1642
1643 vdd_3v3_com: regulator-com { 1643 vdd_3v3_com: regulator-com {
1644 compatible = "regulator-fixed 1644 compatible = "regulator-fixed";
1645 regulator-name = "vdd_3v3_com 1645 regulator-name = "vdd_3v3_com";
1646 regulator-min-microvolt = <33 1646 regulator-min-microvolt = <3300000>;
1647 regulator-max-microvolt = <33 1647 regulator-max-microvolt = <3300000>;
1648 regulator-always-on; 1648 regulator-always-on;
1649 gpio = <&gpio TEGRA_GPIO(D, 0 1649 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1650 enable-active-high; 1650 enable-active-high;
1651 vin-supply = <&vdd_3v3_sys>; 1651 vin-supply = <&vdd_3v3_sys>;
1652 }; 1652 };
1653 1653
1654 vdd_5v0_bl: regulator-bl { 1654 vdd_5v0_bl: regulator-bl {
1655 compatible = "regulator-fixed 1655 compatible = "regulator-fixed";
1656 regulator-name = "vdd_5v0_bl" 1656 regulator-name = "vdd_5v0_bl";
1657 regulator-min-microvolt = <50 1657 regulator-min-microvolt = <5000000>;
1658 regulator-max-microvolt = <50 1658 regulator-max-microvolt = <5000000>;
1659 regulator-boot-on; 1659 regulator-boot-on;
1660 gpio = <&gpio TEGRA_GPIO(H, 3 1660 gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1661 enable-active-high; 1661 enable-active-high;
1662 vin-supply = <&vdd_5v0_bat>; 1662 vin-supply = <&vdd_5v0_bat>;
1663 }; 1663 };
1664 1664
1665 hdmi_5v0_sys: regulator-hdmi { 1665 hdmi_5v0_sys: regulator-hdmi {
1666 compatible = "regulator-fixed 1666 compatible = "regulator-fixed";
1667 regulator-name = "hdmi_5v0_sy 1667 regulator-name = "hdmi_5v0_sys";
1668 regulator-min-microvolt = <50 1668 regulator-min-microvolt = <5000000>;
1669 regulator-max-microvolt = <50 1669 regulator-max-microvolt = <5000000>;
1670 gpio = <&gpio TEGRA_GPIO(P, 2 1670 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1671 enable-active-high; 1671 enable-active-high;
1672 vin-supply = <&vdd_5v0_sys>; 1672 vin-supply = <&vdd_5v0_sys>;
1673 }; 1673 };
1674 1674
1675 sound { 1675 sound {
1676 nvidia,i2s-controller = <&teg 1676 nvidia,i2s-controller = <&tegra_i2s1>;
1677 1677
1678 nvidia,hp-det-gpios = <&gpio 1678 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1679 nvidia,mic-det-gpios = <&gpio 1679 nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
1680 nvidia,coupled-mic-hp-det; 1680 nvidia,coupled-mic-hp-det;
1681 1681
1682 clocks = <&tegra_car TEGRA30_ 1682 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1683 <&tegra_car TEGRA30_ 1683 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1684 <&tegra_pmc TEGRA_PM 1684 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1685 clock-names = "pll_a", "pll_a 1685 clock-names = "pll_a", "pll_a_out0", "mclk";
1686 1686
1687 assigned-clocks = <&tegra_car 1687 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1688 <&tegra_pmc 1688 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1689 1689
1690 assigned-clock-parents = <&te 1690 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1691 <&te 1691 <&tegra_car TEGRA30_CLK_EXTERN1>;
1692 }; 1692 };
1693 1693
1694 thermal-zones { 1694 thermal-zones {
1695 /* 1695 /*
1696 * NCT72 has two sensors: 1696 * NCT72 has two sensors:
1697 * 1697 *
1698 * 0: internal that moni 1698 * 0: internal that monitors ambient/skin temperature
1699 * 1: external that is c 1699 * 1: external that is connected to the CPU's diode
1700 * 1700 *
1701 * Ideally we should use user 1701 * Ideally we should use userspace thermal governor,
1702 * but it's a much more compl 1702 * but it's a much more complex solution. The "skin"
1703 * zone exists as a simpler s 1703 * zone exists as a simpler solution which prevents
1704 * Transformers from getting 1704 * Transformers from getting too hot from a user's
1705 * tactile perspective. The C 1705 * tactile perspective. The CPU zone is intended to
1706 * protect silicon from damag 1706 * protect silicon from damage.
1707 */ 1707 */
1708 1708
1709 skin-thermal { 1709 skin-thermal {
1710 polling-delay-passive 1710 polling-delay-passive = <1000>; /* milliseconds */
1711 polling-delay = <5000 1711 polling-delay = <5000>; /* milliseconds */
1712 1712
1713 thermal-sensors = <&n 1713 thermal-sensors = <&nct72 0>;
1714 1714
1715 trips { 1715 trips {
1716 trip0: skin-a 1716 trip0: skin-alert {
1717 /* th 1717 /* throttle at 57C until temperature drops to 56.8C */
1718 tempe 1718 temperature = <57000>;
1719 hyste 1719 hysteresis = <200>;
1720 type 1720 type = "passive";
1721 }; 1721 };
1722 1722
1723 trip1: skin-c 1723 trip1: skin-crit {
1724 /* sh 1724 /* shut down at 65C */
1725 tempe 1725 temperature = <65000>;
1726 hyste 1726 hysteresis = <2000>;
1727 type 1727 type = "critical";
1728 }; 1728 };
1729 }; 1729 };
1730 1730
1731 cooling-maps { 1731 cooling-maps {
1732 map0 { 1732 map0 {
1733 trip 1733 trip = <&trip0>;
1734 cooli 1734 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735 1735 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1736 1736 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1737 1737 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1738 1738 <&actmon THERMAL_NO_LIMIT
1739 1739 THERMAL_NO_LIMIT>;
1740 }; 1740 };
1741 }; 1741 };
1742 }; 1742 };
1743 1743
1744 cpu-thermal { 1744 cpu-thermal {
1745 polling-delay-passive 1745 polling-delay-passive = <1000>; /* milliseconds */
1746 polling-delay = <5000 1746 polling-delay = <5000>; /* milliseconds */
1747 1747
1748 thermal-sensors = <&n 1748 thermal-sensors = <&nct72 1>;
1749 1749
1750 trips { 1750 trips {
1751 trip2: cpu-al 1751 trip2: cpu-alert {
1752 /* th 1752 /* throttle at 75C until temperature drops to 74.8C */
1753 tempe 1753 temperature = <75000>;
1754 hyste 1754 hysteresis = <200>;
1755 type 1755 type = "passive";
1756 }; 1756 };
1757 1757
1758 trip3: cpu-cr 1758 trip3: cpu-crit {
1759 /* sh 1759 /* shut down at 90C */
1760 tempe 1760 temperature = <90000>;
1761 hyste 1761 hysteresis = <2000>;
1762 type 1762 type = "critical";
1763 }; 1763 };
1764 }; 1764 };
1765 1765
1766 cooling-maps { 1766 cooling-maps {
1767 map1 { 1767 map1 {
1768 trip 1768 trip = <&trip2>;
1769 cooli 1769 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770 1770 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771 1771 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1772 1772 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1773 1773 <&actmon THERMAL_NO_LIMIT
1774 1774 THERMAL_NO_LIMIT>;
1775 }; 1775 };
1776 }; 1776 };
1777 }; 1777 };
1778 }; 1778 };
1779 1779
1780 brcm_wifi_pwrseq: wifi-pwrseq { 1780 brcm_wifi_pwrseq: wifi-pwrseq {
1781 compatible = "mmc-pwrseq-simp 1781 compatible = "mmc-pwrseq-simple";
1782 1782
1783 clocks = <&tegra_pmc TEGRA_PM 1783 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1784 clock-names = "ext_clock"; 1784 clock-names = "ext_clock";
1785 1785
1786 reset-gpios = <&gpio TEGRA_GP 1786 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1787 post-power-on-delay-ms = <300 1787 post-power-on-delay-ms = <300>;
1788 power-off-delay-us = <300>; 1788 power-off-delay-us = <300>;
1789 }; 1789 };
1790 }; 1790 };
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