1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h> 2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h> 3 #include <dt-bindings/thermal/thermal.h>
4 #include "tegra30.dtsi" 4 #include "tegra30.dtsi"
5 #include "tegra30-cpu-opp.dtsi" 5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi" 6 #include "tegra30-cpu-opp-microvolt.dtsi"
7 7
8 /** 8 /**
9 * This file contains common DT entry for all 9 * This file contains common DT entry for all fab version of Cardhu.
10 * There is multiple fab version of Cardhu sta 10 * There is multiple fab version of Cardhu starting from A01 to A07.
11 * Cardhu fab version A01 and A03 are not supp 11 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
12 * A02 will have different sets of GPIOs for f 12 * A02 will have different sets of GPIOs for fixed regulator compare to
13 * Cardhu fab version A04. The Cardhu fab vers 13 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
14 * compatible with fab version A04. Based on C 14 * compatible with fab version A04. Based on Cardhu fab version, the
15 * related dts file need to be chosen like for 15 * related dts file need to be chosen like for Cardhu fab version A02,
16 * use tegra30-cardhu-a02.dts, Cardhu fab vers 16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts. 17 * tegra30-cardhu-a04.dts.
18 * The identification of board is done in two 18 * The identification of board is done in two ways, by looking the sticker
19 * on PCB and by reading board id eeprom. 19 * on PCB and by reading board id eeprom.
20 * The sticker will have number like 600-81291 20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
21 * number is the fab version like here it is 0 21 * number is the fab version like here it is 002 and hence fab version A02.
22 * The (downstream internal) U-Boot of Cardhu 22 * The (downstream internal) U-Boot of Cardhu display the board-id as
23 * follows: 23 * follows:
24 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45. 24 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
25 * In this Fab version is 02 i.e. A02. 25 * In this Fab version is 02 i.e. A02.
26 * The BoardID I2C eeprom is interfaced throug 26 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
27 * The location 0x8 of this eeprom contains th 27 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
28 * wide. 28 * wide.
29 */ 29 */
30 30
31 / { 31 / {
32 model = "NVIDIA Tegra30 Cardhu evaluat 32 model = "NVIDIA Tegra30 Cardhu evaluation board";
33 compatible = "nvidia,cardhu", "nvidia, 33 compatible = "nvidia,cardhu", "nvidia,tegra30";
34 34
35 aliases { 35 aliases {
36 rtc0 = "/i2c@7000d000/tps65911 36 rtc0 = "/i2c@7000d000/tps65911@2d";
37 rtc1 = "/rtc@7000e000"; 37 rtc1 = "/rtc@7000e000";
38 serial0 = &uarta; 38 serial0 = &uarta;
39 serial1 = &uartc; 39 serial1 = &uartc;
40 }; 40 };
41 41
42 chosen { 42 chosen {
43 stdout-path = "serial0:115200n 43 stdout-path = "serial0:115200n8";
44 }; 44 };
45 45
46 memory@80000000 { 46 memory@80000000 {
47 reg = <0x80000000 0x40000000>; 47 reg = <0x80000000 0x40000000>;
48 }; 48 };
49 49
50 pcie@3000 { 50 pcie@3000 {
51 status = "okay"; 51 status = "okay";
52 52
53 /* AVDD_PEXA and VDD_PEXA inpu 53 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
54 avdd-pexb-supply = <&ldo1_reg> 54 avdd-pexb-supply = <&ldo1_reg>;
55 vdd-pexb-supply = <&ldo1_reg>; 55 vdd-pexb-supply = <&ldo1_reg>;
56 avdd-pex-pll-supply = <&ldo1_r 56 avdd-pex-pll-supply = <&ldo1_reg>;
57 hvdd-pex-supply = <&pex_hvdd_3 57 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
58 vddio-pex-ctl-supply = <&sys_3 58 vddio-pex-ctl-supply = <&sys_3v3_reg>;
59 avdd-plle-supply = <&ldo2_reg> 59 avdd-plle-supply = <&ldo2_reg>;
60 60
61 pci@1,0 { 61 pci@1,0 {
62 nvidia,num-lanes = <4> 62 nvidia,num-lanes = <4>;
63 }; 63 };
64 64
65 pci@2,0 { 65 pci@2,0 {
66 nvidia,num-lanes = <1> 66 nvidia,num-lanes = <1>;
67 }; 67 };
68 68
69 pci@3,0 { 69 pci@3,0 {
70 status = "okay"; 70 status = "okay";
71 nvidia,num-lanes = <1> 71 nvidia,num-lanes = <1>;
72 }; 72 };
73 }; 73 };
74 74
75 host1x@50000000 { 75 host1x@50000000 {
76 dc@54200000 { 76 dc@54200000 {
77 rgb { 77 rgb {
78 status = "okay 78 status = "okay";
79 79
80 nvidia,panel = 80 nvidia,panel = <&panel>;
81 }; 81 };
82 }; 82 };
83 }; 83 };
84 84
85 pinmux@70000868 { 85 pinmux@70000868 {
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&state_default>; 87 pinctrl-0 = <&state_default>;
88 88
89 state_default: pinmux { 89 state_default: pinmux {
90 sdmmc1_clk_pz0 { 90 sdmmc1_clk_pz0 {
91 nvidia,pins = 91 nvidia,pins = "sdmmc1_clk_pz0";
92 nvidia,functio 92 nvidia,function = "sdmmc1";
93 nvidia,pull = 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
94 nvidia,tristat 94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
95 }; 95 };
96 sdmmc1_cmd_pz1 { 96 sdmmc1_cmd_pz1 {
97 nvidia,pins = 97 nvidia,pins = "sdmmc1_cmd_pz1",
98 98 "sdmmc1_dat0_py7",
99 99 "sdmmc1_dat1_py6",
100 100 "sdmmc1_dat2_py5",
101 101 "sdmmc1_dat3_py4";
102 nvidia,functio 102 nvidia,function = "sdmmc1";
103 nvidia,pull = 103 nvidia,pull = <TEGRA_PIN_PULL_UP>;
104 nvidia,tristat 104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
105 }; 105 };
106 sdmmc3_clk_pa6 { 106 sdmmc3_clk_pa6 {
107 nvidia,pins = 107 nvidia,pins = "sdmmc3_clk_pa6";
108 nvidia,functio 108 nvidia,function = "sdmmc3";
109 nvidia,pull = 109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
110 nvidia,tristat 110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
111 }; 111 };
112 sdmmc3_cmd_pa7 { 112 sdmmc3_cmd_pa7 {
113 nvidia,pins = 113 nvidia,pins = "sdmmc3_cmd_pa7",
114 114 "sdmmc3_dat0_pb7",
115 115 "sdmmc3_dat1_pb6",
116 116 "sdmmc3_dat2_pb5",
117 117 "sdmmc3_dat3_pb4";
118 nvidia,functio 118 nvidia,function = "sdmmc3";
119 nvidia,pull = 119 nvidia,pull = <TEGRA_PIN_PULL_UP>;
120 nvidia,tristat 120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 }; 121 };
122 sdmmc4_clk_pcc4 { 122 sdmmc4_clk_pcc4 {
123 nvidia,pins = 123 nvidia,pins = "sdmmc4_clk_pcc4",
124 124 "sdmmc4_rst_n_pcc3";
125 nvidia,functio 125 nvidia,function = "sdmmc4";
126 nvidia,pull = 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristat 127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
128 }; 128 };
129 sdmmc4_dat0_paa0 { 129 sdmmc4_dat0_paa0 {
130 nvidia,pins = 130 nvidia,pins = "sdmmc4_dat0_paa0",
131 131 "sdmmc4_dat1_paa1",
132 132 "sdmmc4_dat2_paa2",
133 133 "sdmmc4_dat3_paa3",
134 134 "sdmmc4_dat4_paa4",
135 135 "sdmmc4_dat5_paa5",
136 136 "sdmmc4_dat6_paa6",
137 137 "sdmmc4_dat7_paa7";
138 nvidia,functio 138 nvidia,function = "sdmmc4";
139 nvidia,pull = 139 nvidia,pull = <TEGRA_PIN_PULL_UP>;
140 nvidia,tristat 140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
141 }; 141 };
142 dap2_fs_pa2 { 142 dap2_fs_pa2 {
143 nvidia,pins = 143 nvidia,pins = "dap2_fs_pa2",
144 144 "dap2_sclk_pa3",
145 145 "dap2_din_pa4",
146 146 "dap2_dout_pa5";
147 nvidia,functio 147 nvidia,function = "i2s1";
148 nvidia,pull = 148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristat 149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 }; 150 };
151 sdio3 { 151 sdio3 {
152 nvidia,pins = 152 nvidia,pins = "drive_sdio3";
153 nvidia,high-sp 153 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
154 nvidia,schmitt 154 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
155 nvidia,pull-do 155 nvidia,pull-down-strength = <46>;
156 nvidia,pull-up 156 nvidia,pull-up-strength = <42>;
157 nvidia,slew-ra 157 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
158 nvidia,slew-ra 158 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
159 }; 159 };
160 uart3_txd_pw6 { 160 uart3_txd_pw6 {
161 nvidia,pins = 161 nvidia,pins = "uart3_txd_pw6",
162 162 "uart3_cts_n_pa1",
163 163 "uart3_rts_n_pc0",
164 164 "uart3_rxd_pw7";
165 nvidia,functio 165 nvidia,function = "uartc";
166 nvidia,pull = 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristat 167 nvidia,tristate = <TEGRA_PIN_DISABLE>;
168 }; 168 };
169 }; 169 };
170 }; 170 };
171 171
172 serial@70006000 { 172 serial@70006000 {
173 /delete-property/ dmas; <<
174 /delete-property/ dma-names; <<
175 status = "okay"; 173 status = "okay";
176 }; 174 };
177 175
178 serial@70006200 { 176 serial@70006200 {
179 compatible = "nvidia,tegra30-h 177 compatible = "nvidia,tegra30-hsuart";
180 reset-names = "serial"; <<
181 /delete-property/ reg-shift; 178 /delete-property/ reg-shift;
182 status = "okay"; 179 status = "okay";
183 }; 180 };
184 181
185 pwm@7000a000 { 182 pwm@7000a000 {
186 status = "okay"; 183 status = "okay";
187 }; 184 };
188 185
189 panelddc: i2c@7000c000 { 186 panelddc: i2c@7000c000 {
190 status = "okay"; 187 status = "okay";
191 clock-frequency = <100000>; 188 clock-frequency = <100000>;
192 }; 189 };
193 190
194 i2c@7000c400 { 191 i2c@7000c400 {
195 status = "okay"; 192 status = "okay";
196 clock-frequency = <100000>; 193 clock-frequency = <100000>;
197 }; 194 };
198 195
199 i2c@7000c500 { 196 i2c@7000c500 {
200 status = "okay"; 197 status = "okay";
201 clock-frequency = <100000>; 198 clock-frequency = <100000>;
202 199
203 /* ALS and Proximity sensor */ 200 /* ALS and Proximity sensor */
204 isl29028@44 { 201 isl29028@44 {
205 compatible = "isil,isl 202 compatible = "isil,isl29028";
206 reg = <0x44>; 203 reg = <0x44>;
207 interrupt-parent = <&g 204 interrupt-parent = <&gpio>;
208 interrupts = <TEGRA_GP 205 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
209 }; 206 };
210 207
211 i2cmux@70 { 208 i2cmux@70 {
212 compatible = "nxp,pca9 209 compatible = "nxp,pca9546";
213 #address-cells = <1>; 210 #address-cells = <1>;
214 #size-cells = <0>; 211 #size-cells = <0>;
215 reg = <0x70>; 212 reg = <0x70>;
216 reset-gpios = <&gpio T 213 reset-gpios = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_LOW>;
217 }; 214 };
218 }; 215 };
219 216
220 i2c@7000c700 { 217 i2c@7000c700 {
221 status = "okay"; 218 status = "okay";
222 clock-frequency = <100000>; 219 clock-frequency = <100000>;
223 }; 220 };
224 221
225 i2c@7000d000 { 222 i2c@7000d000 {
226 status = "okay"; 223 status = "okay";
227 clock-frequency = <100000>; 224 clock-frequency = <100000>;
228 225
229 wm8903: wm8903@1a { 226 wm8903: wm8903@1a {
230 compatible = "wlf,wm89 227 compatible = "wlf,wm8903";
231 reg = <0x1a>; 228 reg = <0x1a>;
232 interrupt-parent = <&g 229 interrupt-parent = <&gpio>;
233 interrupts = <TEGRA_GP 230 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
234 231
235 gpio-controller; 232 gpio-controller;
236 #gpio-cells = <2>; 233 #gpio-cells = <2>;
237 234
238 micdet-cfg = <0>; 235 micdet-cfg = <0>;
239 micdet-delay = <100>; 236 micdet-delay = <100>;
240 gpio-cfg = <0xffffffff 237 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
241 }; 238 };
242 239
243 pmic: tps65911@2d { 240 pmic: tps65911@2d {
244 compatible = "ti,tps65 241 compatible = "ti,tps65911";
245 reg = <0x2d>; 242 reg = <0x2d>;
246 243
247 interrupts = <GIC_SPI 244 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
248 #interrupt-cells = <2> 245 #interrupt-cells = <2>;
249 interrupt-controller; 246 interrupt-controller;
250 wakeup-source; 247 wakeup-source;
251 248
252 ti,system-power-contro 249 ti,system-power-controller;
253 250
254 #gpio-cells = <2>; 251 #gpio-cells = <2>;
255 gpio-controller; 252 gpio-controller;
256 253
257 vcc1-supply = <&vdd_ac 254 vcc1-supply = <&vdd_ac_bat_reg>;
258 vcc2-supply = <&vdd_ac 255 vcc2-supply = <&vdd_ac_bat_reg>;
259 vcc3-supply = <&vio_re 256 vcc3-supply = <&vio_reg>;
260 vcc4-supply = <&vdd_5v 257 vcc4-supply = <&vdd_5v0_reg>;
261 vcc5-supply = <&vdd_ac 258 vcc5-supply = <&vdd_ac_bat_reg>;
262 vcc6-supply = <&vdd2_r 259 vcc6-supply = <&vdd2_reg>;
263 vcc7-supply = <&vdd_ac 260 vcc7-supply = <&vdd_ac_bat_reg>;
264 vccio-supply = <&vdd_a 261 vccio-supply = <&vdd_ac_bat_reg>;
265 262
266 regulators { 263 regulators {
267 vdd1_reg: vdd1 264 vdd1_reg: vdd1 {
268 regula 265 regulator-name = "vddio_ddr_1v2";
269 regula 266 regulator-min-microvolt = <1200000>;
270 regula 267 regulator-max-microvolt = <1200000>;
271 regula 268 regulator-always-on;
272 }; 269 };
273 270
274 vdd2_reg: vdd2 271 vdd2_reg: vdd2 {
275 regula 272 regulator-name = "vdd_1v5_gen";
276 regula 273 regulator-min-microvolt = <1500000>;
277 regula 274 regulator-max-microvolt = <1500000>;
278 regula 275 regulator-always-on;
279 }; 276 };
280 277
281 vddctrl_reg: v 278 vddctrl_reg: vddctrl {
282 regula 279 regulator-name = "vdd_cpu,vdd_sys";
283 regula 280 regulator-min-microvolt = <800000>;
284 regula 281 regulator-max-microvolt = <1250000>;
285 regula 282 regulator-coupled-with = <&vdd_core>;
286 regula 283 regulator-coupled-max-spread = <300000>;
287 regula 284 regulator-max-step-microvolt = <100000>;
288 regula 285 regulator-always-on;
289 286
290 nvidia 287 nvidia,tegra-cpu-regulator;
291 }; 288 };
292 289
293 vio_reg: vio { 290 vio_reg: vio {
294 regula 291 regulator-name = "vdd_1v8_gen";
295 regula 292 regulator-min-microvolt = <1800000>;
296 regula 293 regulator-max-microvolt = <1800000>;
297 regula 294 regulator-always-on;
298 }; 295 };
299 296
300 ldo1_reg: ldo1 297 ldo1_reg: ldo1 {
301 regula 298 regulator-name = "vdd_pexa,vdd_pexb";
302 regula 299 regulator-min-microvolt = <1050000>;
303 regula 300 regulator-max-microvolt = <1050000>;
304 }; 301 };
305 302
306 ldo2_reg: ldo2 303 ldo2_reg: ldo2 {
307 regula 304 regulator-name = "vdd_sata,avdd_plle";
308 regula 305 regulator-min-microvolt = <1050000>;
309 regula 306 regulator-max-microvolt = <1050000>;
310 }; 307 };
311 308
312 /* LDO3 is not 309 /* LDO3 is not connected to anything */
313 310
314 ldo4_reg: ldo4 311 ldo4_reg: ldo4 {
315 regula 312 regulator-name = "vdd_rtc";
316 regula 313 regulator-min-microvolt = <1200000>;
317 regula 314 regulator-max-microvolt = <1200000>;
318 regula 315 regulator-always-on;
319 }; 316 };
320 317
321 ldo5_reg: ldo5 318 ldo5_reg: ldo5 {
322 regula 319 regulator-name = "vddio_sdmmc,avdd_vdac";
323 regula 320 regulator-min-microvolt = <3300000>;
324 regula 321 regulator-max-microvolt = <3300000>;
325 regula 322 regulator-always-on;
326 }; 323 };
327 324
328 ldo6_reg: ldo6 325 ldo6_reg: ldo6 {
329 regula 326 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
330 regula 327 regulator-min-microvolt = <1200000>;
331 regula 328 regulator-max-microvolt = <1200000>;
332 }; 329 };
333 330
334 ldo7_reg: ldo7 331 ldo7_reg: ldo7 {
335 regula 332 regulator-name = "vdd_pllm,x,u,a_p_c_s";
336 regula 333 regulator-min-microvolt = <1200000>;
337 regula 334 regulator-max-microvolt = <1200000>;
338 regula 335 regulator-always-on;
339 }; 336 };
340 337
341 ldo8_reg: ldo8 338 ldo8_reg: ldo8 {
342 regula 339 regulator-name = "vdd_ddr_hs";
343 regula 340 regulator-min-microvolt = <1000000>;
344 regula 341 regulator-max-microvolt = <1000000>;
345 regula 342 regulator-always-on;
346 }; 343 };
347 }; 344 };
348 }; 345 };
349 346
350 nct1008: temperature-sensor@4c 347 nct1008: temperature-sensor@4c {
351 compatible = "onnn,nct 348 compatible = "onnn,nct1008";
352 reg = <0x4c>; 349 reg = <0x4c>;
353 vcc-supply = <&sys_3v3 350 vcc-supply = <&sys_3v3_reg>;
354 interrupt-parent = <&g 351 interrupt-parent = <&gpio>;
355 interrupts = <TEGRA_GP 352 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
356 #thermal-sensor-cells 353 #thermal-sensor-cells = <1>;
357 }; 354 };
358 355
359 vdd_core: tps62361@60 { 356 vdd_core: tps62361@60 {
360 compatible = "ti,tps62 357 compatible = "ti,tps62361";
361 reg = <0x60>; 358 reg = <0x60>;
362 359
363 regulator-name = "tps6 360 regulator-name = "tps62361-vout";
364 regulator-min-microvol 361 regulator-min-microvolt = <500000>;
365 regulator-max-microvol 362 regulator-max-microvolt = <1500000>;
366 regulator-coupled-with 363 regulator-coupled-with = <&vddctrl_reg>;
367 regulator-coupled-max- 364 regulator-coupled-max-spread = <300000>;
368 regulator-max-step-mic 365 regulator-max-step-microvolt = <100000>;
369 regulator-boot-on; 366 regulator-boot-on;
370 regulator-always-on; 367 regulator-always-on;
371 ti,vsel0-state-high; 368 ti,vsel0-state-high;
372 ti,vsel1-state-high; 369 ti,vsel1-state-high;
373 370
374 nvidia,tegra-core-regu 371 nvidia,tegra-core-regulator;
375 }; 372 };
376 }; 373 };
377 374
378 spi@7000da00 { 375 spi@7000da00 {
379 status = "okay"; 376 status = "okay";
380 spi-max-frequency = <25000000> 377 spi-max-frequency = <25000000>;
381 378
382 flash@1 { 379 flash@1 {
383 compatible = "winbond, 380 compatible = "winbond,w25q32", "jedec,spi-nor";
384 reg = <1>; 381 reg = <1>;
385 spi-max-frequency = <2 382 spi-max-frequency = <20000000>;
386 }; 383 };
387 }; 384 };
388 385
389 pmc@7000e400 { 386 pmc@7000e400 {
390 status = "okay"; 387 status = "okay";
391 nvidia,invert-interrupt; 388 nvidia,invert-interrupt;
392 nvidia,suspend-mode = <1>; 389 nvidia,suspend-mode = <1>;
393 nvidia,cpu-pwr-good-time = <20 390 nvidia,cpu-pwr-good-time = <2000>;
394 nvidia,cpu-pwr-off-time = <200 391 nvidia,cpu-pwr-off-time = <200>;
395 nvidia,core-pwr-good-time = <3 392 nvidia,core-pwr-good-time = <3845 3845>;
396 nvidia,core-pwr-off-time = <0> 393 nvidia,core-pwr-off-time = <0>;
397 nvidia,core-power-req-active-h 394 nvidia,core-power-req-active-high;
398 nvidia,sys-clock-req-active-hi 395 nvidia,sys-clock-req-active-high;
399 core-supply = <&vdd_core>; 396 core-supply = <&vdd_core>;
400 }; 397 };
401 398
402 ahub@70080000 { 399 ahub@70080000 {
403 i2s@70080400 { 400 i2s@70080400 {
404 status = "okay"; 401 status = "okay";
405 }; 402 };
406 }; 403 };
407 404
408 mmc@78000000 { 405 mmc@78000000 {
409 status = "okay"; 406 status = "okay";
410 cd-gpios = <&gpio TEGRA_GPIO(I 407 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
411 wp-gpios = <&gpio TEGRA_GPIO(T 408 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
412 power-gpios = <&gpio TEGRA_GPI 409 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
413 bus-width = <4>; 410 bus-width = <4>;
414 }; 411 };
415 412
416 mmc@78000600 { 413 mmc@78000600 {
417 status = "okay"; 414 status = "okay";
418 bus-width = <8>; 415 bus-width = <8>;
419 non-removable; 416 non-removable;
420 }; 417 };
421 418
422 usb@7d008000 { 419 usb@7d008000 {
423 status = "okay"; 420 status = "okay";
424 }; 421 };
425 422
426 usb-phy@7d008000 { 423 usb-phy@7d008000 {
427 vbus-supply = <&usb3_vbus_reg> 424 vbus-supply = <&usb3_vbus_reg>;
428 status = "okay"; 425 status = "okay";
429 }; 426 };
430 427
431 backlight: backlight { 428 backlight: backlight {
432 compatible = "pwm-backlight"; 429 compatible = "pwm-backlight";
433 430
434 enable-gpios = <&gpio TEGRA_GP 431 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
435 power-supply = <&vdd_bl_reg>; 432 power-supply = <&vdd_bl_reg>;
436 pwms = <&pwm 0 5000000>; 433 pwms = <&pwm 0 5000000>;
437 434
438 brightness-levels = <0 4 8 16 435 brightness-levels = <0 4 8 16 32 64 128 255>;
439 default-brightness-level = <6> 436 default-brightness-level = <6>;
440 }; 437 };
441 438
442 clk32k_in: clock-32k { 439 clk32k_in: clock-32k {
443 compatible = "fixed-clock"; 440 compatible = "fixed-clock";
444 clock-frequency = <32768>; 441 clock-frequency = <32768>;
445 #clock-cells = <0>; 442 #clock-cells = <0>;
446 }; 443 };
447 444
448 cpus { 445 cpus {
449 cpu0: cpu@0 { 446 cpu0: cpu@0 {
450 cpu-supply = <&vddctrl 447 cpu-supply = <&vddctrl_reg>;
451 operating-points-v2 = 448 operating-points-v2 = <&cpu0_opp_table>;
452 #cooling-cells = <2>; 449 #cooling-cells = <2>;
453 }; 450 };
454 451
455 cpu1: cpu@1 { 452 cpu1: cpu@1 {
456 cpu-supply = <&vddctrl 453 cpu-supply = <&vddctrl_reg>;
457 operating-points-v2 = 454 operating-points-v2 = <&cpu0_opp_table>;
458 #cooling-cells = <2>; 455 #cooling-cells = <2>;
459 }; 456 };
460 457
461 cpu2: cpu@2 { 458 cpu2: cpu@2 {
462 cpu-supply = <&vddctrl 459 cpu-supply = <&vddctrl_reg>;
463 operating-points-v2 = 460 operating-points-v2 = <&cpu0_opp_table>;
464 #cooling-cells = <2>; 461 #cooling-cells = <2>;
465 }; 462 };
466 463
467 cpu3: cpu@3 { 464 cpu3: cpu@3 {
468 cpu-supply = <&vddctrl 465 cpu-supply = <&vddctrl_reg>;
469 operating-points-v2 = 466 operating-points-v2 = <&cpu0_opp_table>;
470 #cooling-cells = <2>; 467 #cooling-cells = <2>;
471 }; 468 };
472 }; 469 };
473 470
474 gpio-keys { 471 gpio-keys {
475 compatible = "gpio-keys"; 472 compatible = "gpio-keys";
476 473
477 key-power { 474 key-power {
478 label = "Power"; 475 label = "Power";
479 interrupt-parent = <&p 476 interrupt-parent = <&pmic>;
480 interrupts = <2 0>; 477 interrupts = <2 0>;
481 linux,code = <KEY_POWE 478 linux,code = <KEY_POWER>;
482 debounce-interval = <1 479 debounce-interval = <100>;
483 wakeup-source; 480 wakeup-source;
484 }; 481 };
485 482
486 key-volume-down { 483 key-volume-down {
487 label = "Volume Down"; 484 label = "Volume Down";
488 gpios = <&gpio TEGRA_G 485 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
489 linux,code = <KEY_VOLU 486 linux,code = <KEY_VOLUMEDOWN>;
490 debounce-interval = <1 487 debounce-interval = <10>;
491 }; 488 };
492 489
493 key-volume-up { 490 key-volume-up {
494 label = "Volume Up"; 491 label = "Volume Up";
495 gpios = <&gpio TEGRA_G 492 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
496 linux,code = <KEY_VOLU 493 linux,code = <KEY_VOLUMEUP>;
497 debounce-interval = <1 494 debounce-interval = <10>;
498 }; 495 };
499 }; 496 };
500 497
501 panel: panel { 498 panel: panel {
502 compatible = "chunghwa,claa101 499 compatible = "chunghwa,claa101wb01";
503 ddc-i2c-bus = <&panelddc>; 500 ddc-i2c-bus = <&panelddc>;
504 501
505 power-supply = <&vdd_pnl1_reg> 502 power-supply = <&vdd_pnl1_reg>;
506 enable-gpios = <&gpio TEGRA_GP 503 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
507 504
508 backlight = <&backlight>; 505 backlight = <&backlight>;
509 }; 506 };
510 507
511 vdd_ac_bat_reg: regulator-acbat { 508 vdd_ac_bat_reg: regulator-acbat {
512 compatible = "regulator-fixed" 509 compatible = "regulator-fixed";
513 regulator-name = "vdd_ac_bat"; 510 regulator-name = "vdd_ac_bat";
514 regulator-min-microvolt = <500 511 regulator-min-microvolt = <5000000>;
515 regulator-max-microvolt = <500 512 regulator-max-microvolt = <5000000>;
516 regulator-always-on; 513 regulator-always-on;
517 }; 514 };
518 515
519 cam_1v8_reg: regulator-cam { 516 cam_1v8_reg: regulator-cam {
520 compatible = "regulator-fixed" 517 compatible = "regulator-fixed";
521 regulator-name = "cam_1v8"; 518 regulator-name = "cam_1v8";
522 regulator-min-microvolt = <180 519 regulator-min-microvolt = <1800000>;
523 regulator-max-microvolt = <180 520 regulator-max-microvolt = <1800000>;
524 enable-active-high; 521 enable-active-high;
525 gpio = <&gpio TEGRA_GPIO(BB, 4 522 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
526 vin-supply = <&vio_reg>; 523 vin-supply = <&vio_reg>;
527 }; 524 };
528 525
529 cp_5v_reg: regulator-5v0cp { 526 cp_5v_reg: regulator-5v0cp {
530 compatible = "regulator-fixed" 527 compatible = "regulator-fixed";
531 regulator-name = "cp_5v"; 528 regulator-name = "cp_5v";
532 regulator-min-microvolt = <500 529 regulator-min-microvolt = <5000000>;
533 regulator-max-microvolt = <500 530 regulator-max-microvolt = <5000000>;
534 regulator-boot-on; 531 regulator-boot-on;
535 regulator-always-on; 532 regulator-always-on;
536 enable-active-high; 533 enable-active-high;
537 gpio = <&pmic 0 GPIO_ACTIVE_HI 534 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
538 }; 535 };
539 536
540 emmc_3v3_reg: regulator-emmc { 537 emmc_3v3_reg: regulator-emmc {
541 compatible = "regulator-fixed" 538 compatible = "regulator-fixed";
542 regulator-name = "emmc_3v3"; 539 regulator-name = "emmc_3v3";
543 regulator-min-microvolt = <330 540 regulator-min-microvolt = <3300000>;
544 regulator-max-microvolt = <330 541 regulator-max-microvolt = <3300000>;
545 regulator-always-on; 542 regulator-always-on;
546 regulator-boot-on; 543 regulator-boot-on;
547 enable-active-high; 544 enable-active-high;
548 gpio = <&gpio TEGRA_GPIO(D, 1) 545 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
549 vin-supply = <&sys_3v3_reg>; 546 vin-supply = <&sys_3v3_reg>;
550 }; 547 };
551 548
552 modem_3v3_reg: regulator-modem { 549 modem_3v3_reg: regulator-modem {
553 compatible = "regulator-fixed" 550 compatible = "regulator-fixed";
554 regulator-name = "modem_3v3"; 551 regulator-name = "modem_3v3";
555 regulator-min-microvolt = <330 552 regulator-min-microvolt = <3300000>;
556 regulator-max-microvolt = <330 553 regulator-max-microvolt = <3300000>;
557 enable-active-high; 554 enable-active-high;
558 gpio = <&gpio TEGRA_GPIO(D, 6) 555 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
559 }; 556 };
560 557
561 pex_hvdd_3v3_reg: regulator-pex { 558 pex_hvdd_3v3_reg: regulator-pex {
562 compatible = "regulator-fixed" 559 compatible = "regulator-fixed";
563 regulator-name = "pex_hvdd_3v3 560 regulator-name = "pex_hvdd_3v3";
564 regulator-min-microvolt = <330 561 regulator-min-microvolt = <3300000>;
565 regulator-max-microvolt = <330 562 regulator-max-microvolt = <3300000>;
566 enable-active-high; 563 enable-active-high;
567 gpio = <&gpio TEGRA_GPIO(L, 7) 564 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
568 vin-supply = <&sys_3v3_reg>; 565 vin-supply = <&sys_3v3_reg>;
569 }; 566 };
570 567
571 vdd_cam1_ldo_reg: regulator-cam1 { 568 vdd_cam1_ldo_reg: regulator-cam1 {
572 compatible = "regulator-fixed" 569 compatible = "regulator-fixed";
573 regulator-name = "vdd_cam1_ldo 570 regulator-name = "vdd_cam1_ldo";
574 regulator-min-microvolt = <280 571 regulator-min-microvolt = <2800000>;
575 regulator-max-microvolt = <280 572 regulator-max-microvolt = <2800000>;
576 enable-active-high; 573 enable-active-high;
577 gpio = <&gpio TEGRA_GPIO(R, 6) 574 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
578 vin-supply = <&sys_3v3_reg>; 575 vin-supply = <&sys_3v3_reg>;
579 }; 576 };
580 577
581 vdd_cam2_ldo_reg: regulator-cam2 { 578 vdd_cam2_ldo_reg: regulator-cam2 {
582 compatible = "regulator-fixed" 579 compatible = "regulator-fixed";
583 regulator-name = "vdd_cam2_ldo 580 regulator-name = "vdd_cam2_ldo";
584 regulator-min-microvolt = <280 581 regulator-min-microvolt = <2800000>;
585 regulator-max-microvolt = <280 582 regulator-max-microvolt = <2800000>;
586 enable-active-high; 583 enable-active-high;
587 gpio = <&gpio TEGRA_GPIO(R, 7) 584 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
588 vin-supply = <&sys_3v3_reg>; 585 vin-supply = <&sys_3v3_reg>;
589 }; 586 };
590 587
591 vdd_cam3_ldo_reg: regulator-cam3 { 588 vdd_cam3_ldo_reg: regulator-cam3 {
592 compatible = "regulator-fixed" 589 compatible = "regulator-fixed";
593 regulator-name = "vdd_cam3_ldo 590 regulator-name = "vdd_cam3_ldo";
594 regulator-min-microvolt = <330 591 regulator-min-microvolt = <3300000>;
595 regulator-max-microvolt = <330 592 regulator-max-microvolt = <3300000>;
596 enable-active-high; 593 enable-active-high;
597 gpio = <&gpio TEGRA_GPIO(S, 0) 594 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
598 vin-supply = <&sys_3v3_reg>; 595 vin-supply = <&sys_3v3_reg>;
599 }; 596 };
600 597
601 vdd_com_reg: regulator-com { 598 vdd_com_reg: regulator-com {
602 compatible = "regulator-fixed" 599 compatible = "regulator-fixed";
603 regulator-name = "vdd_com"; 600 regulator-name = "vdd_com";
604 regulator-min-microvolt = <330 601 regulator-min-microvolt = <3300000>;
605 regulator-max-microvolt = <330 602 regulator-max-microvolt = <3300000>;
606 regulator-always-on; 603 regulator-always-on;
607 regulator-boot-on; 604 regulator-boot-on;
608 enable-active-high; 605 enable-active-high;
609 gpio = <&gpio TEGRA_GPIO(D, 0) 606 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
610 vin-supply = <&sys_3v3_reg>; 607 vin-supply = <&sys_3v3_reg>;
611 }; 608 };
612 609
613 vdd_fuse_3v3_reg: regulator-fuse { 610 vdd_fuse_3v3_reg: regulator-fuse {
614 compatible = "regulator-fixed" 611 compatible = "regulator-fixed";
615 regulator-name = "vdd_fuse_3v3 612 regulator-name = "vdd_fuse_3v3";
616 regulator-min-microvolt = <330 613 regulator-min-microvolt = <3300000>;
617 regulator-max-microvolt = <330 614 regulator-max-microvolt = <3300000>;
618 enable-active-high; 615 enable-active-high;
619 gpio = <&gpio TEGRA_GPIO(L, 6) 616 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
620 vin-supply = <&sys_3v3_reg>; 617 vin-supply = <&sys_3v3_reg>;
621 }; 618 };
622 619
623 vdd_pnl1_reg: regulator-pnl1 { 620 vdd_pnl1_reg: regulator-pnl1 {
624 compatible = "regulator-fixed" 621 compatible = "regulator-fixed";
625 regulator-name = "vdd_pnl1"; 622 regulator-name = "vdd_pnl1";
626 regulator-min-microvolt = <330 623 regulator-min-microvolt = <3300000>;
627 regulator-max-microvolt = <330 624 regulator-max-microvolt = <3300000>;
628 regulator-always-on; 625 regulator-always-on;
629 regulator-boot-on; 626 regulator-boot-on;
630 enable-active-high; 627 enable-active-high;
631 gpio = <&gpio TEGRA_GPIO(L, 4) 628 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
632 vin-supply = <&sys_3v3_reg>; 629 vin-supply = <&sys_3v3_reg>;
633 }; 630 };
634 631
635 vdd_vid_reg: regulator-vid { 632 vdd_vid_reg: regulator-vid {
636 compatible = "regulator-fixed" 633 compatible = "regulator-fixed";
637 regulator-name = "vddio_vid"; 634 regulator-name = "vddio_vid";
638 regulator-min-microvolt = <500 635 regulator-min-microvolt = <5000000>;
639 regulator-max-microvolt = <500 636 regulator-max-microvolt = <5000000>;
640 enable-active-high; 637 enable-active-high;
641 gpio = <&gpio TEGRA_GPIO(T, 0) 638 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
642 gpio-open-drain; 639 gpio-open-drain;
643 vin-supply = <&vdd_5v0_reg>; 640 vin-supply = <&vdd_5v0_reg>;
644 }; 641 };
645 642
646 sound { 643 sound {
647 compatible = "nvidia,tegra-aud 644 compatible = "nvidia,tegra-audio-wm8903-cardhu",
648 "nvidia,tegra-aud 645 "nvidia,tegra-audio-wm8903";
649 nvidia,model = "NVIDIA Tegra C 646 nvidia,model = "NVIDIA Tegra Cardhu";
650 647
651 nvidia,audio-routing = 648 nvidia,audio-routing =
652 "Headphone Jack", "HPO 649 "Headphone Jack", "HPOUTR",
653 "Headphone Jack", "HPO 650 "Headphone Jack", "HPOUTL",
654 "Int Spk", "ROP", 651 "Int Spk", "ROP",
655 "Int Spk", "RON", 652 "Int Spk", "RON",
656 "Int Spk", "LOP", 653 "Int Spk", "LOP",
657 "Int Spk", "LON", 654 "Int Spk", "LON",
658 "Mic Jack", "MICBIAS", 655 "Mic Jack", "MICBIAS",
659 "IN1L", "Mic Jack"; 656 "IN1L", "Mic Jack";
660 657
661 nvidia,i2s-controller = <&tegr 658 nvidia,i2s-controller = <&tegra_i2s1>;
662 nvidia,audio-codec = <&wm8903> 659 nvidia,audio-codec = <&wm8903>;
663 660
664 nvidia,spkr-en-gpios = <&wm890 661 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
665 nvidia,hp-det-gpios = <&gpio T 662 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
666 GPIO_ACTIVE_LOW>; 663 GPIO_ACTIVE_LOW>;
667 664
668 clocks = <&tegra_car TEGRA30_C 665 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
669 <&tegra_car TEGRA30_C 666 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
670 <&tegra_pmc TEGRA_PMC 667 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
671 clock-names = "pll_a", "pll_a_ 668 clock-names = "pll_a", "pll_a_out0", "mclk";
672 669
673 assigned-clocks = <&tegra_car 670 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
674 <&tegra_pmc 671 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
675 672
676 assigned-clock-parents = <&teg 673 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
677 <&teg 674 <&tegra_car TEGRA30_CLK_EXTERN1>;
678 }; 675 };
679 676
680 thermal-zones { 677 thermal-zones {
681 cpu-thermal { 678 cpu-thermal {
682 polling-delay-passive 679 polling-delay-passive = <1000>; /* milliseconds */
683 polling-delay = <5000> 680 polling-delay = <5000>; /* milliseconds */
684 681
685 thermal-sensors = <&nc 682 thermal-sensors = <&nct1008 1>;
686 683
687 trips { 684 trips {
688 trip0: cpu-ale 685 trip0: cpu-alert0 {
689 /* thr 686 /* throttle at 57C until temperature drops to 56.8C */
690 temper 687 temperature = <57000>;
691 hyster 688 hysteresis = <200>;
692 type = 689 type = "passive";
693 }; 690 };
694 691
695 trip1: cpu-cri 692 trip1: cpu-crit {
696 /* shu 693 /* shut down at 60C */
697 temper 694 temperature = <60000>;
698 hyster 695 hysteresis = <2000>;
699 type = 696 type = "critical";
700 }; 697 };
701 }; 698 };
702 699
703 cooling-maps { 700 cooling-maps {
704 map0 { 701 map0 {
705 trip = 702 trip = <&trip0>;
706 coolin 703 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
707 704 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
708 705 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
709 706 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
710 }; 707 };
711 }; 708 };
712 }; 709 };
713 }; 710 };
714 }; 711 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.