1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
9
10 #include "tegra30-peripherals-opp.dtsi"
11
12 / {
13 compatible = "nvidia,tegra30";
14 interrupt-parent = <&lic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 memory@80000000 {
19 device_type = "memory";
20 reg = <0x80000000 0x0>;
21 };
22
23 pcie@3000 {
24 compatible = "nvidia,tegra30-p
25 device_type = "pci";
26 reg = <0x00003000 0x00000800>,
27 <0x00003800 0x00000200>,
28 <0x10000000 0x10000000>;
29 reg-names = "pads", "afi", "cs
30 interrupts = <GIC_SPI 98 IRQ_T
31 <GIC_SPI 99 IRQ_T
32 interrupt-names = "intr", "msi
33
34 #interrupt-cells = <1>;
35 interrupt-map-mask = <0 0 0 0>
36 interrupt-map = <0 0 0 0 &intc
37
38 bus-range = <0x00 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
41
42 ranges = <0x02000000 0 0x00000
43 <0x02000000 0 0x00001
44 <0x02000000 0 0x00004
45 <0x01000000 0 0
46 <0x02000000 0 0x20000
47 <0x42000000 0 0x28000
48
49 clocks = <&tegra_car TEGRA30_C
50 <&tegra_car TEGRA30_C
51 <&tegra_car TEGRA30_C
52 <&tegra_car TEGRA30_C
53 clock-names = "pex", "afi", "p
54 resets = <&tegra_car 70>,
55 <&tegra_car 72>,
56 <&tegra_car 74>;
57 reset-names = "pex", "afi", "p
58 power-domains = <&pd_core>;
59 operating-points-v2 = <&pcie_d
60 status = "disabled";
61
62 pci@1,0 {
63 device_type = "pci";
64 assigned-addresses = <
65 reg = <0x000800 0 0 0
66 bus-range = <0x00 0xff
67 status = "disabled";
68
69 #address-cells = <3>;
70 #size-cells = <2>;
71 ranges;
72
73 nvidia,num-lanes = <2>
74 };
75
76 pci@2,0 {
77 device_type = "pci";
78 assigned-addresses = <
79 reg = <0x001000 0 0 0
80 bus-range = <0x00 0xff
81 status = "disabled";
82
83 #address-cells = <3>;
84 #size-cells = <2>;
85 ranges;
86
87 nvidia,num-lanes = <2>
88 };
89
90 pci@3,0 {
91 device_type = "pci";
92 assigned-addresses = <
93 reg = <0x001800 0 0 0
94 bus-range = <0x00 0xff
95 status = "disabled";
96
97 #address-cells = <3>;
98 #size-cells = <2>;
99 ranges;
100
101 nvidia,num-lanes = <2>
102 };
103 };
104
105 sram@40000000 {
106 compatible = "mmio-sram";
107 reg = <0x40000000 0x40000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x40000000 0x40000
111
112 vde_pool: sram@400 {
113 reg = <0x400 0x3fc00>;
114 pool;
115 };
116 };
117
118 host1x@50000000 {
119 compatible = "nvidia,tegra30-h
120 reg = <0x50000000 0x00024000>;
121 interrupts = <GIC_SPI 65 IRQ_T
122 <GIC_SPI 67 IRQ_T
123 interrupt-names = "syncpt", "h
124 clocks = <&tegra_car TEGRA30_C
125 clock-names = "host1x";
126 resets = <&tegra_car 28>, <&mc
127 reset-names = "host1x", "mc";
128 iommus = <&mc TEGRA_SWGROUP_HC
129 power-domains = <&pd_heg>;
130 operating-points-v2 = <&host1x
131
132 #address-cells = <1>;
133 #size-cells = <1>;
134
135 ranges = <0x54000000 0x5400000
136
137 mpe@54040000 {
138 compatible = "nvidia,t
139 reg = <0x54040000 0x00
140 interrupts = <GIC_SPI
141 clocks = <&tegra_car T
142 resets = <&tegra_car 6
143 reset-names = "mpe";
144 power-domains = <&pd_m
145 operating-points-v2 =
146
147 iommus = <&mc TEGRA_SW
148
149 status = "disabled";
150 };
151
152 vi@54080000 {
153 compatible = "nvidia,t
154 reg = <0x54080000 0x00
155 interrupts = <GIC_SPI
156 clocks = <&tegra_car T
157 resets = <&tegra_car 2
158 reset-names = "vi";
159 power-domains = <&pd_v
160 operating-points-v2 =
161
162 iommus = <&mc TEGRA_SW
163
164 status = "disabled";
165 };
166
167 epp@540c0000 {
168 compatible = "nvidia,t
169 reg = <0x540c0000 0x00
170 interrupts = <GIC_SPI
171 clocks = <&tegra_car T
172 resets = <&tegra_car 1
173 reset-names = "epp";
174 power-domains = <&pd_h
175 operating-points-v2 =
176
177 iommus = <&mc TEGRA_SW
178
179 status = "disabled";
180 };
181
182 isp@54100000 {
183 compatible = "nvidia,t
184 reg = <0x54100000 0x00
185 interrupts = <GIC_SPI
186 clocks = <&tegra_car T
187 resets = <&tegra_car 2
188 reset-names = "isp";
189 power-domains = <&pd_v
190
191 iommus = <&mc TEGRA_SW
192
193 status = "disabled";
194 };
195
196 gr2d@54140000 {
197 compatible = "nvidia,t
198 reg = <0x54140000 0x00
199 interrupts = <GIC_SPI
200 clocks = <&tegra_car T
201 resets = <&tegra_car 2
202 reset-names = "2d", "m
203 power-domains = <&pd_h
204 operating-points-v2 =
205
206 iommus = <&mc TEGRA_SW
207 };
208
209 gr3d@54180000 {
210 compatible = "nvidia,t
211 reg = <0x54180000 0x00
212 clocks = <&tegra_car T
213 <&tegra_car T
214 clock-names = "3d", "3
215 resets = <&tegra_car 2
216 <&tegra_car 9
217 <&mc TEGRA30_
218 <&mc TEGRA30_
219 reset-names = "3d", "3
220 power-domains = <&pd_3
221 power-domain-names = "
222 operating-points-v2 =
223
224 iommus = <&mc TEGRA_SW
225 <&mc TEGRA_SW
226 };
227
228 dc@54200000 {
229 compatible = "nvidia,t
230 reg = <0x54200000 0x00
231 interrupts = <GIC_SPI
232 clocks = <&tegra_car T
233 <&tegra_car T
234 clock-names = "dc", "p
235 resets = <&tegra_car 2
236 reset-names = "dc";
237 power-domains = <&pd_c
238 operating-points-v2 =
239
240 iommus = <&mc TEGRA_SW
241
242 nvidia,head = <0>;
243
244 interconnects = <&mc T
245 <&mc T
246 <&mc T
247 <&mc T
248 <&mc T
249 interconnect-names = "
250 "
251 "
252 "
253 "
254
255 rgb {
256 status = "disa
257 };
258 };
259
260 dc@54240000 {
261 compatible = "nvidia,t
262 reg = <0x54240000 0x00
263 interrupts = <GIC_SPI
264 clocks = <&tegra_car T
265 <&tegra_car T
266 clock-names = "dc", "p
267 resets = <&tegra_car 2
268 reset-names = "dc";
269 power-domains = <&pd_c
270 operating-points-v2 =
271
272 iommus = <&mc TEGRA_SW
273
274 nvidia,head = <1>;
275
276 interconnects = <&mc T
277 <&mc T
278 <&mc T
279 <&mc T
280 <&mc T
281 interconnect-names = "
282 "
283 "
284 "
285 "
286
287 rgb {
288 status = "disa
289 };
290 };
291
292 hdmi@54280000 {
293 compatible = "nvidia,t
294 reg = <0x54280000 0x00
295 interrupts = <GIC_SPI
296 clocks = <&tegra_car T
297 <&tegra_car T
298 clock-names = "hdmi",
299 resets = <&tegra_car 5
300 reset-names = "hdmi";
301 power-domains = <&pd_c
302 operating-points-v2 =
303 status = "disabled";
304 };
305
306 tvo@542c0000 {
307 compatible = "nvidia,t
308 reg = <0x542c0000 0x00
309 interrupts = <GIC_SPI
310 clocks = <&tegra_car T
311 power-domains = <&pd_c
312 operating-points-v2 =
313 status = "disabled";
314 };
315
316 dsi@54300000 {
317 compatible = "nvidia,t
318 reg = <0x54300000 0x00
319 clocks = <&tegra_car T
320 <&tegra_car T
321 clock-names = "dsi", "
322 resets = <&tegra_car 4
323 reset-names = "dsi";
324 power-domains = <&pd_c
325 operating-points-v2 =
326 status = "disabled";
327 };
328
329 dsi@54400000 {
330 compatible = "nvidia,t
331 reg = <0x54400000 0x00
332 clocks = <&tegra_car T
333 <&tegra_car T
334 clock-names = "dsi", "
335 resets = <&tegra_car 8
336 reset-names = "dsi";
337 power-domains = <&pd_c
338 operating-points-v2 =
339 status = "disabled";
340 };
341 };
342
343 timer@50040600 {
344 compatible = "arm,cortex-a9-tw
345 reg = <0x50040600 0x20>;
346 interrupt-parent = <&intc>;
347 interrupts = <GIC_PPI 13
348 (GIC_CPU_MASK_SIMPLE(4
349 clocks = <&tegra_car TEGRA30_C
350 };
351
352 intc: interrupt-controller@50041000 {
353 compatible = "arm,cortex-a9-gi
354 reg = <0x50041000 0x1000>,
355 <0x50040100 0x0100>;
356 interrupt-controller;
357 #interrupt-cells = <3>;
358 interrupt-parent = <&intc>;
359 };
360
361 cache-controller@50043000 {
362 compatible = "arm,pl310-cache"
363 reg = <0x50043000 0x1000>;
364 arm,data-latency = <6 6 2>;
365 arm,tag-latency = <5 5 2>;
366 cache-unified;
367 cache-level = <2>;
368 };
369
370 lic: interrupt-controller@60004000 {
371 compatible = "nvidia,tegra30-i
372 reg = <0x60004000 0x100>,
373 <0x60004100 0x50>,
374 <0x60004200 0x50>,
375 <0x60004300 0x50>,
376 <0x60004400 0x50>;
377 interrupt-controller;
378 #interrupt-cells = <3>;
379 interrupt-parent = <&intc>;
380 };
381
382 timer@60005000 {
383 compatible = "nvidia,tegra30-t
384 reg = <0x60005000 0x400>;
385 interrupts = <GIC_SPI 0 IRQ_TY
386 <GIC_SPI 1 IRQ_TY
387 <GIC_SPI 41 IRQ_T
388 <GIC_SPI 42 IRQ_T
389 <GIC_SPI 121 IRQ_
390 <GIC_SPI 122 IRQ_
391 clocks = <&tegra_car TEGRA30_C
392 };
393
394 tegra_car: clock@60006000 {
395 compatible = "nvidia,tegra30-c
396 reg = <0x60006000 0x1000>;
397 #clock-cells = <1>;
398 #reset-cells = <1>;
399
400 pll-c {
401 compatible = "nvidia,t
402 clocks = <&tegra_car T
403 power-domains = <&pd_c
404 operating-points-v2 =
405 };
406
407 pll-e {
408 compatible = "nvidia,t
409 clocks = <&tegra_car T
410 power-domains = <&pd_c
411 operating-points-v2 =
412 };
413
414 pll-m {
415 compatible = "nvidia,t
416 clocks = <&tegra_car T
417 power-domains = <&pd_c
418 operating-points-v2 =
419 };
420
421 sclk {
422 compatible = "nvidia,t
423 clocks = <&tegra_car T
424 power-domains = <&pd_c
425 operating-points-v2 =
426 };
427 };
428
429 flow-controller@60007000 {
430 compatible = "nvidia,tegra30-f
431 reg = <0x60007000 0x1000>;
432 };
433
434 apbdma: dma@6000a000 {
435 compatible = "nvidia,tegra30-a
436 reg = <0x6000a000 0x1400>;
437 interrupts = <GIC_SPI 104 IRQ_
438 <GIC_SPI 105 IRQ_
439 <GIC_SPI 106 IRQ_
440 <GIC_SPI 107 IRQ_
441 <GIC_SPI 108 IRQ_
442 <GIC_SPI 109 IRQ_
443 <GIC_SPI 110 IRQ_
444 <GIC_SPI 111 IRQ_
445 <GIC_SPI 112 IRQ_
446 <GIC_SPI 113 IRQ_
447 <GIC_SPI 114 IRQ_
448 <GIC_SPI 115 IRQ_
449 <GIC_SPI 116 IRQ_
450 <GIC_SPI 117 IRQ_
451 <GIC_SPI 118 IRQ_
452 <GIC_SPI 119 IRQ_
453 <GIC_SPI 128 IRQ_
454 <GIC_SPI 129 IRQ_
455 <GIC_SPI 130 IRQ_
456 <GIC_SPI 131 IRQ_
457 <GIC_SPI 132 IRQ_
458 <GIC_SPI 133 IRQ_
459 <GIC_SPI 134 IRQ_
460 <GIC_SPI 135 IRQ_
461 <GIC_SPI 136 IRQ_
462 <GIC_SPI 137 IRQ_
463 <GIC_SPI 138 IRQ_
464 <GIC_SPI 139 IRQ_
465 <GIC_SPI 140 IRQ_
466 <GIC_SPI 141 IRQ_
467 <GIC_SPI 142 IRQ_
468 <GIC_SPI 143 IRQ_
469 clocks = <&tegra_car TEGRA30_C
470 resets = <&tegra_car 34>;
471 reset-names = "dma";
472 #dma-cells = <1>;
473 };
474
475 ahb: ahb@6000c000 {
476 compatible = "nvidia,tegra30-a
477 reg = <0x6000c000 0x150>; /* A
478 };
479
480 actmon: actmon@6000c800 {
481 compatible = "nvidia,tegra30-a
482 reg = <0x6000c800 0x400>;
483 interrupts = <GIC_SPI 45 IRQ_T
484 clocks = <&tegra_car TEGRA30_C
485 <&tegra_car TEGRA30_C
486 clock-names = "actmon", "emc";
487 resets = <&tegra_car TEGRA30_C
488 reset-names = "actmon";
489 operating-points-v2 = <&emc_bw
490 interconnects = <&mc TEGRA30_M
491 interconnect-names = "cpu-read
492 #cooling-cells = <2>;
493 };
494
495 gpio: gpio@6000d000 {
496 compatible = "nvidia,tegra30-g
497 reg = <0x6000d000 0x1000>;
498 interrupts = <GIC_SPI 32 IRQ_T
499 <GIC_SPI 33 IRQ_T
500 <GIC_SPI 34 IRQ_T
501 <GIC_SPI 35 IRQ_T
502 <GIC_SPI 55 IRQ_T
503 <GIC_SPI 87 IRQ_T
504 <GIC_SPI 89 IRQ_T
505 <GIC_SPI 125 IRQ_
506 #gpio-cells = <2>;
507 gpio-controller;
508 #interrupt-cells = <2>;
509 interrupt-controller;
510 gpio-ranges = <&pinmux 0 0 248
511 };
512
513 vde@6001a000 {
514 compatible = "nvidia,tegra30-v
515 reg = <0x6001a000 0x1000>, /*
516 <0x6001b000 0x1000>, /*
517 <0x6001c000 0x100>, /*
518 <0x6001c200 0x100>, /*
519 <0x6001c400 0x100>, /*
520 <0x6001c600 0x100>, /*
521 <0x6001c800 0x100>, /*
522 <0x6001ca00 0x100>, /*
523 <0x6001d800 0x400>; /*
524 reg-names = "sxe", "bsev", "mb
525 "tfe", "ppb", "vdm
526 iram = <&vde_pool>; /* IRAM re
527 interrupts = <GIC_SPI 9 IRQ_T
528 <GIC_SPI 10 IRQ_T
529 <GIC_SPI 12 IRQ_T
530 interrupt-names = "sync-token"
531 clocks = <&tegra_car TEGRA30_C
532 reset-names = "vde", "mc";
533 resets = <&tegra_car 61>, <&mc
534 iommus = <&mc TEGRA_SWGROUP_VD
535 power-domains = <&pd_vde>;
536 operating-points-v2 = <&vde_dv
537 };
538
539 apbmisc@70000800 {
540 compatible = "nvidia,tegra30-a
541 reg = <0x70000800 0x64>, /* Ch
542 <0x70000008 0x04>; /* St
543 };
544
545 pinmux: pinmux@70000868 {
546 compatible = "nvidia,tegra30-p
547 reg = <0x70000868 0x0d4>, /* P
548 <0x70003000 0x3e4>; /* M
549 };
550
551 /*
552 * There are two serial driver i.e. 82
553 * driver and APB DMA based serial dri
554 * and performace. To enable the 8250
555 * is "nvidia,tegra30-uart", "nvidia,t
556 * the APB DMA based serial driver, th
557 * "nvidia,tegra30-hsuart", "nvidia,te
558 */
559 uarta: serial@70006000 {
560 compatible = "nvidia,tegra30-u
561 reg = <0x70006000 0x40>;
562 reg-shift = <2>;
563 interrupts = <GIC_SPI 36 IRQ_T
564 clocks = <&tegra_car TEGRA30_C
565 resets = <&tegra_car 6>;
566 dmas = <&apbdma 8>, <&apbdma 8
567 dma-names = "rx", "tx";
568 status = "disabled";
569 };
570
571 uartb: serial@70006040 {
572 compatible = "nvidia,tegra30-u
573 reg = <0x70006040 0x40>;
574 reg-shift = <2>;
575 interrupts = <GIC_SPI 37 IRQ_T
576 clocks = <&tegra_car TEGRA30_C
577 resets = <&tegra_car 7>;
578 dmas = <&apbdma 9>, <&apbdma 9
579 dma-names = "rx", "tx";
580 status = "disabled";
581 };
582
583 uartc: serial@70006200 {
584 compatible = "nvidia,tegra30-u
585 reg = <0x70006200 0x100>;
586 reg-shift = <2>;
587 interrupts = <GIC_SPI 46 IRQ_T
588 clocks = <&tegra_car TEGRA30_C
589 resets = <&tegra_car 55>;
590 dmas = <&apbdma 10>, <&apbdma
591 dma-names = "rx", "tx";
592 status = "disabled";
593 };
594
595 uartd: serial@70006300 {
596 compatible = "nvidia,tegra30-u
597 reg = <0x70006300 0x100>;
598 reg-shift = <2>;
599 interrupts = <GIC_SPI 90 IRQ_T
600 clocks = <&tegra_car TEGRA30_C
601 resets = <&tegra_car 65>;
602 dmas = <&apbdma 19>, <&apbdma
603 dma-names = "rx", "tx";
604 status = "disabled";
605 };
606
607 uarte: serial@70006400 {
608 compatible = "nvidia,tegra30-u
609 reg = <0x70006400 0x100>;
610 reg-shift = <2>;
611 interrupts = <GIC_SPI 91 IRQ_T
612 clocks = <&tegra_car TEGRA30_C
613 resets = <&tegra_car 66>;
614 dmas = <&apbdma 20>, <&apbdma
615 dma-names = "rx", "tx";
616 status = "disabled";
617 };
618
619 gmi@70009000 {
620 compatible = "nvidia,tegra30-g
621 reg = <0x70009000 0x1000>;
622 #address-cells = <2>;
623 #size-cells = <1>;
624 ranges = <0 0 0x48000000 0x7ff
625 clocks = <&tegra_car TEGRA30_C
626 clock-names = "gmi";
627 resets = <&tegra_car 42>;
628 reset-names = "gmi";
629 power-domains = <&pd_core>;
630 operating-points-v2 = <&nor_dv
631 status = "disabled";
632 };
633
634 pwm: pwm@7000a000 {
635 compatible = "nvidia,tegra30-p
636 reg = <0x7000a000 0x100>;
637 #pwm-cells = <2>;
638 clocks = <&tegra_car TEGRA30_C
639 resets = <&tegra_car 17>;
640 reset-names = "pwm";
641 power-domains = <&pd_core>;
642 operating-points-v2 = <&pwm_dv
643 status = "disabled";
644 };
645
646 i2c@7000c000 {
647 compatible = "nvidia,tegra30-i
648 reg = <0x7000c000 0x100>;
649 interrupts = <GIC_SPI 38 IRQ_T
650 #address-cells = <1>;
651 #size-cells = <0>;
652 clocks = <&tegra_car TEGRA30_C
653 <&tegra_car TEGRA30_C
654 clock-names = "div-clk", "fast
655 resets = <&tegra_car 12>;
656 reset-names = "i2c";
657 dmas = <&apbdma 21>, <&apbdma
658 dma-names = "rx", "tx";
659 status = "disabled";
660 };
661
662 i2c@7000c400 {
663 compatible = "nvidia,tegra30-i
664 reg = <0x7000c400 0x100>;
665 interrupts = <GIC_SPI 84 IRQ_T
666 #address-cells = <1>;
667 #size-cells = <0>;
668 clocks = <&tegra_car TEGRA30_C
669 <&tegra_car TEGRA30_C
670 clock-names = "div-clk", "fast
671 resets = <&tegra_car 54>;
672 reset-names = "i2c";
673 dmas = <&apbdma 22>, <&apbdma
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
677
678 i2c@7000c500 {
679 compatible = "nvidia,tegra30-i
680 reg = <0x7000c500 0x100>;
681 interrupts = <GIC_SPI 92 IRQ_T
682 #address-cells = <1>;
683 #size-cells = <0>;
684 clocks = <&tegra_car TEGRA30_C
685 <&tegra_car TEGRA30_C
686 clock-names = "div-clk", "fast
687 resets = <&tegra_car 67>;
688 reset-names = "i2c";
689 dmas = <&apbdma 23>, <&apbdma
690 dma-names = "rx", "tx";
691 status = "disabled";
692 };
693
694 i2c@7000c700 {
695 compatible = "nvidia,tegra30-i
696 reg = <0x7000c700 0x100>;
697 interrupts = <GIC_SPI 120 IRQ_
698 #address-cells = <1>;
699 #size-cells = <0>;
700 clocks = <&tegra_car TEGRA30_C
701 <&tegra_car TEGRA30_C
702 resets = <&tegra_car 103>;
703 reset-names = "i2c";
704 clock-names = "div-clk", "fast
705 dmas = <&apbdma 26>, <&apbdma
706 dma-names = "rx", "tx";
707 status = "disabled";
708 };
709
710 i2c@7000d000 {
711 compatible = "nvidia,tegra30-i
712 reg = <0x7000d000 0x100>;
713 interrupts = <GIC_SPI 53 IRQ_T
714 #address-cells = <1>;
715 #size-cells = <0>;
716 clocks = <&tegra_car TEGRA30_C
717 <&tegra_car TEGRA30_C
718 clock-names = "div-clk", "fast
719 resets = <&tegra_car 47>;
720 reset-names = "i2c";
721 dmas = <&apbdma 24>, <&apbdma
722 dma-names = "rx", "tx";
723 status = "disabled";
724 };
725
726 spi@7000d400 {
727 compatible = "nvidia,tegra30-s
728 reg = <0x7000d400 0x200>;
729 interrupts = <GIC_SPI 59 IRQ_T
730 #address-cells = <1>;
731 #size-cells = <0>;
732 clocks = <&tegra_car TEGRA30_C
733 resets = <&tegra_car 41>;
734 reset-names = "spi";
735 dmas = <&apbdma 15>, <&apbdma
736 dma-names = "rx", "tx";
737 power-domains = <&pd_core>;
738 operating-points-v2 = <&sbc1_d
739 status = "disabled";
740 };
741
742 spi@7000d600 {
743 compatible = "nvidia,tegra30-s
744 reg = <0x7000d600 0x200>;
745 interrupts = <GIC_SPI 82 IRQ_T
746 #address-cells = <1>;
747 #size-cells = <0>;
748 clocks = <&tegra_car TEGRA30_C
749 resets = <&tegra_car 44>;
750 reset-names = "spi";
751 dmas = <&apbdma 16>, <&apbdma
752 dma-names = "rx", "tx";
753 power-domains = <&pd_core>;
754 operating-points-v2 = <&sbc2_d
755 status = "disabled";
756 };
757
758 spi@7000d800 {
759 compatible = "nvidia,tegra30-s
760 reg = <0x7000d800 0x200>;
761 interrupts = <GIC_SPI 83 IRQ_T
762 #address-cells = <1>;
763 #size-cells = <0>;
764 clocks = <&tegra_car TEGRA30_C
765 resets = <&tegra_car 46>;
766 reset-names = "spi";
767 dmas = <&apbdma 17>, <&apbdma
768 dma-names = "rx", "tx";
769 power-domains = <&pd_core>;
770 operating-points-v2 = <&sbc3_d
771 status = "disabled";
772 };
773
774 spi@7000da00 {
775 compatible = "nvidia,tegra30-s
776 reg = <0x7000da00 0x200>;
777 interrupts = <GIC_SPI 93 IRQ_T
778 #address-cells = <1>;
779 #size-cells = <0>;
780 clocks = <&tegra_car TEGRA30_C
781 resets = <&tegra_car 68>;
782 reset-names = "spi";
783 dmas = <&apbdma 18>, <&apbdma
784 dma-names = "rx", "tx";
785 power-domains = <&pd_core>;
786 operating-points-v2 = <&sbc4_d
787 status = "disabled";
788 };
789
790 spi@7000dc00 {
791 compatible = "nvidia,tegra30-s
792 reg = <0x7000dc00 0x200>;
793 interrupts = <GIC_SPI 94 IRQ_T
794 #address-cells = <1>;
795 #size-cells = <0>;
796 clocks = <&tegra_car TEGRA30_C
797 resets = <&tegra_car 104>;
798 reset-names = "spi";
799 dmas = <&apbdma 27>, <&apbdma
800 dma-names = "rx", "tx";
801 power-domains = <&pd_core>;
802 operating-points-v2 = <&sbc5_d
803 status = "disabled";
804 };
805
806 spi@7000de00 {
807 compatible = "nvidia,tegra30-s
808 reg = <0x7000de00 0x200>;
809 interrupts = <GIC_SPI 79 IRQ_T
810 #address-cells = <1>;
811 #size-cells = <0>;
812 clocks = <&tegra_car TEGRA30_C
813 resets = <&tegra_car 106>;
814 reset-names = "spi";
815 dmas = <&apbdma 28>, <&apbdma
816 dma-names = "rx", "tx";
817 power-domains = <&pd_core>;
818 operating-points-v2 = <&sbc6_d
819 status = "disabled";
820 };
821
822 rtc@7000e000 {
823 compatible = "nvidia,tegra30-r
824 reg = <0x7000e000 0x100>;
825 interrupts = <GIC_SPI 2 IRQ_TY
826 clocks = <&tegra_car TEGRA30_C
827 };
828
829 kbc@7000e200 {
830 compatible = "nvidia,tegra30-k
831 reg = <0x7000e200 0x100>;
832 interrupts = <GIC_SPI 85 IRQ_T
833 clocks = <&tegra_car TEGRA30_C
834 resets = <&tegra_car 36>;
835 reset-names = "kbc";
836 status = "disabled";
837 };
838
839 tegra_pmc: pmc@7000e400 {
840 compatible = "nvidia,tegra30-p
841 reg = <0x7000e400 0x400>;
842 clocks = <&tegra_car TEGRA30_C
843 clock-names = "pclk", "clk32k_
844 #clock-cells = <1>;
845
846 pd_core: core-domain {
847 #power-domain-cells =
848 operating-points-v2 =
849 };
850
851 powergates {
852 pd_heg: heg {
853 clocks = <&teg
854 <&teg
855 <&teg
856 resets = <&mc
857 <&mc
858 <&mc
859 <&teg
860 <&teg
861 <&teg
862 power-domains
863 #power-domain-
864 };
865
866 pd_mpe: mpe {
867 clocks = <&teg
868 resets = <&mc
869 <&teg
870 power-domains
871 #power-domain-
872 };
873
874 pd_3d0: td {
875 clocks = <&teg
876 resets = <&mc
877 <&teg
878 power-domains
879 #power-domain-
880 };
881
882 pd_3d1: td2 {
883 clocks = <&teg
884 resets = <&mc
885 <&teg
886 power-domains
887 #power-domain-
888 };
889
890 pd_vde: vdec {
891 clocks = <&teg
892 resets = <&mc
893 <&teg
894 power-domains
895 #power-domain-
896 };
897
898 pd_venc: venc {
899 clocks = <&teg
900 <&teg
901 <&teg
902 resets = <&mc
903 <&mc
904 <&teg
905 <&teg
906 <&teg
907 power-domains
908 #power-domain-
909 };
910 };
911 };
912
913 mc: memory-controller@7000f000 {
914 compatible = "nvidia,tegra30-m
915 reg = <0x7000f000 0x400>;
916 clocks = <&tegra_car TEGRA30_C
917 clock-names = "mc";
918
919 interrupts = <GIC_SPI 77 IRQ_T
920
921 #iommu-cells = <1>;
922 #reset-cells = <1>;
923 #interconnect-cells = <1>;
924 };
925
926 emc: memory-controller@7000f400 {
927 compatible = "nvidia,tegra30-e
928 reg = <0x7000f400 0x400>;
929 interrupts = <GIC_SPI 78 IRQ_T
930 clocks = <&tegra_car TEGRA30_C
931 power-domains = <&pd_core>;
932
933 nvidia,memory-controller = <&m
934 operating-points-v2 = <&emc_ic
935
936 #interconnect-cells = <0>;
937 };
938
939 fuse@7000f800 {
940 compatible = "nvidia,tegra30-e
941 reg = <0x7000f800 0x400>;
942 clocks = <&tegra_car TEGRA30_C
943 clock-names = "fuse";
944 resets = <&tegra_car 39>;
945 reset-names = "fuse";
946 power-domains = <&pd_core>;
947 operating-points-v2 = <&fuse_b
948 };
949
950 tsensor: tsensor@70014000 {
951 compatible = "nvidia,tegra30-t
952 reg = <0x70014000 0x500>;
953 interrupts = <GIC_SPI 102 IRQ_
954 clocks = <&tegra_car TEGRA30_C
955 resets = <&tegra_car TEGRA30_C
956
957 assigned-clocks = <&tegra_car
958 assigned-clock-parents = <&teg
959 assigned-clock-rates = <500000
960
961 #thermal-sensor-cells = <1>;
962 };
963
964 hda@70030000 {
965 compatible = "nvidia,tegra30-h
966 reg = <0x70030000 0x10000>;
967 interrupts = <GIC_SPI 81 IRQ_T
968 clocks = <&tegra_car TEGRA30_C
969 <&tegra_car TEGRA30_C
970 <&tegra_car TEGRA30_C
971 clock-names = "hda", "hda2hdmi
972 resets = <&tegra_car 125>, /*
973 <&tegra_car 128>, /*
974 <&tegra_car 111>; /*
975 reset-names = "hda", "hda2hdmi
976 status = "disabled";
977 };
978
979 ahub@70080000 {
980 compatible = "nvidia,tegra30-a
981 reg = <0x70080000 0x200>,
982 <0x70080200 0x100>;
983 interrupts = <GIC_SPI 103 IRQ_
984 clocks = <&tegra_car TEGRA30_C
985 <&tegra_car TEGRA30_C
986 clock-names = "d_audio", "apbi
987 resets = <&tegra_car 106>, /*
988 <&tegra_car 107>, /*
989 <&tegra_car 30>, /*
990 <&tegra_car 11>, /*
991 <&tegra_car 18>, /*
992 <&tegra_car 101>, /*
993 <&tegra_car 102>, /*
994 <&tegra_car 108>, /*
995 <&tegra_car 109>, /*
996 <&tegra_car 110>, /*
997 <&tegra_car 10>; /*
998 reset-names = "d_audio", "apbi
999 "i2s3", "i2s4",
1000 "spdif";
1001 dmas = <&apbdma 1>, <&apbdma
1002 <&apbdma 2>, <&apbdma
1003 <&apbdma 3>, <&apbdma
1004 <&apbdma 4>, <&apbdma
1005 dma-names = "rx0", "tx0", "rx
1006 "rx3", "tx3";
1007 ranges;
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1010
1011 tegra_i2s0: i2s@70080300 {
1012 compatible = "nvidia,
1013 reg = <0x70080300 0x1
1014 nvidia,ahub-cif-ids =
1015 clocks = <&tegra_car
1016 resets = <&tegra_car
1017 reset-names = "i2s";
1018 status = "disabled";
1019 };
1020
1021 tegra_i2s1: i2s@70080400 {
1022 compatible = "nvidia,
1023 reg = <0x70080400 0x1
1024 nvidia,ahub-cif-ids =
1025 clocks = <&tegra_car
1026 resets = <&tegra_car
1027 reset-names = "i2s";
1028 status = "disabled";
1029 };
1030
1031 tegra_i2s2: i2s@70080500 {
1032 compatible = "nvidia,
1033 reg = <0x70080500 0x1
1034 nvidia,ahub-cif-ids =
1035 clocks = <&tegra_car
1036 resets = <&tegra_car
1037 reset-names = "i2s";
1038 status = "disabled";
1039 };
1040
1041 tegra_i2s3: i2s@70080600 {
1042 compatible = "nvidia,
1043 reg = <0x70080600 0x1
1044 nvidia,ahub-cif-ids =
1045 clocks = <&tegra_car
1046 resets = <&tegra_car
1047 reset-names = "i2s";
1048 status = "disabled";
1049 };
1050
1051 tegra_i2s4: i2s@70080700 {
1052 compatible = "nvidia,
1053 reg = <0x70080700 0x1
1054 nvidia,ahub-cif-ids =
1055 clocks = <&tegra_car
1056 resets = <&tegra_car
1057 reset-names = "i2s";
1058 status = "disabled";
1059 };
1060 };
1061
1062 mmc@78000000 {
1063 compatible = "nvidia,tegra30-
1064 reg = <0x78000000 0x200>;
1065 interrupts = <GIC_SPI 14 IRQ_
1066 clocks = <&tegra_car TEGRA30_
1067 clock-names = "sdhci";
1068 resets = <&tegra_car 14>;
1069 reset-names = "sdhci";
1070 power-domains = <&pd_core>;
1071 operating-points-v2 = <&sdmmc
1072 status = "disabled";
1073 };
1074
1075 mmc@78000200 {
1076 compatible = "nvidia,tegra30-
1077 reg = <0x78000200 0x200>;
1078 interrupts = <GIC_SPI 15 IRQ_
1079 clocks = <&tegra_car TEGRA30_
1080 clock-names = "sdhci";
1081 resets = <&tegra_car 9>;
1082 reset-names = "sdhci";
1083 status = "disabled";
1084 };
1085
1086 mmc@78000400 {
1087 compatible = "nvidia,tegra30-
1088 reg = <0x78000400 0x200>;
1089 interrupts = <GIC_SPI 19 IRQ_
1090 clocks = <&tegra_car TEGRA30_
1091 clock-names = "sdhci";
1092 resets = <&tegra_car 69>;
1093 reset-names = "sdhci";
1094 power-domains = <&pd_core>;
1095 operating-points-v2 = <&sdmmc
1096 status = "disabled";
1097 };
1098
1099 mmc@78000600 {
1100 compatible = "nvidia,tegra30-
1101 reg = <0x78000600 0x200>;
1102 interrupts = <GIC_SPI 31 IRQ_
1103 clocks = <&tegra_car TEGRA30_
1104 clock-names = "sdhci";
1105 resets = <&tegra_car 15>;
1106 reset-names = "sdhci";
1107 status = "disabled";
1108 };
1109
1110 usb@7d000000 {
1111 compatible = "nvidia,tegra30-
1112 reg = <0x7d000000 0x4000>;
1113 interrupts = <GIC_SPI 20 IRQ_
1114 phy_type = "utmi";
1115 clocks = <&tegra_car TEGRA30_
1116 resets = <&tegra_car 22>;
1117 reset-names = "usb";
1118 nvidia,needs-double-reset;
1119 nvidia,phy = <&phy1>;
1120 power-domains = <&pd_core>;
1121 operating-points-v2 = <&usbd_
1122 status = "disabled";
1123 };
1124
1125 phy1: usb-phy@7d000000 {
1126 compatible = "nvidia,tegra30-
1127 reg = <0x7d000000 0x4000>,
1128 <0x7d000000 0x4000>;
1129 interrupts = <GIC_SPI 20 IRQ_
1130 phy_type = "utmi";
1131 clocks = <&tegra_car TEGRA30_
1132 <&tegra_car TEGRA30_
1133 <&tegra_car TEGRA30_
1134 clock-names = "reg", "pll_u",
1135 resets = <&tegra_car 22>, <&t
1136 reset-names = "usb", "utmi-pa
1137 #phy-cells = <0>;
1138 nvidia,hssync-start-delay = <
1139 nvidia,idle-wait-delay = <17>
1140 nvidia,elastic-limit = <16>;
1141 nvidia,term-range-adj = <6>;
1142 nvidia,xcvr-setup = <51>;
1143 nvidia,xcvr-setup-use-fuses;
1144 nvidia,xcvr-lsfslew = <1>;
1145 nvidia,xcvr-lsrslew = <1>;
1146 nvidia,xcvr-hsslew = <32>;
1147 nvidia,hssquelch-level = <2>;
1148 nvidia,hsdiscon-level = <5>;
1149 nvidia,has-utmi-pad-registers
1150 nvidia,pmc = <&tegra_pmc 0>;
1151 status = "disabled";
1152 };
1153
1154 usb@7d004000 {
1155 compatible = "nvidia,tegra30-
1156 reg = <0x7d004000 0x4000>;
1157 interrupts = <GIC_SPI 21 IRQ_
1158 phy_type = "utmi";
1159 clocks = <&tegra_car TEGRA30_
1160 resets = <&tegra_car 58>;
1161 reset-names = "usb";
1162 nvidia,phy = <&phy2>;
1163 power-domains = <&pd_core>;
1164 operating-points-v2 = <&usb2_
1165 status = "disabled";
1166 };
1167
1168 phy2: usb-phy@7d004000 {
1169 compatible = "nvidia,tegra30-
1170 reg = <0x7d004000 0x4000>,
1171 <0x7d000000 0x4000>;
1172 interrupts = <GIC_SPI 21 IRQ_
1173 phy_type = "utmi";
1174 clocks = <&tegra_car TEGRA30_
1175 <&tegra_car TEGRA30_
1176 <&tegra_car TEGRA30_
1177 clock-names = "reg", "pll_u",
1178 resets = <&tegra_car 58>, <&t
1179 reset-names = "usb", "utmi-pa
1180 #phy-cells = <0>;
1181 nvidia,hssync-start-delay = <
1182 nvidia,idle-wait-delay = <17>
1183 nvidia,elastic-limit = <16>;
1184 nvidia,term-range-adj = <6>;
1185 nvidia,xcvr-setup = <51>;
1186 nvidia,xcvr-setup-use-fuses;
1187 nvidia,xcvr-lsfslew = <2>;
1188 nvidia,xcvr-lsrslew = <2>;
1189 nvidia,xcvr-hsslew = <32>;
1190 nvidia,hssquelch-level = <2>;
1191 nvidia,hsdiscon-level = <5>;
1192 nvidia,pmc = <&tegra_pmc 2>;
1193 status = "disabled";
1194 };
1195
1196 usb@7d008000 {
1197 compatible = "nvidia,tegra30-
1198 reg = <0x7d008000 0x4000>;
1199 interrupts = <GIC_SPI 97 IRQ_
1200 phy_type = "utmi";
1201 clocks = <&tegra_car TEGRA30_
1202 resets = <&tegra_car 59>;
1203 reset-names = "usb";
1204 nvidia,phy = <&phy3>;
1205 power-domains = <&pd_core>;
1206 operating-points-v2 = <&usb3_
1207 status = "disabled";
1208 };
1209
1210 phy3: usb-phy@7d008000 {
1211 compatible = "nvidia,tegra30-
1212 reg = <0x7d008000 0x4000>,
1213 <0x7d000000 0x4000>;
1214 interrupts = <GIC_SPI 97 IRQ_
1215 phy_type = "utmi";
1216 clocks = <&tegra_car TEGRA30_
1217 <&tegra_car TEGRA30_
1218 <&tegra_car TEGRA30_
1219 clock-names = "reg", "pll_u",
1220 resets = <&tegra_car 59>, <&t
1221 reset-names = "usb", "utmi-pa
1222 #phy-cells = <0>;
1223 nvidia,hssync-start-delay = <
1224 nvidia,idle-wait-delay = <17>
1225 nvidia,elastic-limit = <16>;
1226 nvidia,term-range-adj = <6>;
1227 nvidia,xcvr-setup = <51>;
1228 nvidia,xcvr-setup-use-fuses;
1229 nvidia,xcvr-lsfslew = <2>;
1230 nvidia,xcvr-lsrslew = <2>;
1231 nvidia,xcvr-hsslew = <32>;
1232 nvidia,hssquelch-level = <2>;
1233 nvidia,hsdiscon-level = <5>;
1234 nvidia,pmc = <&tegra_pmc 1>;
1235 status = "disabled";
1236 };
1237
1238 cpus {
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241
1242 cpu0: cpu@0 {
1243 device_type = "cpu";
1244 compatible = "arm,cor
1245 reg = <0>;
1246 clocks = <&tegra_car
1247 #cooling-cells = <2>;
1248 };
1249
1250 cpu1: cpu@1 {
1251 device_type = "cpu";
1252 compatible = "arm,cor
1253 reg = <1>;
1254 clocks = <&tegra_car
1255 #cooling-cells = <2>;
1256 };
1257
1258 cpu2: cpu@2 {
1259 device_type = "cpu";
1260 compatible = "arm,cor
1261 reg = <2>;
1262 clocks = <&tegra_car
1263 #cooling-cells = <2>;
1264 };
1265
1266 cpu3: cpu@3 {
1267 device_type = "cpu";
1268 compatible = "arm,cor
1269 reg = <3>;
1270 clocks = <&tegra_car
1271 #cooling-cells = <2>;
1272 };
1273 };
1274
1275 pmu {
1276 compatible = "arm,cortex-a9-p
1277 interrupts = <GIC_SPI 144 IRQ
1278 <GIC_SPI 145 IRQ
1279 <GIC_SPI 146 IRQ
1280 <GIC_SPI 147 IRQ
1281 interrupt-affinity = <&cpu0>,
1282 };
1283
1284 thermal-zones {
1285 tsensor0-thermal {
1286 polling-delay-passive
1287 polling-delay = <5000
1288
1289 thermal-sensors = <&t
1290
1291 trips {
1292 level1_trip:
1293 /* th
1294 tempe
1295 hyste
1296 type
1297 };
1298
1299 level2_trip:
1300 /* ha
1301 tempe
1302 hyste
1303 type
1304 };
1305
1306 level3_trip:
1307 /* ha
1308 tempe
1309 hyste
1310 type
1311 };
1312 };
1313
1314 cooling-maps {
1315 map0 {
1316 trip
1317 cooli
1318
1319
1320
1321
1322 };
1323 };
1324 };
1325
1326 tsensor1-thermal {
1327 status = "disabled";
1328
1329 polling-delay-passive
1330 polling-delay = <0>;
1331
1332 thermal-sensors = <&t
1333
1334 trips {
1335 dvfs-alert {
1336 tempe
1337 hyste
1338 type
1339 };
1340 };
1341 };
1342 };
1343 };
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