1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 // 2 //
3 // Copyright (C) 2014 Alexander Shiyan <shc_wor 3 // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
4 4
5 #include "imx1-pinfunc.h" 5 #include "imx1-pinfunc.h"
6 6
7 #include <dt-bindings/clock/imx1-clock.h> 7 #include <dt-bindings/clock/imx1-clock.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 /* 14 /*
15 * The decompressor and also some boot 15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be ava 16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS 17 * command line and merge other ATAGS info.
18 */ 18 */
19 chosen {}; 19 chosen {};
20 20
21 aliases { 21 aliases {
22 gpio0 = &gpio1; 22 gpio0 = &gpio1;
23 gpio1 = &gpio2; 23 gpio1 = &gpio2;
24 gpio2 = &gpio3; 24 gpio2 = &gpio3;
25 gpio3 = &gpio4; 25 gpio3 = &gpio4;
26 i2c0 = &i2c; 26 i2c0 = &i2c;
27 serial0 = &uart1; 27 serial0 = &uart1;
28 serial1 = &uart2; 28 serial1 = &uart2;
29 serial2 = &uart3; 29 serial2 = &uart3;
30 spi0 = &cspi1; 30 spi0 = &cspi1;
31 spi1 = &cspi2; 31 spi1 = &cspi2;
32 }; 32 };
33 33
34 aitc: aitc-interrupt-controller@223000 34 aitc: aitc-interrupt-controller@223000 {
35 compatible = "fsl,imx1-aitc", 35 compatible = "fsl,imx1-aitc", "fsl,avic";
36 interrupt-controller; 36 interrupt-controller;
37 #interrupt-cells = <1>; 37 #interrupt-cells = <1>;
38 reg = <0x00223000 0x1000>; 38 reg = <0x00223000 0x1000>;
39 }; 39 };
40 40
41 cpus { 41 cpus {
42 #size-cells = <0>; 42 #size-cells = <0>;
43 #address-cells = <1>; 43 #address-cells = <1>;
44 44
45 cpu@0 { 45 cpu@0 {
46 device_type = "cpu"; 46 device_type = "cpu";
47 reg = <0>; 47 reg = <0>;
48 compatible = "arm,arm9 48 compatible = "arm,arm920t";
49 operating-points = <20 49 operating-points = <200000 1900000>;
50 clock-latency = <62500 50 clock-latency = <62500>;
51 clocks = <&clks IMX1_C 51 clocks = <&clks IMX1_CLK_MCU>;
52 voltage-tolerance = <5 52 voltage-tolerance = <5>;
53 }; 53 };
54 }; 54 };
55 55
56 clocks { 56 clocks {
57 clk32 { 57 clk32 {
58 compatible = "fixed-cl 58 compatible = "fixed-clock";
59 #clock-cells = <0>; 59 #clock-cells = <0>;
60 clock-frequency = <320 60 clock-frequency = <32000>;
61 }; 61 };
62 }; 62 };
63 63
64 soc { 64 soc {
65 #address-cells = <1>; 65 #address-cells = <1>;
66 #size-cells = <1>; 66 #size-cells = <1>;
67 compatible = "simple-bus"; 67 compatible = "simple-bus";
68 interrupt-parent = <&aitc>; 68 interrupt-parent = <&aitc>;
69 ranges; 69 ranges;
70 70
71 bus@200000 { 71 bus@200000 {
72 compatible = "fsl,aipi 72 compatible = "fsl,aipi-bus", "simple-bus";
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <1>; 74 #size-cells = <1>;
75 reg = <0x00200000 0x10 75 reg = <0x00200000 0x10000>;
76 ranges; 76 ranges;
77 77
78 gpt1: timer@202000 { 78 gpt1: timer@202000 {
79 compatible = " 79 compatible = "fsl,imx1-gpt";
80 reg = <0x00202 80 reg = <0x00202000 0x1000>;
81 interrupts = < 81 interrupts = <59>;
82 clocks = <&clk 82 clocks = <&clks IMX1_CLK_HCLK>,
83 <&clk 83 <&clks IMX1_CLK_PER1>;
84 clock-names = 84 clock-names = "ipg", "per";
85 }; 85 };
86 86
87 gpt2: timer@203000 { 87 gpt2: timer@203000 {
88 compatible = " 88 compatible = "fsl,imx1-gpt";
89 reg = <0x00203 89 reg = <0x00203000 0x1000>;
90 interrupts = < 90 interrupts = <58>;
91 clocks = <&clk 91 clocks = <&clks IMX1_CLK_HCLK>,
92 <&clk 92 <&clks IMX1_CLK_PER1>;
93 clock-names = 93 clock-names = "ipg", "per";
94 }; 94 };
95 95
96 fb: fb@205000 { 96 fb: fb@205000 {
97 compatible = " 97 compatible = "fsl,imx1-fb";
98 reg = <0x00205 98 reg = <0x00205000 0x1000>;
99 interrupts = < 99 interrupts = <14>;
100 clocks = <&clk 100 clocks = <&clks IMX1_CLK_DUMMY>,
101 <&clk 101 <&clks IMX1_CLK_DUMMY>,
102 <&clk 102 <&clks IMX1_CLK_PER2>;
103 clock-names = 103 clock-names = "ipg", "ahb", "per";
104 status = "disa 104 status = "disabled";
105 }; 105 };
106 106
107 uart1: serial@206000 { 107 uart1: serial@206000 {
108 compatible = " 108 compatible = "fsl,imx1-uart";
109 reg = <0x00206 109 reg = <0x00206000 0x1000>;
110 interrupts = < 110 interrupts = <30 29 26>;
111 clocks = <&clk 111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clk 112 <&clks IMX1_CLK_PER1>;
113 clock-names = 113 clock-names = "ipg", "per";
114 status = "disa 114 status = "disabled";
115 }; 115 };
116 116
117 uart2: serial@207000 { 117 uart2: serial@207000 {
118 compatible = " 118 compatible = "fsl,imx1-uart";
119 reg = <0x00207 119 reg = <0x00207000 0x1000>;
120 interrupts = < 120 interrupts = <24 23 20>;
121 clocks = <&clk 121 clocks = <&clks IMX1_CLK_HCLK>,
122 <&clk 122 <&clks IMX1_CLK_PER1>;
123 clock-names = 123 clock-names = "ipg", "per";
124 status = "disa 124 status = "disabled";
125 }; 125 };
126 126
127 pwm: pwm@208000 { 127 pwm: pwm@208000 {
128 #pwm-cells = < 128 #pwm-cells = <3>;
129 compatible = " 129 compatible = "fsl,imx1-pwm";
130 reg = <0x00208 130 reg = <0x00208000 0x1000>;
131 interrupts = < 131 interrupts = <34>;
132 clocks = <&clk 132 clocks = <&clks IMX1_CLK_DUMMY>,
133 <&clk 133 <&clks IMX1_CLK_PER1>;
134 clock-names = 134 clock-names = "ipg", "per";
135 }; 135 };
136 136
137 dma: dma-controller@20 137 dma: dma-controller@209000 {
138 compatible = " 138 compatible = "fsl,imx1-dma";
139 reg = <0x00209 139 reg = <0x00209000 0x1000>;
140 interrupts = < 140 interrupts = <61 60>;
141 clocks = <&clk 141 clocks = <&clks IMX1_CLK_HCLK>,
142 <&clk 142 <&clks IMX1_CLK_DMA_GATE>;
143 clock-names = 143 clock-names = "ipg", "ahb";
144 #dma-cells = < 144 #dma-cells = <1>;
145 }; 145 };
146 146
147 uart3: serial@20a000 { 147 uart3: serial@20a000 {
148 compatible = " 148 compatible = "fsl,imx1-uart";
149 reg = <0x0020a 149 reg = <0x0020a000 0x1000>;
150 interrupts = < 150 interrupts = <54 4 1>;
151 clocks = <&clk 151 clocks = <&clks IMX1_CLK_UART3_GATE>,
152 <&clk 152 <&clks IMX1_CLK_PER1>;
153 clock-names = 153 clock-names = "ipg", "per";
154 status = "disa 154 status = "disabled";
155 }; 155 };
156 }; 156 };
157 157
158 bus@210000 { 158 bus@210000 {
159 compatible = "fsl,aipi 159 compatible = "fsl,aipi-bus", "simple-bus";
160 #address-cells = <1>; 160 #address-cells = <1>;
161 #size-cells = <1>; 161 #size-cells = <1>;
162 reg = <0x00210000 0x10 162 reg = <0x00210000 0x10000>;
163 ranges; 163 ranges;
164 164
165 cspi1: spi@213000 { 165 cspi1: spi@213000 {
166 #address-cells 166 #address-cells = <1>;
167 #size-cells = 167 #size-cells = <0>;
168 compatible = " 168 compatible = "fsl,imx1-cspi";
169 reg = <0x00213 169 reg = <0x00213000 0x1000>;
170 interrupts = < 170 interrupts = <41>;
171 clocks = <&clk 171 clocks = <&clks IMX1_CLK_DUMMY>,
172 <&clk 172 <&clks IMX1_CLK_PER1>;
173 clock-names = 173 clock-names = "ipg", "per";
174 status = "disa 174 status = "disabled";
175 }; 175 };
176 176
177 i2c: i2c@217000 { 177 i2c: i2c@217000 {
178 #address-cells 178 #address-cells = <1>;
179 #size-cells = 179 #size-cells = <0>;
180 compatible = " 180 compatible = "fsl,imx1-i2c";
181 reg = <0x00217 181 reg = <0x00217000 0x1000>;
182 interrupts = < 182 interrupts = <39>;
183 clocks = <&clk 183 clocks = <&clks IMX1_CLK_HCLK>;
184 status = "disa 184 status = "disabled";
185 }; 185 };
186 186
187 cspi2: spi@219000 { 187 cspi2: spi@219000 {
188 #address-cells 188 #address-cells = <1>;
189 #size-cells = 189 #size-cells = <0>;
190 compatible = " 190 compatible = "fsl,imx1-cspi";
191 reg = <0x00219 191 reg = <0x00219000 0x1000>;
192 interrupts = < 192 interrupts = <40>;
193 clocks = <&clk 193 clocks = <&clks IMX1_CLK_DUMMY>,
194 <&clk 194 <&clks IMX1_CLK_PER1>;
195 clock-names = 195 clock-names = "ipg", "per";
196 status = "disa 196 status = "disabled";
197 }; 197 };
198 198
199 clks: ccm@21b000 { 199 clks: ccm@21b000 {
200 compatible = " 200 compatible = "fsl,imx1-ccm";
201 reg = <0x0021b 201 reg = <0x0021b000 0x1000>;
202 #clock-cells = 202 #clock-cells = <1>;
203 }; 203 };
204 204
205 iomuxc: iomuxc@21c000 205 iomuxc: iomuxc@21c000 {
206 compatible = " 206 compatible = "fsl,imx1-iomuxc";
207 reg = <0x0021c 207 reg = <0x0021c000 0x1000>;
208 #address-cells 208 #address-cells = <1>;
209 #size-cells = 209 #size-cells = <1>;
210 ranges; 210 ranges;
211 211
212 gpio1: gpio@21 212 gpio1: gpio@21c000 {
213 compat 213 compatible = "fsl,imx1-gpio";
214 reg = 214 reg = <0x0021c000 0x100>;
215 interr 215 interrupts = <11>;
216 gpio-c 216 gpio-controller;
217 #gpio- 217 #gpio-cells = <2>;
218 interr 218 interrupt-controller;
219 #inter 219 #interrupt-cells = <2>;
220 }; 220 };
221 221
222 gpio2: gpio@21 222 gpio2: gpio@21c100 {
223 compat 223 compatible = "fsl,imx1-gpio";
224 reg = 224 reg = <0x0021c100 0x100>;
225 interr 225 interrupts = <12>;
226 gpio-c 226 gpio-controller;
227 #gpio- 227 #gpio-cells = <2>;
228 interr 228 interrupt-controller;
229 #inter 229 #interrupt-cells = <2>;
230 }; 230 };
231 231
232 gpio3: gpio@21 232 gpio3: gpio@21c200 {
233 compat 233 compatible = "fsl,imx1-gpio";
234 reg = 234 reg = <0x0021c200 0x100>;
235 interr 235 interrupts = <13>;
236 gpio-c 236 gpio-controller;
237 #gpio- 237 #gpio-cells = <2>;
238 interr 238 interrupt-controller;
239 #inter 239 #interrupt-cells = <2>;
240 }; 240 };
241 241
242 gpio4: gpio@21 242 gpio4: gpio@21c300 {
243 compat 243 compatible = "fsl,imx1-gpio";
244 reg = 244 reg = <0x0021c300 0x100>;
245 interr 245 interrupts = <62>;
246 gpio-c 246 gpio-controller;
247 #gpio- 247 #gpio-cells = <2>;
248 interr 248 interrupt-controller;
249 #inter 249 #interrupt-cells = <2>;
250 }; 250 };
251 }; 251 };
252 }; 252 };
253 253
254 weim: memory-controller@220000 254 weim: memory-controller@220000 {
255 #address-cells = <2>; 255 #address-cells = <2>;
256 #size-cells = <1>; 256 #size-cells = <1>;
257 compatible = "fsl,imx1 257 compatible = "fsl,imx1-weim";
258 reg = <0x00220000 0x10 258 reg = <0x00220000 0x1000>;
259 clocks = <&clks IMX1_C 259 clocks = <&clks IMX1_CLK_DUMMY>;
260 ranges = < 260 ranges = <
261 0 0 0x10000000 261 0 0 0x10000000 0x02000000
262 1 0 0x12000000 262 1 0 0x12000000 0x01000000
263 2 0 0x13000000 263 2 0 0x13000000 0x01000000
264 3 0 0x14000000 264 3 0 0x14000000 0x01000000
265 4 0 0x15000000 265 4 0 0x15000000 0x01000000
266 5 0 0x16000000 266 5 0 0x16000000 0x01000000
267 >; 267 >;
268 status = "disabled"; 268 status = "disabled";
269 }; 269 };
270 270
271 esram: sram@300000 { 271 esram: sram@300000 {
272 compatible = "mmio-sra 272 compatible = "mmio-sram";
273 reg = <0x00300000 0x20 273 reg = <0x00300000 0x20000>;
274 ranges = <0 0x00300000 274 ranges = <0 0x00300000 0x20000>;
275 #address-cells = <1>; 275 #address-cells = <1>;
276 #size-cells = <1>; 276 #size-cells = <1>;
277 }; 277 };
278 }; 278 };
279 }; 279 };
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