1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 // 2 //
3 // Copyright 2013 Greg Ungerer <gerg@uclinux.or 3 // Copyright 2013 Greg Ungerer <gerg@uclinux.org>
4 // Copyright 2011 Freescale Semiconductor, Inc 4 // Copyright 2011 Freescale Semiconductor, Inc.
5 // Copyright 2011 Linaro Ltd. 5 // Copyright 2011 Linaro Ltd.
6 6
7 #include "imx50-pinfunc.h" 7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h> 9 #include <dt-bindings/clock/imx5-clock.h>
10 10
11 / { 11 / {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 /* 14 /*
15 * The decompressor and also some boot 15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be ava 16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS 17 * command line and merge other ATAGS info.
18 */ 18 */
19 chosen {}; 19 chosen {};
20 20
21 aliases { 21 aliases {
22 ethernet0 = &fec; 22 ethernet0 = &fec;
23 gpio0 = &gpio1; 23 gpio0 = &gpio1;
24 gpio1 = &gpio2; 24 gpio1 = &gpio2;
25 gpio2 = &gpio3; 25 gpio2 = &gpio3;
26 gpio3 = &gpio4; 26 gpio3 = &gpio4;
27 gpio4 = &gpio5; 27 gpio4 = &gpio5;
28 gpio5 = &gpio6; 28 gpio5 = &gpio6;
29 i2c0 = &i2c1; 29 i2c0 = &i2c1;
30 i2c1 = &i2c2; 30 i2c1 = &i2c2;
31 i2c2 = &i2c3; 31 i2c2 = &i2c3;
32 mmc0 = &esdhc1; 32 mmc0 = &esdhc1;
33 mmc1 = &esdhc2; 33 mmc1 = &esdhc2;
34 mmc2 = &esdhc3; 34 mmc2 = &esdhc3;
35 mmc3 = &esdhc4; 35 mmc3 = &esdhc4;
36 serial0 = &uart1; 36 serial0 = &uart1;
37 serial1 = &uart2; 37 serial1 = &uart2;
38 serial2 = &uart3; 38 serial2 = &uart3;
39 serial3 = &uart4; 39 serial3 = &uart4;
40 serial4 = &uart5; 40 serial4 = &uart5;
41 spi0 = &ecspi1; 41 spi0 = &ecspi1;
42 spi1 = &ecspi2; 42 spi1 = &ecspi2;
43 spi2 = &cspi; 43 spi2 = &cspi;
44 }; 44 };
45 45
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 cpu@0 { 49 cpu@0 {
50 device_type = "cpu"; 50 device_type = "cpu";
51 compatible = "arm,cort 51 compatible = "arm,cortex-a8";
52 reg = <0x0>; 52 reg = <0x0>;
53 }; 53 };
54 }; 54 };
55 55
56 tzic: tz-interrupt-controller@fffc000 56 tzic: tz-interrupt-controller@fffc000 {
57 compatible = "fsl,imx50-tzic", 57 compatible = "fsl,imx50-tzic", "fsl,imx53-tzic", "fsl,tzic";
58 interrupt-controller; 58 interrupt-controller;
59 #interrupt-cells = <1>; 59 #interrupt-cells = <1>;
60 reg = <0x0fffc000 0x4000>; 60 reg = <0x0fffc000 0x4000>;
61 }; 61 };
62 62
63 clocks { 63 clocks {
64 ckil { 64 ckil {
65 compatible = "fixed-cl 65 compatible = "fixed-clock";
66 #clock-cells = <0>; 66 #clock-cells = <0>;
67 clock-frequency = <327 67 clock-frequency = <32768>;
68 }; 68 };
69 69
70 ckih1 { 70 ckih1 {
71 compatible = "fixed-cl 71 compatible = "fixed-clock";
72 #clock-cells = <0>; 72 #clock-cells = <0>;
73 clock-frequency = <225 73 clock-frequency = <22579200>;
74 }; 74 };
75 75
76 ckih2 { 76 ckih2 {
77 compatible = "fixed-cl 77 compatible = "fixed-clock";
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 clock-frequency = <0>; 79 clock-frequency = <0>;
80 }; 80 };
81 81
82 osc { 82 osc {
83 compatible = "fixed-cl 83 compatible = "fixed-clock";
84 #clock-cells = <0>; 84 #clock-cells = <0>;
85 clock-frequency = <240 85 clock-frequency = <24000000>;
86 }; 86 };
87 }; 87 };
88 88
89 usbphy0: usbphy-0 { 89 usbphy0: usbphy-0 {
90 compatible = "usb-nop-xceiv"; 90 compatible = "usb-nop-xceiv";
91 clocks = <&clks IMX5_CLK_USB_P 91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
92 clock-names = "main_clk"; 92 clock-names = "main_clk";
93 #phy-cells = <0>; 93 #phy-cells = <0>;
94 status = "okay"; 94 status = "okay";
95 }; 95 };
96 96
97 soc: soc { 97 soc: soc {
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <1>; 99 #size-cells = <1>;
100 compatible = "simple-bus"; 100 compatible = "simple-bus";
101 interrupt-parent = <&tzic>; 101 interrupt-parent = <&tzic>;
102 ranges; 102 ranges;
103 103
104 aips1: bus@50000000 { /* AIPS1 104 aips1: bus@50000000 { /* AIPS1 */
105 compatible = "fsl,aips 105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>; 106 #address-cells = <1>;
107 #size-cells = <1>; 107 #size-cells = <1>;
108 reg = <0x50000000 0x10 108 reg = <0x50000000 0x10000000>;
109 ranges; 109 ranges;
110 110
111 spba-bus@50000000 { 111 spba-bus@50000000 {
112 compatible = " 112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells 113 #address-cells = <1>;
114 #size-cells = 114 #size-cells = <1>;
115 reg = <0x50000 115 reg = <0x50000000 0x40000>;
116 ranges; 116 ranges;
117 117
118 esdhc1: mmc@50 118 esdhc1: mmc@50004000 {
119 compat 119 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
120 reg = 120 reg = <0x50004000 0x4000>;
121 interr 121 interrupts = <1>;
122 clocks 122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 123 <&clks IMX5_CLK_DUMMY>,
124 124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
125 clock- 125 clock-names = "ipg", "ahb", "per";
126 bus-wi 126 bus-width = <4>;
127 status 127 status = "disabled";
128 }; 128 };
129 129
130 esdhc2: mmc@50 130 esdhc2: mmc@50008000 {
131 compat 131 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
132 reg = 132 reg = <0x50008000 0x4000>;
133 interr 133 interrupts = <2>;
134 clocks 134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 135 <&clks IMX5_CLK_DUMMY>,
136 136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
137 clock- 137 clock-names = "ipg", "ahb", "per";
138 bus-wi 138 bus-width = <4>;
139 status 139 status = "disabled";
140 }; 140 };
141 141
142 uart3: serial@ 142 uart3: serial@5000c000 {
143 compat 143 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
144 reg = 144 reg = <0x5000c000 0x4000>;
145 interr 145 interrupts = <33>;
146 clocks 146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 147 <&clks IMX5_CLK_UART3_PER_GATE>;
148 clock- 148 clock-names = "ipg", "per";
149 status 149 status = "disabled";
150 }; 150 };
151 151
152 ecspi1: spi@50 152 ecspi1: spi@50010000 {
153 #addre 153 #address-cells = <1>;
154 #size- 154 #size-cells = <0>;
155 compat 155 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
156 reg = 156 reg = <0x50010000 0x4000>;
157 interr 157 interrupts = <36>;
158 clocks 158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
159 159 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
160 clock- 160 clock-names = "ipg", "per";
161 status 161 status = "disabled";
162 }; 162 };
163 163
164 ssi2: ssi@5001 164 ssi2: ssi@50014000 {
165 #sound 165 #sound-dai-cells = <0>;
166 compat 166 compatible = "fsl,imx50-ssi",
167 167 "fsl,imx51-ssi",
168 168 "fsl,imx21-ssi";
169 reg = 169 reg = <0x50014000 0x4000>;
170 interr 170 interrupts = <30>;
171 clocks 171 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
172 dmas = 172 dmas = <&sdma 24 1 0>,
173 173 <&sdma 25 1 0>;
174 dma-na 174 dma-names = "rx", "tx";
175 fsl,fi 175 fsl,fifo-depth = <15>;
176 status 176 status = "disabled";
177 }; 177 };
178 178
179 esdhc3: mmc@50 179 esdhc3: mmc@50020000 {
180 compat 180 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
181 reg = 181 reg = <0x50020000 0x4000>;
182 interr 182 interrupts = <3>;
183 clocks 183 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
184 184 <&clks IMX5_CLK_DUMMY>,
185 185 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
186 clock- 186 clock-names = "ipg", "ahb", "per";
187 bus-wi 187 bus-width = <4>;
188 status 188 status = "disabled";
189 }; 189 };
190 190
191 esdhc4: mmc@50 191 esdhc4: mmc@50024000 {
192 compat 192 compatible = "fsl,imx50-esdhc", "fsl,imx53-esdhc";
193 reg = 193 reg = <0x50024000 0x4000>;
194 interr 194 interrupts = <4>;
195 clocks 195 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
196 196 <&clks IMX5_CLK_DUMMY>,
197 197 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
198 clock- 198 clock-names = "ipg", "ahb", "per";
199 bus-wi 199 bus-width = <4>;
200 status 200 status = "disabled";
201 }; 201 };
202 }; 202 };
203 203
204 usbotg: usb@53f80000 { 204 usbotg: usb@53f80000 {
205 compatible = " 205 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
206 reg = <0x53f80 206 reg = <0x53f80000 0x0200>;
207 interrupts = < 207 interrupts = <18>;
208 clocks = <&clk 208 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
209 fsl,usbphy = < 209 fsl,usbphy = <&usbphy0>;
210 status = "disa 210 status = "disabled";
211 }; 211 };
212 212
213 usbh1: usb@53f80200 { 213 usbh1: usb@53f80200 {
214 compatible = " 214 compatible = "fsl,imx50-usb", "fsl,imx27-usb";
215 reg = <0x53f80 215 reg = <0x53f80200 0x0200>;
216 interrupts = < 216 interrupts = <14>;
217 clocks = <&clk 217 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
218 dr_mode = "hos 218 dr_mode = "host";
219 status = "disa 219 status = "disabled";
220 }; 220 };
221 221
222 gpio1: gpio@53f84000 { 222 gpio1: gpio@53f84000 {
223 compatible = " 223 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
224 reg = <0x53f84 224 reg = <0x53f84000 0x4000>;
225 interrupts = < 225 interrupts = <50 51>;
226 gpio-controlle 226 gpio-controller;
227 #gpio-cells = 227 #gpio-cells = <2>;
228 interrupt-cont 228 interrupt-controller;
229 #interrupt-cel 229 #interrupt-cells = <2>;
230 gpio-ranges = 230 gpio-ranges = <&iomuxc 0 151 28>;
231 }; 231 };
232 232
233 gpio2: gpio@53f88000 { 233 gpio2: gpio@53f88000 {
234 compatible = " 234 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
235 reg = <0x53f88 235 reg = <0x53f88000 0x4000>;
236 interrupts = < 236 interrupts = <52 53>;
237 gpio-controlle 237 gpio-controller;
238 #gpio-cells = 238 #gpio-cells = <2>;
239 interrupt-cont 239 interrupt-controller;
240 #interrupt-cel 240 #interrupt-cells = <2>;
241 gpio-ranges = 241 gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
242 242 <&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
243 243 <&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
244 244 <&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
245 }; 245 };
246 246
247 gpio3: gpio@53f8c000 { 247 gpio3: gpio@53f8c000 {
248 compatible = " 248 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
249 reg = <0x53f8c 249 reg = <0x53f8c000 0x4000>;
250 interrupts = < 250 interrupts = <54 55>;
251 gpio-controlle 251 gpio-controller;
252 #gpio-cells = 252 #gpio-cells = <2>;
253 interrupt-cont 253 interrupt-controller;
254 #interrupt-cel 254 #interrupt-cells = <2>;
255 gpio-ranges = 255 gpio-ranges = <&iomuxc 0 108 32>;
256 }; 256 };
257 257
258 gpio4: gpio@53f90000 { 258 gpio4: gpio@53f90000 {
259 compatible = " 259 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
260 reg = <0x53f90 260 reg = <0x53f90000 0x4000>;
261 interrupts = < 261 interrupts = <56 57>;
262 gpio-controlle 262 gpio-controller;
263 #gpio-cells = 263 #gpio-cells = <2>;
264 interrupt-cont 264 interrupt-controller;
265 #interrupt-cel 265 #interrupt-cells = <2>;
266 gpio-ranges = 266 gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
267 267 <&iomuxc 20 140 11>;
268 }; 268 };
269 269
270 wdog1: watchdog@53f980 270 wdog1: watchdog@53f98000 {
271 compatible = " 271 compatible = "fsl,imx50-wdt", "fsl,imx21-wdt";
272 reg = <0x53f98 272 reg = <0x53f98000 0x4000>;
273 interrupts = < 273 interrupts = <58>;
274 clocks = <&clk 274 clocks = <&clks IMX5_CLK_DUMMY>;
275 }; 275 };
276 276
277 gpt: timer@53fa0000 { 277 gpt: timer@53fa0000 {
278 compatible = " 278 compatible = "fsl,imx50-gpt", "fsl,imx31-gpt";
279 reg = <0x53fa0 279 reg = <0x53fa0000 0x4000>;
280 interrupts = < 280 interrupts = <39>;
281 clocks = <&clk 281 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
282 <&clk 282 <&clks IMX5_CLK_GPT_HF_GATE>;
283 clock-names = 283 clock-names = "ipg", "per";
284 }; 284 };
285 285
286 iomuxc: iomuxc@53fa800 286 iomuxc: iomuxc@53fa8000 {
287 compatible = " 287 compatible = "fsl,imx50-iomuxc", "fsl,imx53-iomuxc";
288 reg = <0x53fa8 288 reg = <0x53fa8000 0x4000>;
289 }; 289 };
290 290
291 pwm1: pwm@53fb4000 { 291 pwm1: pwm@53fb4000 {
292 #pwm-cells = < 292 #pwm-cells = <3>;
293 compatible = " 293 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
294 reg = <0x53fb4 294 reg = <0x53fb4000 0x4000>;
295 clocks = <&clk 295 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
296 <&clk 296 <&clks IMX5_CLK_PWM1_HF_GATE>;
297 clock-names = 297 clock-names = "ipg", "per";
298 interrupts = < 298 interrupts = <61>;
299 }; 299 };
300 300
301 pwm2: pwm@53fb8000 { 301 pwm2: pwm@53fb8000 {
302 #pwm-cells = < 302 #pwm-cells = <3>;
303 compatible = " 303 compatible = "fsl,imx50-pwm", "fsl,imx27-pwm";
304 reg = <0x53fb8 304 reg = <0x53fb8000 0x4000>;
305 clocks = <&clk 305 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
306 <&clk 306 <&clks IMX5_CLK_PWM2_HF_GATE>;
307 clock-names = 307 clock-names = "ipg", "per";
308 interrupts = < 308 interrupts = <94>;
309 }; 309 };
310 310
311 uart1: serial@53fbc000 311 uart1: serial@53fbc000 {
312 compatible = " 312 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
313 reg = <0x53fbc 313 reg = <0x53fbc000 0x4000>;
314 interrupts = < 314 interrupts = <31>;
315 clocks = <&clk 315 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
316 <&clk 316 <&clks IMX5_CLK_UART1_PER_GATE>;
317 clock-names = 317 clock-names = "ipg", "per";
318 status = "disa 318 status = "disabled";
319 }; 319 };
320 320
321 uart2: serial@53fc0000 321 uart2: serial@53fc0000 {
322 compatible = " 322 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
323 reg = <0x53fc0 323 reg = <0x53fc0000 0x4000>;
324 interrupts = < 324 interrupts = <32>;
325 clocks = <&clk 325 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
326 <&clk 326 <&clks IMX5_CLK_UART2_PER_GATE>;
327 clock-names = 327 clock-names = "ipg", "per";
328 status = "disa 328 status = "disabled";
329 }; 329 };
330 330
331 src: reset-controller@ 331 src: reset-controller@53fd0000 {
332 compatible = " 332 compatible = "fsl,imx50-src", "fsl,imx51-src";
333 reg = <0x53fd0 333 reg = <0x53fd0000 0x4000>;
334 interrupts = < 334 interrupts = <75>;
335 #reset-cells = 335 #reset-cells = <1>;
336 }; 336 };
337 337
338 clks: ccm@53fd4000 { 338 clks: ccm@53fd4000 {
339 compatible = " 339 compatible = "fsl,imx50-ccm";
340 reg = <0x53fd4 340 reg = <0x53fd4000 0x4000>;
341 interrupts = < 341 interrupts = <0 71 0x04 0 72 0x04>;
342 #clock-cells = 342 #clock-cells = <1>;
343 }; 343 };
344 344
345 gpio5: gpio@53fdc000 { 345 gpio5: gpio@53fdc000 {
346 compatible = " 346 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
347 reg = <0x53fdc 347 reg = <0x53fdc000 0x4000>;
348 interrupts = < 348 interrupts = <103 104>;
349 gpio-controlle 349 gpio-controller;
350 #gpio-cells = 350 #gpio-cells = <2>;
351 interrupt-cont 351 interrupt-controller;
352 #interrupt-cel 352 #interrupt-cells = <2>;
353 gpio-ranges = 353 gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
354 }; 354 };
355 355
356 gpio6: gpio@53fe0000 { 356 gpio6: gpio@53fe0000 {
357 compatible = " 357 compatible = "fsl,imx50-gpio", "fsl,imx35-gpio";
358 reg = <0x53fe0 358 reg = <0x53fe0000 0x4000>;
359 interrupts = < 359 interrupts = <105 106>;
360 gpio-controlle 360 gpio-controller;
361 #gpio-cells = 361 #gpio-cells = <2>;
362 interrupt-cont 362 interrupt-controller;
363 #interrupt-cel 363 #interrupt-cells = <2>;
364 gpio-ranges = 364 gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
365 }; 365 };
366 366
367 i2c3: i2c@53fec000 { 367 i2c3: i2c@53fec000 {
368 #address-cells 368 #address-cells = <1>;
369 #size-cells = 369 #size-cells = <0>;
370 compatible = " 370 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
371 reg = <0x53fec 371 reg = <0x53fec000 0x4000>;
372 interrupts = < 372 interrupts = <64>;
373 clocks = <&clk 373 clocks = <&clks IMX5_CLK_I2C3_GATE>;
374 status = "disa 374 status = "disabled";
375 }; 375 };
376 376
377 uart4: serial@53ff0000 377 uart4: serial@53ff0000 {
378 compatible = " 378 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
379 reg = <0x53ff0 379 reg = <0x53ff0000 0x4000>;
380 interrupts = < 380 interrupts = <13>;
381 clocks = <&clk 381 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
382 <&clk 382 <&clks IMX5_CLK_UART4_PER_GATE>;
383 clock-names = 383 clock-names = "ipg", "per";
384 status = "disa 384 status = "disabled";
385 }; 385 };
386 }; 386 };
387 387
388 aips2: bus@60000000 { /* AIP 388 aips2: bus@60000000 { /* AIPS2 */
389 compatible = "fsl,aips 389 compatible = "fsl,aips-bus", "simple-bus";
390 #address-cells = <1>; 390 #address-cells = <1>;
391 #size-cells = <1>; 391 #size-cells = <1>;
392 reg = <0x60000000 0x10 392 reg = <0x60000000 0x10000000>;
393 ranges; 393 ranges;
394 394
395 uart5: serial@63f90000 395 uart5: serial@63f90000 {
396 compatible = " 396 compatible = "fsl,imx50-uart", "fsl,imx21-uart";
397 reg = <0x63f90 397 reg = <0x63f90000 0x4000>;
398 interrupts = < 398 interrupts = <86>;
399 clocks = <&clk 399 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
400 <&clk 400 <&clks IMX5_CLK_UART5_PER_GATE>;
401 clock-names = 401 clock-names = "ipg", "per";
402 status = "disa 402 status = "disabled";
403 }; 403 };
404 404
405 owire: owire@63fa4000 405 owire: owire@63fa4000 {
406 compatible = " 406 compatible = "fsl,imx50-owire", "fsl,imx21-owire";
407 reg = <0x63fa4 407 reg = <0x63fa4000 0x4000>;
408 clocks = <&clk 408 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
409 status = "disa 409 status = "disabled";
410 }; 410 };
411 411
412 ecspi2: spi@63fac000 { 412 ecspi2: spi@63fac000 {
413 #address-cells 413 #address-cells = <1>;
414 #size-cells = 414 #size-cells = <0>;
415 compatible = " 415 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
416 reg = <0x63fac 416 reg = <0x63fac000 0x4000>;
417 interrupts = < 417 interrupts = <37>;
418 clocks = <&clk 418 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
419 <&clk 419 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
420 clock-names = 420 clock-names = "ipg", "per";
421 status = "disa 421 status = "disabled";
422 }; 422 };
423 423
424 sdma: dma-controller@6 424 sdma: dma-controller@63fb0000 {
425 compatible = " 425 compatible = "fsl,imx50-sdma", "fsl,imx35-sdma";
426 reg = <0x63fb0 426 reg = <0x63fb0000 0x4000>;
427 interrupts = < 427 interrupts = <6>;
428 clocks = <&clk 428 clocks = <&clks IMX5_CLK_SDMA_GATE>,
429 <&clk 429 <&clks IMX5_CLK_AHB>;
430 clock-names = 430 clock-names = "ipg", "ahb";
431 #dma-cells = < 431 #dma-cells = <3>;
432 fsl,sdma-ram-s 432 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
433 }; 433 };
434 434
435 cspi: spi@63fc0000 { 435 cspi: spi@63fc0000 {
436 #address-cells 436 #address-cells = <1>;
437 #size-cells = 437 #size-cells = <0>;
438 compatible = " 438 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
439 reg = <0x63fc0 439 reg = <0x63fc0000 0x4000>;
440 interrupts = < 440 interrupts = <38>;
441 clocks = <&clk 441 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
442 <&clk 442 <&clks IMX5_CLK_CSPI_IPG_GATE>;
443 clock-names = 443 clock-names = "ipg", "per";
444 status = "disa 444 status = "disabled";
445 }; 445 };
446 446
447 i2c2: i2c@63fc4000 { 447 i2c2: i2c@63fc4000 {
448 #address-cells 448 #address-cells = <1>;
449 #size-cells = 449 #size-cells = <0>;
450 compatible = " 450 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
451 reg = <0x63fc4 451 reg = <0x63fc4000 0x4000>;
452 interrupts = < 452 interrupts = <63>;
453 clocks = <&clk 453 clocks = <&clks IMX5_CLK_I2C2_GATE>;
454 status = "disa 454 status = "disabled";
455 }; 455 };
456 456
457 i2c1: i2c@63fc8000 { 457 i2c1: i2c@63fc8000 {
458 #address-cells 458 #address-cells = <1>;
459 #size-cells = 459 #size-cells = <0>;
460 compatible = " 460 compatible = "fsl,imx50-i2c", "fsl,imx21-i2c";
461 reg = <0x63fc8 461 reg = <0x63fc8000 0x4000>;
462 interrupts = < 462 interrupts = <62>;
463 clocks = <&clk 463 clocks = <&clks IMX5_CLK_I2C1_GATE>;
464 status = "disa 464 status = "disabled";
465 }; 465 };
466 466
467 ssi1: ssi@63fcc000 { 467 ssi1: ssi@63fcc000 {
468 #sound-dai-cel 468 #sound-dai-cells = <0>;
469 compatible = " 469 compatible = "fsl,imx50-ssi", "fsl,imx51-ssi",
470 470 "fsl,imx21-ssi";
471 reg = <0x63fcc 471 reg = <0x63fcc000 0x4000>;
472 interrupts = < 472 interrupts = <29>;
473 clocks = <&clk 473 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
474 dmas = <&sdma 474 dmas = <&sdma 28 0 0>,
475 <&sdma 475 <&sdma 29 0 0>;
476 dma-names = "r 476 dma-names = "rx", "tx";
477 fsl,fifo-depth 477 fsl,fifo-depth = <15>;
478 status = "disa 478 status = "disabled";
479 }; 479 };
480 480
481 audmux: audmux@63fd000 481 audmux: audmux@63fd0000 {
482 compatible = " 482 compatible = "fsl,imx50-audmux", "fsl,imx31-audmux";
483 reg = <0x63fd0 483 reg = <0x63fd0000 0x4000>;
484 status = "disa 484 status = "disabled";
485 }; 485 };
486 486
487 fec: ethernet@63fec000 487 fec: ethernet@63fec000 {
488 compatible = " 488 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
489 reg = <0x63fec 489 reg = <0x63fec000 0x4000>;
490 interrupts = < 490 interrupts = <87>;
491 clocks = <&clk 491 clocks = <&clks IMX5_CLK_FEC_GATE>,
492 <&clk 492 <&clks IMX5_CLK_FEC_GATE>,
493 <&clk 493 <&clks IMX5_CLK_FEC_GATE>;
494 clock-names = 494 clock-names = "ipg", "ahb", "ptp";
495 status = "disa 495 status = "disabled";
496 }; 496 };
497 }; 497 };
498 }; 498 };
499 }; 499 };
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