1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2017 Zodiac Inflight Innovati 3 * Copyright (C) 2017 Zodiac Inflight Innovations
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include "imx51.dtsi" 7 #include "imx51.dtsi"
8 #include <dt-bindings/sound/fsl-imx-audmux.h> 8 #include <dt-bindings/sound/fsl-imx-audmux.h>
9 9
10 / { 10 / {
11 model = "ZII RDU1 Board"; 11 model = "ZII RDU1 Board";
12 compatible = "zii,imx51-rdu1", "fsl,im 12 compatible = "zii,imx51-rdu1", "fsl,imx51";
13 13
14 chosen { 14 chosen {
15 stdout-path = &uart1; 15 stdout-path = &uart1;
16 }; 16 };
17 17
18 /* Will be filled by the bootloader */ 18 /* Will be filled by the bootloader */
19 memory@90000000 { 19 memory@90000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x90000000 0>; 21 reg = <0x90000000 0>;
22 }; 22 };
23 23
24 aliases { 24 aliases {
25 mdio-gpio0 = &mdio_gpio; 25 mdio-gpio0 = &mdio_gpio;
26 rtc0 = &ds1341; 26 rtc0 = &ds1341;
27 }; 27 };
28 28
29 clk_26M_osc: 26M_osc { 29 clk_26M_osc: 26M_osc {
30 compatible = "fixed-clock"; 30 compatible = "fixed-clock";
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 clock-frequency = <26000000>; 32 clock-frequency = <26000000>;
33 }; 33 };
34 34
35 clk_26M_osc_gate: 26M_gate { 35 clk_26M_osc_gate: 26M_gate {
36 compatible = "gpio-gate-clock" 36 compatible = "gpio-gate-clock";
37 pinctrl-names = "default"; 37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_clk26mhz 38 pinctrl-0 = <&pinctrl_clk26mhz>;
39 clocks = <&clk_26M_osc>; 39 clocks = <&clk_26M_osc>;
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 enable-gpios = <&gpio3 1 GPIO_ 41 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
42 }; 42 };
43 43
44 clk_26M_usb: usbhost_gate { 44 clk_26M_usb: usbhost_gate {
45 compatible = "gpio-gate-clock" 45 compatible = "gpio-gate-clock";
46 pinctrl-names = "default"; 46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_usbgate2 47 pinctrl-0 = <&pinctrl_usbgate26mhz>;
48 clocks = <&clk_26M_osc_gate>; 48 clocks = <&clk_26M_osc_gate>;
49 #clock-cells = <0>; 49 #clock-cells = <0>;
50 enable-gpios = <&gpio1 19 GPIO 50 enable-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
51 }; 51 };
52 52
53 clk_26M_snd: snd_gate { 53 clk_26M_snd: snd_gate {
54 compatible = "gpio-gate-clock" 54 compatible = "gpio-gate-clock";
55 pinctrl-names = "default"; 55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_sndgate2 56 pinctrl-0 = <&pinctrl_sndgate26mhz>;
57 clocks = <&clk_26M_osc_gate>; 57 clocks = <&clk_26M_osc_gate>;
58 #clock-cells = <0>; 58 #clock-cells = <0>;
59 enable-gpios = <&gpio4 26 GPIO 59 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
60 }; 60 };
61 61
62 reg_5p0v_main: regulator-5p0v-main { 62 reg_5p0v_main: regulator-5p0v-main {
63 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
64 regulator-name = "5V_MAIN"; 64 regulator-name = "5V_MAIN";
65 regulator-min-microvolt = <500 65 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <500 66 regulator-max-microvolt = <5000000>;
67 regulator-always-on; 67 regulator-always-on;
68 }; 68 };
69 69
70 reg_3p3v: regulator-3p3v { 70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed" 71 compatible = "regulator-fixed";
72 regulator-name = "3.3V"; 72 regulator-name = "3.3V";
73 regulator-min-microvolt = <330 73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <330 74 regulator-max-microvolt = <3300000>;
75 regulator-always-on; 75 regulator-always-on;
76 }; 76 };
77 77
78 disp0 { 78 disp0 {
79 compatible = "fsl,imx-parallel 79 compatible = "fsl,imx-parallel-display";
80 pinctrl-names = "default"; 80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_ipu_disp 81 pinctrl-0 = <&pinctrl_ipu_disp1>;
82 82
83 #address-cells = <1>; 83 #address-cells = <1>;
84 #size-cells = <0>; 84 #size-cells = <0>;
85 85
86 port@0 { 86 port@0 {
87 reg = <0>; 87 reg = <0>;
88 88
89 display_in: endpoint { 89 display_in: endpoint {
90 remote-endpoin 90 remote-endpoint = <&ipu_di0_disp1>;
91 }; 91 };
92 }; 92 };
93 93
94 port@1 { 94 port@1 {
95 reg = <1>; 95 reg = <1>;
96 96
97 display_out: endpoint 97 display_out: endpoint {
98 remote-endpoin 98 remote-endpoint = <&panel_in>;
99 }; 99 };
100 }; 100 };
101 }; 101 };
102 102
103 panel { 103 panel {
104 /* no compatible here, bootloa 104 /* no compatible here, bootloader will patch in correct one */
105 pinctrl-names = "default"; 105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_panel>; 106 pinctrl-0 = <&pinctrl_panel>;
107 power-supply = <®_3p3v>; 107 power-supply = <®_3p3v>;
108 enable-gpios = <&gpio3 3 GPIO_ 108 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
109 status = "disabled"; 109 status = "disabled";
110 110
111 port { 111 port {
112 panel_in: endpoint { 112 panel_in: endpoint {
113 remote-endpoin 113 remote-endpoint = <&display_out>;
114 }; 114 };
115 }; 115 };
116 }; 116 };
117 117
118 i2c_gpio: i2c-gpio { 118 i2c_gpio: i2c-gpio {
119 compatible = "i2c-gpio"; 119 compatible = "i2c-gpio";
120 pinctrl-names = "default"; 120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_swi2c>; 121 pinctrl-0 = <&pinctrl_swi2c>;
122 sda-gpios = <&gpio1 2 GPIO_ACT 122 sda-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
123 scl-gpios = <&gpio3 4 GPIO_ACT 123 scl-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
124 i2c-gpio,delay-us = <50>; 124 i2c-gpio,delay-us = <50>;
125 status = "okay"; 125 status = "okay";
126 126
127 #address-cells = <1>; 127 #address-cells = <1>;
128 #size-cells = <0>; 128 #size-cells = <0>;
129 129
130 sgtl5000: codec@a { 130 sgtl5000: codec@a {
131 compatible = "fsl,sgtl 131 compatible = "fsl,sgtl5000";
132 reg = <0x0a>; 132 reg = <0x0a>;
133 clocks = <&clk_26M_snd 133 clocks = <&clk_26M_snd>;
134 VDDA-supply = <&vdig_r 134 VDDA-supply = <&vdig_reg>;
135 VDDIO-supply = <&vvide 135 VDDIO-supply = <&vvideo_reg>;
136 #sound-dai-cells = <0> 136 #sound-dai-cells = <0>;
137 }; 137 };
138 }; 138 };
139 139
140 spi_gpio: spi { 140 spi_gpio: spi {
141 compatible = "spi-gpio"; 141 compatible = "spi-gpio";
142 #address-cells = <1>; 142 #address-cells = <1>;
143 #size-cells = <0>; 143 #size-cells = <0>;
144 pinctrl-names = "default"; 144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_gpiospi0 145 pinctrl-0 = <&pinctrl_gpiospi0>;
146 status = "okay"; 146 status = "okay";
147 147
148 sck-gpios = <&gpio4 15 GPIO_AC 148 sck-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
149 mosi-gpios = <&gpio4 12 GPIO_A 149 mosi-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
150 miso-gpios = <&gpio4 11 GPIO_A 150 miso-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
151 num-chipselects = <1>; 151 num-chipselects = <1>;
152 cs-gpios = <&gpio4 14 GPIO_ACT 152 cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
153 153
154 eeprom@0 { 154 eeprom@0 {
155 compatible = "eeprom-9 155 compatible = "eeprom-93xx46";
156 reg = <0>; 156 reg = <0>;
157 spi-max-frequency = <1 157 spi-max-frequency = <1000000>;
158 spi-cs-high; 158 spi-cs-high;
159 data-size = <8>; 159 data-size = <8>;
160 }; 160 };
161 }; 161 };
162 162
163 mdio_gpio: mdio-gpio { 163 mdio_gpio: mdio-gpio {
164 compatible = "virtual,mdio-gpi 164 compatible = "virtual,mdio-gpio";
165 pinctrl-names = "default"; 165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_swmdio>; 166 pinctrl-0 = <&pinctrl_swmdio>;
167 gpios = <&gpio3 26 GPIO_ACTIVE 167 gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>, /* mdc */
168 <&gpio3 25 GPIO_ACTIVE 168 <&gpio3 25 GPIO_ACTIVE_HIGH>; /* mdio */
169 169
170 #address-cells = <1>; 170 #address-cells = <1>;
171 #size-cells = <0>; 171 #size-cells = <0>;
172 172
173 switch@0 { 173 switch@0 {
174 compatible = "marvell, 174 compatible = "marvell,mv88e6085";
175 reg = <0>; 175 reg = <0>;
176 dsa,member = <0 0>; 176 dsa,member = <0 0>;
177 177
178 ports { 178 ports {
179 #address-cells 179 #address-cells = <1>;
180 #size-cells = 180 #size-cells = <0>;
181 181
182 port@0 { 182 port@0 {
183 reg = 183 reg = <0>;
184 phy-mo 184 phy-mode = "rev-mii";
185 ethern 185 ethernet = <&fec>;
186 186
187 fixed- 187 fixed-link {
188 188 speed = <100>;
189 189 full-duplex;
190 }; 190 };
191 }; 191 };
192 192
193 port@1 { 193 port@1 {
194 reg = 194 reg = <1>;
195 label 195 label = "netaux";
196 }; 196 };
197 197
198 port@3 { 198 port@3 {
199 reg = 199 reg = <3>;
200 label 200 label = "netright";
201 }; 201 };
202 202
203 port@4 { 203 port@4 {
204 reg = 204 reg = <4>;
205 label 205 label = "netleft";
206 }; 206 };
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 210
211 sound { 211 sound {
212 compatible = "simple-audio-car 212 compatible = "simple-audio-card";
213 simple-audio-card,name = "Fron 213 simple-audio-card,name = "Front";
214 simple-audio-card,format = "i2 214 simple-audio-card,format = "i2s";
215 simple-audio-card,bitclock-mas 215 simple-audio-card,bitclock-master = <&sound_codec>;
216 simple-audio-card,frame-master 216 simple-audio-card,frame-master = <&sound_codec>;
217 simple-audio-card,widgets = 217 simple-audio-card,widgets =
218 "Headphone", "Headphon 218 "Headphone", "Headphone Jack";
219 simple-audio-card,routing = 219 simple-audio-card,routing =
220 "Headphone Jack", "TPA 220 "Headphone Jack", "TPA6130A2 HPLEFT",
221 "Headphone Jack", "TPA 221 "Headphone Jack", "TPA6130A2 HPRIGHT";
222 simple-audio-card,aux-devs = < 222 simple-audio-card,aux-devs = <&hpa1>;
223 223
224 sound_cpu: simple-audio-card,c 224 sound_cpu: simple-audio-card,cpu {
225 sound-dai = <&ssi2>; 225 sound-dai = <&ssi2>;
226 }; 226 };
227 227
228 sound_codec: simple-audio-card 228 sound_codec: simple-audio-card,codec {
229 sound-dai = <&sgtl5000 229 sound-dai = <&sgtl5000>;
230 clocks = <&clk_26M_snd 230 clocks = <&clk_26M_snd>;
231 }; 231 };
232 }; 232 };
233 233
234 usbh1phy: usbphy1 { 234 usbh1phy: usbphy1 {
235 compatible = "usb-nop-xceiv"; 235 compatible = "usb-nop-xceiv";
236 pinctrl-names = "default"; 236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_usbh1phy 237 pinctrl-0 = <&pinctrl_usbh1phy>;
238 clocks = <&clk_26M_usb>; 238 clocks = <&clk_26M_usb>;
239 clock-names = "main_clk"; 239 clock-names = "main_clk";
240 reset-gpios = <&gpio4 8 GPIO_A 240 reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
241 vcc-supply = <&vusb_reg>; 241 vcc-supply = <&vusb_reg>;
242 #phy-cells = <0>; 242 #phy-cells = <0>;
243 }; 243 };
244 244
245 usbh2phy: usbphy2 { 245 usbh2phy: usbphy2 {
246 compatible = "usb-nop-xceiv"; 246 compatible = "usb-nop-xceiv";
247 pinctrl-names = "default"; 247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_usbh2phy 248 pinctrl-0 = <&pinctrl_usbh2phy>;
249 clocks = <&clk_26M_usb>; 249 clocks = <&clk_26M_usb>;
250 clock-names = "main_clk"; 250 clock-names = "main_clk";
251 reset-gpios = <&gpio4 7 GPIO_A 251 reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
252 vcc-supply = <&vusb_reg>; 252 vcc-supply = <&vusb_reg>;
253 #phy-cells = <0>; 253 #phy-cells = <0>;
254 }; 254 };
255 }; 255 };
256 256
257 &audmux { 257 &audmux {
258 pinctrl-names = "default"; 258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_audmux>; 259 pinctrl-0 = <&pinctrl_audmux>;
260 status = "okay"; 260 status = "okay";
261 261
262 ssi2 { 262 ssi2 {
263 fsl,audmux-port = <1>; 263 fsl,audmux-port = <1>;
264 fsl,port-config = < 264 fsl,port-config = <
265 (IMX_AUDMUX_V2_PTCR_SY 265 (IMX_AUDMUX_V2_PTCR_SYN |
266 IMX_AUDMUX_V2_PTCR_TF 266 IMX_AUDMUX_V2_PTCR_TFSEL(2) |
267 IMX_AUDMUX_V2_PTCR_TC 267 IMX_AUDMUX_V2_PTCR_TCSEL(2) |
268 IMX_AUDMUX_V2_PTCR_TF 268 IMX_AUDMUX_V2_PTCR_TFSDIR |
269 IMX_AUDMUX_V2_PTCR_TC 269 IMX_AUDMUX_V2_PTCR_TCLKDIR)
270 IMX_AUDMUX_V2_PDCR_RXD 270 IMX_AUDMUX_V2_PDCR_RXDSEL(2)
271 >; 271 >;
272 }; 272 };
273 273
274 aud3 { 274 aud3 {
275 fsl,audmux-port = <2>; 275 fsl,audmux-port = <2>;
276 fsl,port-config = < 276 fsl,port-config = <
277 IMX_AUDMUX_V2_PTCR_SYN 277 IMX_AUDMUX_V2_PTCR_SYN
278 IMX_AUDMUX_V2_PDCR_RXD 278 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
279 >; 279 >;
280 }; 280 };
281 }; 281 };
282 282
283 &cpu { 283 &cpu {
284 cpu-supply = <&sw1_reg>; 284 cpu-supply = <&sw1_reg>;
285 }; 285 };
286 286
287 &ecspi1 { 287 &ecspi1 {
288 pinctrl-names = "default"; 288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_ecspi1>; 289 pinctrl-0 = <&pinctrl_ecspi1>;
290 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH 290 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
291 <&gpio4 25 GPIO_ACTIVE_LOW> 291 <&gpio4 25 GPIO_ACTIVE_LOW>;
292 status = "okay"; 292 status = "okay";
293 293
294 pmic@0 { 294 pmic@0 {
295 compatible = "fsl,mc13892"; 295 compatible = "fsl,mc13892";
296 pinctrl-names = "default"; 296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_pmic>; 297 pinctrl-0 = <&pinctrl_pmic>;
298 spi-max-frequency = <6000000>; 298 spi-max-frequency = <6000000>;
299 spi-cs-high; 299 spi-cs-high;
300 reg = <0>; 300 reg = <0>;
301 interrupt-parent = <&gpio1>; 301 interrupt-parent = <&gpio1>;
302 interrupts = <8 IRQ_TYPE_LEVEL 302 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
303 fsl,mc13xxx-uses-adc; 303 fsl,mc13xxx-uses-adc;
304 304
305 regulators { 305 regulators {
306 sw1_reg: sw1 { 306 sw1_reg: sw1 {
307 regulator-min- 307 regulator-min-microvolt = <600000>;
308 regulator-max- 308 regulator-max-microvolt = <1375000>;
309 regulator-boot 309 regulator-boot-on;
310 regulator-alwa 310 regulator-always-on;
311 }; 311 };
312 312
313 sw2_reg: sw2 { 313 sw2_reg: sw2 {
314 regulator-min- 314 regulator-min-microvolt = <900000>;
315 regulator-max- 315 regulator-max-microvolt = <1850000>;
316 regulator-boot 316 regulator-boot-on;
317 regulator-alwa 317 regulator-always-on;
318 }; 318 };
319 319
320 sw3_reg: sw3 { 320 sw3_reg: sw3 {
321 regulator-min- 321 regulator-min-microvolt = <1100000>;
322 regulator-max- 322 regulator-max-microvolt = <1850000>;
323 regulator-boot 323 regulator-boot-on;
324 regulator-alwa 324 regulator-always-on;
325 }; 325 };
326 326
327 sw4_reg: sw4 { 327 sw4_reg: sw4 {
328 regulator-min- 328 regulator-min-microvolt = <1100000>;
329 regulator-max- 329 regulator-max-microvolt = <1850000>;
330 regulator-boot 330 regulator-boot-on;
331 regulator-alwa 331 regulator-always-on;
332 }; 332 };
333 333
334 vpll_reg: vpll { 334 vpll_reg: vpll {
335 regulator-min- 335 regulator-min-microvolt = <1050000>;
336 regulator-max- 336 regulator-max-microvolt = <1800000>;
337 regulator-boot 337 regulator-boot-on;
338 regulator-alwa 338 regulator-always-on;
339 }; 339 };
340 340
341 vdig_reg: vdig { 341 vdig_reg: vdig {
342 regulator-min- 342 regulator-min-microvolt = <1650000>;
343 regulator-max- 343 regulator-max-microvolt = <1650000>;
344 regulator-boot 344 regulator-boot-on;
345 }; 345 };
346 346
347 vsd_reg: vsd { 347 vsd_reg: vsd {
348 regulator-min- 348 regulator-min-microvolt = <1800000>;
349 regulator-max- 349 regulator-max-microvolt = <3150000>;
350 }; 350 };
351 351
352 vusb_reg: vusb { 352 vusb_reg: vusb {
353 regulator-alwa 353 regulator-always-on;
354 }; 354 };
355 355
356 vusb2_reg: vusb2 { 356 vusb2_reg: vusb2 {
357 regulator-min- 357 regulator-min-microvolt = <2400000>;
358 regulator-max- 358 regulator-max-microvolt = <2775000>;
359 regulator-boot 359 regulator-boot-on;
360 regulator-alwa 360 regulator-always-on;
361 }; 361 };
362 362
363 vvideo_reg: vvideo { 363 vvideo_reg: vvideo {
364 regulator-min- 364 regulator-min-microvolt = <2775000>;
365 regulator-max- 365 regulator-max-microvolt = <2775000>;
366 }; 366 };
367 367
368 vaudio_reg: vaudio { 368 vaudio_reg: vaudio {
369 regulator-min- 369 regulator-min-microvolt = <2300000>;
370 regulator-max- 370 regulator-max-microvolt = <3000000>;
371 }; 371 };
372 372
373 vcam_reg: vcam { 373 vcam_reg: vcam {
374 regulator-min- 374 regulator-min-microvolt = <2500000>;
375 regulator-max- 375 regulator-max-microvolt = <3000000>;
376 }; 376 };
377 377
378 vgen1_reg: vgen1 { 378 vgen1_reg: vgen1 {
379 regulator-min- 379 regulator-min-microvolt = <1200000>;
380 regulator-max- 380 regulator-max-microvolt = <1200000>;
381 }; 381 };
382 382
383 vgen2_reg: vgen2 { 383 vgen2_reg: vgen2 {
384 regulator-min- 384 regulator-min-microvolt = <1200000>;
385 regulator-max- 385 regulator-max-microvolt = <3150000>;
386 regulator-alwa 386 regulator-always-on;
387 }; 387 };
388 388
389 vgen3_reg: vgen3 { 389 vgen3_reg: vgen3 {
390 regulator-min- 390 regulator-min-microvolt = <1800000>;
391 regulator-max- 391 regulator-max-microvolt = <2900000>;
392 regulator-alwa 392 regulator-always-on;
393 }; 393 };
394 }; 394 };
395 395
396 leds { 396 leds {
397 #address-cells = <1>; 397 #address-cells = <1>;
398 #size-cells = <0>; 398 #size-cells = <0>;
399 led-control = <0x0 0x0 399 led-control = <0x0 0x0 0x3f83f8 0x0>;
400 400
401 sysled0@3 { 401 sysled0@3 {
402 reg = <3>; 402 reg = <3>;
403 label = "syste 403 label = "system:green:status";
404 linux,default- 404 linux,default-trigger = "default-on";
405 }; 405 };
406 406
407 sysled1@4 { 407 sysled1@4 {
408 reg = <4>; 408 reg = <4>;
409 label = "syste 409 label = "system:green:act";
410 linux,default- 410 linux,default-trigger = "heartbeat";
411 }; 411 };
412 }; 412 };
413 }; 413 };
414 414
415 flash@1 { 415 flash@1 {
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <1>; 417 #size-cells = <1>;
418 compatible = "atmel,at45db642d 418 compatible = "atmel,at45db642d", "atmel,at45", "atmel,dataflash";
419 spi-max-frequency = <25000000> 419 spi-max-frequency = <25000000>;
420 reg = <1>; 420 reg = <1>;
421 }; 421 };
422 }; 422 };
423 423
424 &esdhc1 { 424 &esdhc1 {
425 pinctrl-names = "default"; 425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_esdhc1>; 426 pinctrl-0 = <&pinctrl_esdhc1>;
427 bus-width = <4>; 427 bus-width = <4>;
428 no-1-8-v; 428 no-1-8-v;
429 non-removable; 429 non-removable;
430 no-sdio; 430 no-sdio;
431 no-sd; 431 no-sd;
432 status = "okay"; 432 status = "okay";
433 }; 433 };
434 434
435 &fec { 435 &fec {
436 pinctrl-names = "default"; 436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_fec>; 437 pinctrl-0 = <&pinctrl_fec>;
438 phy-mode = "mii"; 438 phy-mode = "mii";
439 phy-reset-gpios = <&gpio2 14 GPIO_ACTI 439 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
440 phy-supply = <&vgen3_reg>; 440 phy-supply = <&vgen3_reg>;
441 status = "okay"; 441 status = "okay";
442 }; 442 };
443 443
444 &gpio1 { 444 &gpio1 {
445 gpio-line-names = "", "", "", "", 445 gpio-line-names = "", "", "", "",
446 "", "", "", "", 446 "", "", "", "",
447 "", "hp-amp-shutdown 447 "", "hp-amp-shutdown-b", "", "",
448 "", "", "", "", 448 "", "", "", "",
449 "", "", "", "", 449 "", "", "", "",
450 "", "", "", "", 450 "", "", "", "",
451 "", "", "", "", 451 "", "", "", "",
452 "", "", "", ""; 452 "", "", "", "";
453 453
454 unused-sd3-wp-hog { 454 unused-sd3-wp-hog {
455 /* 455 /*
456 * See pinctrl_esdhc1 below fo 456 * See pinctrl_esdhc1 below for more details on this
457 */ 457 */
458 gpio-hog; 458 gpio-hog;
459 gpios = <1 GPIO_ACTIVE_HIGH>; 459 gpios = <1 GPIO_ACTIVE_HIGH>;
460 output-high; 460 output-high;
461 }; 461 };
462 }; 462 };
463 463
464 &i2c2 { 464 &i2c2 {
465 pinctrl-names = "default"; 465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_i2c2>; 466 pinctrl-0 = <&pinctrl_i2c2>;
467 status = "okay"; 467 status = "okay";
468 468
469 hpa1: amp@60 { 469 hpa1: amp@60 {
470 compatible = "ti,tpa6130a2"; 470 compatible = "ti,tpa6130a2";
471 reg = <0x60>; 471 reg = <0x60>;
472 Vdd-supply = <®_3p3v>; 472 Vdd-supply = <®_3p3v>;
473 sound-name-prefix = "TPA6130A2 473 sound-name-prefix = "TPA6130A2";
474 }; 474 };
475 475
476 ds1341: rtc@68 { 476 ds1341: rtc@68 {
477 compatible = "dallas,ds1341"; 477 compatible = "dallas,ds1341";
478 reg = <0x68>; 478 reg = <0x68>;
479 }; 479 };
480 480
481 /* touch nodes default disabled, bootl 481 /* touch nodes default disabled, bootloader will enable the right one */
482 482
483 touchscreen@4b { 483 touchscreen@4b {
484 compatible = "atmel,maxtouch"; 484 compatible = "atmel,maxtouch";
485 reg = <0x4b>; 485 reg = <0x4b>;
486 pinctrl-names = "default"; 486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_ts>; 487 pinctrl-0 = <&pinctrl_ts>;
488 interrupt-parent = <&gpio3>; 488 interrupt-parent = <&gpio3>;
489 interrupts = <12 IRQ_TYPE_LEVE 489 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
490 status = "disabled"; 490 status = "disabled";
491 }; 491 };
492 492
493 touchscreen@4c { 493 touchscreen@4c {
494 compatible = "atmel,maxtouch"; 494 compatible = "atmel,maxtouch";
495 reg = <0x4c>; 495 reg = <0x4c>;
496 pinctrl-names = "default"; 496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_ts>; 497 pinctrl-0 = <&pinctrl_ts>;
498 interrupt-parent = <&gpio3>; 498 interrupt-parent = <&gpio3>;
499 interrupts = <12 IRQ_TYPE_LEVE 499 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
500 status = "disabled"; 500 status = "disabled";
501 }; 501 };
502 502
503 touchscreen@20 { 503 touchscreen@20 {
504 compatible = "syna,rmi4-i2c"; 504 compatible = "syna,rmi4-i2c";
505 reg = <0x20>; 505 reg = <0x20>;
506 pinctrl-names = "default"; 506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_ts>; 507 pinctrl-0 = <&pinctrl_ts>;
508 interrupt-parent = <&gpio3>; 508 interrupt-parent = <&gpio3>;
509 interrupts = <12 IRQ_TYPE_LEVE 509 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
510 status = "disabled"; 510 status = "disabled";
511 511
512 #address-cells = <1>; 512 #address-cells = <1>;
513 #size-cells = <0>; 513 #size-cells = <0>;
514 514
515 rmi4-f01@1 { 515 rmi4-f01@1 {
516 reg = <0x1>; 516 reg = <0x1>;
517 syna,nosleep-mode = <2 517 syna,nosleep-mode = <2>;
518 }; 518 };
519 519
520 rmi4-f11@11 { 520 rmi4-f11@11 {
521 reg = <0x11>; 521 reg = <0x11>;
522 touchscreen-inverted-x 522 touchscreen-inverted-x;
523 touchscreen-swapped-x- 523 touchscreen-swapped-x-y;
524 syna,sensor-type = <1> 524 syna,sensor-type = <1>;
525 }; 525 };
526 }; 526 };
527 527
528 }; 528 };
529 529
530 &ipu_di0_disp1 { 530 &ipu_di0_disp1 {
531 remote-endpoint = <&display_in>; 531 remote-endpoint = <&display_in>;
532 }; 532 };
533 533
534 &pmu { 534 &pmu {
535 secure-reg-access; 535 secure-reg-access;
536 }; 536 };
537 537
538 &ssi2 { 538 &ssi2 {
539 status = "okay"; 539 status = "okay";
540 }; 540 };
541 541
542 &uart1 { 542 &uart1 {
543 pinctrl-names = "default"; 543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_uart1>; 544 pinctrl-0 = <&pinctrl_uart1>;
545 status = "okay"; 545 status = "okay";
546 }; 546 };
547 547
548 &uart2 { 548 &uart2 {
549 pinctrl-names = "default"; 549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_uart2>; 550 pinctrl-0 = <&pinctrl_uart2>;
551 status = "okay"; 551 status = "okay";
552 }; 552 };
553 553
554 &uart3 { 554 &uart3 {
555 pinctrl-names = "default"; 555 pinctrl-names = "default";
556 pinctrl-0 = <&pinctrl_uart3>; 556 pinctrl-0 = <&pinctrl_uart3>;
557 status = "okay"; 557 status = "okay";
558 558
559 mcu { 559 mcu {
560 compatible = "zii,rave-sp-rdu1 560 compatible = "zii,rave-sp-rdu1";
561 current-speed = <38400>; 561 current-speed = <38400>;
562 #address-cells = <1>; 562 #address-cells = <1>;
563 #size-cells = <1>; 563 #size-cells = <1>;
564 564
565 watchdog { 565 watchdog {
566 compatible = "zii,rave 566 compatible = "zii,rave-sp-watchdog";
567 }; 567 };
568 568
569 backlight { 569 backlight {
570 compatible = "zii,rave 570 compatible = "zii,rave-sp-backlight";
571 }; 571 };
572 572
573 pwrbutton { 573 pwrbutton {
574 compatible = "zii,rave 574 compatible = "zii,rave-sp-pwrbutton";
575 }; 575 };
576 576
577 eeprom@a3 { 577 eeprom@a3 {
578 compatible = "zii,rave 578 compatible = "zii,rave-sp-eeprom";
579 reg = <0xa3 0x2000>; 579 reg = <0xa3 0x2000>;
580 #address-cells = <1>; 580 #address-cells = <1>;
581 #size-cells = <1>; 581 #size-cells = <1>;
582 zii,eeprom-name = "dds 582 zii,eeprom-name = "dds-eeprom";
583 }; 583 };
584 584
585 eeprom@a4 { 585 eeprom@a4 {
586 compatible = "zii,rave 586 compatible = "zii,rave-sp-eeprom";
587 reg = <0xa4 0x4000>; 587 reg = <0xa4 0x4000>;
588 #address-cells = <1>; 588 #address-cells = <1>;
589 #size-cells = <1>; 589 #size-cells = <1>;
590 zii,eeprom-name = "mai 590 zii,eeprom-name = "main-eeprom";
591 }; 591 };
592 592
593 eeprom@ae { 593 eeprom@ae {
594 compatible = "zii,rave 594 compatible = "zii,rave-sp-eeprom";
595 reg = <0xae 0x200>; 595 reg = <0xae 0x200>;
596 zii,eeprom-name = "swi 596 zii,eeprom-name = "switch-eeprom";
597 /* 597 /*
598 * Not all RDU1s have 598 * Not all RDU1s have this functionality, so we
599 * rely on the bootloa 599 * rely on the bootloader to enable this
600 */ 600 */
601 status = "disabled"; 601 status = "disabled";
602 }; 602 };
603 }; 603 };
604 }; 604 };
605 605
606 &usbh1 { 606 &usbh1 {
607 pinctrl-names = "default"; 607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_usbh1>; 608 pinctrl-0 = <&pinctrl_usbh1>;
609 dr_mode = "host"; 609 dr_mode = "host";
610 phy_type = "ulpi"; 610 phy_type = "ulpi";
611 fsl,usbphy = <&usbh1phy>; 611 fsl,usbphy = <&usbh1phy>;
612 disable-over-current; 612 disable-over-current;
613 maximum-speed = "full-speed"; 613 maximum-speed = "full-speed";
614 vbus-supply = <®_5p0v_main>; 614 vbus-supply = <®_5p0v_main>;
615 status = "okay"; 615 status = "okay";
616 }; 616 };
617 617
618 &usbh2 { 618 &usbh2 {
619 pinctrl-names = "default"; 619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_usbh2>; 620 pinctrl-0 = <&pinctrl_usbh2>;
621 dr_mode = "host"; 621 dr_mode = "host";
622 phy_type = "ulpi"; 622 phy_type = "ulpi";
623 fsl,usbphy = <&usbh2phy>; 623 fsl,usbphy = <&usbh2phy>;
624 disable-over-current; 624 disable-over-current;
625 vbus-supply = <®_5p0v_main>; 625 vbus-supply = <®_5p0v_main>;
626 status = "okay"; 626 status = "okay";
627 }; 627 };
628 628
629 &usbphy0 { 629 &usbphy0 {
630 vcc-supply = <&vusb_reg>; 630 vcc-supply = <&vusb_reg>;
631 }; 631 };
632 632
633 &usbotg { 633 &usbotg {
634 dr_mode = "host"; 634 dr_mode = "host";
635 disable-over-current; 635 disable-over-current;
636 phy_type = "utmi_wide"; 636 phy_type = "utmi_wide";
637 vbus-supply = <®_5p0v_main>; 637 vbus-supply = <®_5p0v_main>;
638 status = "okay"; 638 status = "okay";
639 }; 639 };
640 640
641 &wdog1 { 641 &wdog1 {
642 status = "disabled"; 642 status = "disabled";
643 }; 643 };
644 644
645 &iomuxc { 645 &iomuxc {
646 pinctrl-names = "default"; 646 pinctrl-names = "default";
647 pinctrl-0 = <&pinctrl_hog>; 647 pinctrl-0 = <&pinctrl_hog>;
648 648
649 pinctrl_hog: hoggrp { 649 pinctrl_hog: hoggrp {
650 fsl,pins = < 650 fsl,pins = <
651 MX51_PAD_GPIO1_9__GPIO 651 MX51_PAD_GPIO1_9__GPIO1_9 0x5e
652 >; 652 >;
653 }; 653 };
654 654
655 pinctrl_audmux: audmuxgrp { 655 pinctrl_audmux: audmuxgrp {
656 fsl,pins = < 656 fsl,pins = <
657 MX51_PAD_AUD3_BB_TXD__ 657 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0xa5
658 MX51_PAD_AUD3_BB_RXD__ 658 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x85
659 MX51_PAD_AUD3_BB_CK__A 659 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0xa5
660 MX51_PAD_AUD3_BB_FS__A 660 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x85
661 >; 661 >;
662 }; 662 };
663 663
664 pinctrl_clk26mhz: clk26mhzgrp { 664 pinctrl_clk26mhz: clk26mhzgrp {
665 fsl,pins = < 665 fsl,pins = <
666 MX51_PAD_DI1_PIN12__GP 666 MX51_PAD_DI1_PIN12__GPIO3_1 0x85
667 >; 667 >;
668 }; 668 };
669 669
670 pinctrl_ecspi1: ecspi1grp { 670 pinctrl_ecspi1: ecspi1grp {
671 fsl,pins = < 671 fsl,pins = <
672 MX51_PAD_CSPI1_MISO__E 672 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
673 MX51_PAD_CSPI1_MOSI__E 673 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
674 MX51_PAD_CSPI1_SCLK__E 674 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
675 MX51_PAD_CSPI1_SS0__GP 675 MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
676 MX51_PAD_CSPI1_SS1__GP 676 MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
677 >; 677 >;
678 }; 678 };
679 679
680 pinctrl_esdhc1: esdhc1grp { 680 pinctrl_esdhc1: esdhc1grp {
681 fsl,pins = < 681 fsl,pins = <
682 MX51_PAD_SD1_CMD__SD1_ 682 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
683 MX51_PAD_SD1_CLK__SD1_ 683 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
684 MX51_PAD_SD1_DATA0__SD 684 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
685 MX51_PAD_SD1_DATA1__SD 685 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
686 MX51_PAD_SD1_DATA2__SD 686 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
687 MX51_PAD_SD1_DATA3__SD 687 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
688 /* 688 /*
689 * GPIO1_1 is not dire 689 * GPIO1_1 is not directly used by eSDHC1 in
690 * any capacity, but e 690 * any capacity, but earlier versions of RDU1
691 * used that pin as WP 691 * used that pin as WP GPIO for eSDHC3 and
692 * because of that tha 692 * because of that that pad has an external
693 * pull-up resistor. T 693 * pull-up resistor. This is problematic
694 * because out of rese 694 * because out of reset the pad is configured
695 * as ALT0 which serve 695 * as ALT0 which serves as SD1_WP, which, when
696 * pulled high by and 696 * pulled high by and external pull-up, will
697 * inhibit execution o 697 * inhibit execution of any write request to
698 * attached eMMC devic 698 * attached eMMC device.
699 * 699 *
700 * To avoid this probl 700 * To avoid this problem we configure the pad
701 * to ALT1/GPIO and av 701 * to ALT1/GPIO and avoid driving SD1_WP
702 * signal high. 702 * signal high.
703 */ 703 */
704 MX51_PAD_GPIO1_1__GPIO 704 MX51_PAD_GPIO1_1__GPIO1_1 0x0000
705 >; 705 >;
706 }; 706 };
707 707
708 pinctrl_fec: fecgrp { 708 pinctrl_fec: fecgrp {
709 fsl,pins = < 709 fsl,pins = <
710 MX51_PAD_EIM_EB2__FEC_ 710 MX51_PAD_EIM_EB2__FEC_MDIO 0x1f5
711 MX51_PAD_NANDF_D9__FEC 711 MX51_PAD_NANDF_D9__FEC_RDATA0 0x2180
712 MX51_PAD_EIM_EB3__FEC_ 712 MX51_PAD_EIM_EB3__FEC_RDATA1 0x180
713 MX51_PAD_EIM_CS2__FEC_ 713 MX51_PAD_EIM_CS2__FEC_RDATA2 0x180
714 MX51_PAD_EIM_CS3__FEC_ 714 MX51_PAD_EIM_CS3__FEC_RDATA3 0x180
715 MX51_PAD_EIM_CS4__FEC_ 715 MX51_PAD_EIM_CS4__FEC_RX_ER 0x180
716 MX51_PAD_NANDF_D11__FE 716 MX51_PAD_NANDF_D11__FEC_RX_DV 0x2084
717 MX51_PAD_EIM_CS5__FEC_ 717 MX51_PAD_EIM_CS5__FEC_CRS 0x180
718 MX51_PAD_NANDF_RB2__FE 718 MX51_PAD_NANDF_RB2__FEC_COL 0x2180
719 MX51_PAD_NANDF_RB3__FE 719 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x2180
720 MX51_PAD_NANDF_CS2__FE 720 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x2004
721 MX51_PAD_NANDF_CS3__FE 721 MX51_PAD_NANDF_CS3__FEC_MDC 0x2004
722 MX51_PAD_NANDF_D8__FEC 722 MX51_PAD_NANDF_D8__FEC_TDATA0 0x2180
723 MX51_PAD_NANDF_CS4__FE 723 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x2004
724 MX51_PAD_NANDF_CS5__FE 724 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x2004
725 MX51_PAD_NANDF_CS6__FE 725 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x2004
726 MX51_PAD_DISP2_DAT9__F 726 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004
727 MX51_PAD_DISP2_DAT13__ 727 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180
728 MX51_PAD_EIM_A20__GPIO 728 MX51_PAD_EIM_A20__GPIO2_14 0x85
729 >; 729 >;
730 }; 730 };
731 731
732 pinctrl_gpiospi0: gpiospi0grp { 732 pinctrl_gpiospi0: gpiospi0grp {
733 fsl,pins = < 733 fsl,pins = <
734 MX51_PAD_CSI2_D18__GPI 734 MX51_PAD_CSI2_D18__GPIO4_11 0x85
735 MX51_PAD_CSI2_D19__GPI 735 MX51_PAD_CSI2_D19__GPIO4_12 0x85
736 MX51_PAD_CSI2_HSYNC__G 736 MX51_PAD_CSI2_HSYNC__GPIO4_14 0x85
737 MX51_PAD_CSI2_PIXCLK__ 737 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x85
738 >; 738 >;
739 }; 739 };
740 740
741 pinctrl_i2c2: i2c2grp { 741 pinctrl_i2c2: i2c2grp {
742 fsl,pins = < 742 fsl,pins = <
743 MX51_PAD_KEY_COL4__I2C 743 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
744 MX51_PAD_KEY_COL5__I2C 744 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
745 >; 745 >;
746 }; 746 };
747 747
748 pinctrl_ipu_disp1: ipudisp1grp { 748 pinctrl_ipu_disp1: ipudisp1grp {
749 fsl,pins = < 749 fsl,pins = <
750 MX51_PAD_DISP1_DAT0__D 750 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
751 MX51_PAD_DISP1_DAT1__D 751 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
752 MX51_PAD_DISP1_DAT2__D 752 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
753 MX51_PAD_DISP1_DAT3__D 753 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
754 MX51_PAD_DISP1_DAT4__D 754 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
755 MX51_PAD_DISP1_DAT5__D 755 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
756 MX51_PAD_DISP1_DAT6__D 756 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
757 MX51_PAD_DISP1_DAT7__D 757 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
758 MX51_PAD_DISP1_DAT8__D 758 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
759 MX51_PAD_DISP1_DAT9__D 759 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
760 MX51_PAD_DISP1_DAT10__ 760 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
761 MX51_PAD_DISP1_DAT11__ 761 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
762 MX51_PAD_DISP1_DAT12__ 762 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
763 MX51_PAD_DISP1_DAT13__ 763 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
764 MX51_PAD_DISP1_DAT14__ 764 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
765 MX51_PAD_DISP1_DAT15__ 765 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
766 MX51_PAD_DISP1_DAT16__ 766 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
767 MX51_PAD_DISP1_DAT17__ 767 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
768 MX51_PAD_DISP1_DAT18__ 768 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
769 MX51_PAD_DISP1_DAT19__ 769 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
770 MX51_PAD_DISP1_DAT20__ 770 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
771 MX51_PAD_DISP1_DAT21__ 771 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
772 MX51_PAD_DISP1_DAT22__ 772 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
773 MX51_PAD_DISP1_DAT23__ 773 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
774 MX51_PAD_DI1_PIN2__DI1 774 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
775 MX51_PAD_DI1_PIN3__DI1 775 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
776 MX51_PAD_DI2_DISP_CLK_ 776 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
777 >; 777 >;
778 }; 778 };
779 779
780 pinctrl_panel: panelgrp { 780 pinctrl_panel: panelgrp {
781 fsl,pins = < 781 fsl,pins = <
782 MX51_PAD_DI1_D0_CS__GP 782 MX51_PAD_DI1_D0_CS__GPIO3_3 0x85
783 >; 783 >;
784 }; 784 };
785 785
786 pinctrl_pmic: pmicgrp { 786 pinctrl_pmic: pmicgrp {
787 fsl,pins = < 787 fsl,pins = <
788 MX51_PAD_GPIO1_4__GPIO 788 MX51_PAD_GPIO1_4__GPIO1_4 0x1e0
789 MX51_PAD_GPIO1_8__GPIO 789 MX51_PAD_GPIO1_8__GPIO1_8 0x21e2
790 >; 790 >;
791 }; 791 };
792 792
793 pinctrl_sndgate26mhz: sndgate26mhzgrp 793 pinctrl_sndgate26mhz: sndgate26mhzgrp {
794 fsl,pins = < 794 fsl,pins = <
795 MX51_PAD_CSPI1_RDY__GP 795 MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
796 >; 796 >;
797 }; 797 };
798 798
799 pinctrl_swi2c: swi2cgrp { 799 pinctrl_swi2c: swi2cgrp {
800 fsl,pins = < 800 fsl,pins = <
801 MX51_PAD_GPIO1_2__GPIO 801 MX51_PAD_GPIO1_2__GPIO1_2 0xc5
802 MX51_PAD_DI1_D1_CS__GP 802 MX51_PAD_DI1_D1_CS__GPIO3_4 0x400001f5
803 >; 803 >;
804 }; 804 };
805 805
806 pinctrl_swmdio: swmdiogrp { 806 pinctrl_swmdio: swmdiogrp {
807 fsl,pins = < 807 fsl,pins = <
808 MX51_PAD_NANDF_D14__GP 808 MX51_PAD_NANDF_D14__GPIO3_26 0x21e6
809 MX51_PAD_NANDF_D15__GP 809 MX51_PAD_NANDF_D15__GPIO3_25 0x21e6
810 >; 810 >;
811 }; 811 };
812 812
813 pinctrl_ts: tsgrp { 813 pinctrl_ts: tsgrp {
814 fsl,pins = < 814 fsl,pins = <
815 MX51_PAD_CSI1_D8__GPIO 815 MX51_PAD_CSI1_D8__GPIO3_12 0x04
816 MX51_PAD_CSI1_D9__GPIO 816 MX51_PAD_CSI1_D9__GPIO3_13 0x85
817 >; 817 >;
818 }; 818 };
819 819
820 pinctrl_uart1: uart1grp { 820 pinctrl_uart1: uart1grp {
821 fsl,pins = < 821 fsl,pins = <
822 MX51_PAD_UART1_RXD__UA 822 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
823 MX51_PAD_UART1_TXD__UA 823 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
824 MX51_PAD_UART1_RTS__UA 824 MX51_PAD_UART1_RTS__UART1_RTS 0x1c4
825 MX51_PAD_UART1_CTS__UA 825 MX51_PAD_UART1_CTS__UART1_CTS 0x1c4
826 >; 826 >;
827 }; 827 };
828 828
829 pinctrl_uart2: uart2grp { 829 pinctrl_uart2: uart2grp {
830 fsl,pins = < 830 fsl,pins = <
831 MX51_PAD_UART2_RXD__UA 831 MX51_PAD_UART2_RXD__UART2_RXD 0xc5
832 MX51_PAD_UART2_TXD__UA 832 MX51_PAD_UART2_TXD__UART2_TXD 0xc5
833 >; 833 >;
834 }; 834 };
835 835
836 pinctrl_uart3: uart3grp { 836 pinctrl_uart3: uart3grp {
837 fsl,pins = < 837 fsl,pins = <
838 MX51_PAD_EIM_D25__UART 838 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
839 MX51_PAD_EIM_D26__UART 839 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
840 >; 840 >;
841 }; 841 };
842 842
843 pinctrl_usbgate26mhz: usbgate26mhzgrp 843 pinctrl_usbgate26mhz: usbgate26mhzgrp {
844 fsl,pins = < 844 fsl,pins = <
845 MX51_PAD_DISP2_DAT6__G 845 MX51_PAD_DISP2_DAT6__GPIO1_19 0x85
846 >; 846 >;
847 }; 847 };
848 848
849 pinctrl_usbh1: usbh1grp { 849 pinctrl_usbh1: usbh1grp {
850 fsl,pins = < 850 fsl,pins = <
851 MX51_PAD_USBH1_STP__US 851 MX51_PAD_USBH1_STP__USBH1_STP 0x0
852 MX51_PAD_USBH1_CLK__US 852 MX51_PAD_USBH1_CLK__USBH1_CLK 0x0
853 MX51_PAD_USBH1_DIR__US 853 MX51_PAD_USBH1_DIR__USBH1_DIR 0x0
854 MX51_PAD_USBH1_NXT__US 854 MX51_PAD_USBH1_NXT__USBH1_NXT 0x0
855 MX51_PAD_USBH1_DATA0__ 855 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x0
856 MX51_PAD_USBH1_DATA1__ 856 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x0
857 MX51_PAD_USBH1_DATA2__ 857 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x0
858 MX51_PAD_USBH1_DATA3__ 858 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x0
859 MX51_PAD_USBH1_DATA4__ 859 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x0
860 MX51_PAD_USBH1_DATA5__ 860 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x0
861 MX51_PAD_USBH1_DATA6__ 861 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x0
862 MX51_PAD_USBH1_DATA7__ 862 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x0
863 >; 863 >;
864 }; 864 };
865 865
866 pinctrl_usbh1phy: usbh1phygrp { 866 pinctrl_usbh1phy: usbh1phygrp {
867 fsl,pins = < 867 fsl,pins = <
868 MX51_PAD_NANDF_D0__GPI 868 MX51_PAD_NANDF_D0__GPIO4_8 0x85
869 >; 869 >;
870 }; 870 };
871 871
872 pinctrl_usbh2: usbh2grp { 872 pinctrl_usbh2: usbh2grp {
873 fsl,pins = < 873 fsl,pins = <
874 MX51_PAD_EIM_A26__USBH 874 MX51_PAD_EIM_A26__USBH2_STP 0x0
875 MX51_PAD_EIM_A24__USBH 875 MX51_PAD_EIM_A24__USBH2_CLK 0x0
876 MX51_PAD_EIM_A25__USBH 876 MX51_PAD_EIM_A25__USBH2_DIR 0x0
877 MX51_PAD_EIM_A27__USBH 877 MX51_PAD_EIM_A27__USBH2_NXT 0x0
878 MX51_PAD_EIM_D16__USBH 878 MX51_PAD_EIM_D16__USBH2_DATA0 0x0
879 MX51_PAD_EIM_D17__USBH 879 MX51_PAD_EIM_D17__USBH2_DATA1 0x0
880 MX51_PAD_EIM_D18__USBH 880 MX51_PAD_EIM_D18__USBH2_DATA2 0x0
881 MX51_PAD_EIM_D19__USBH 881 MX51_PAD_EIM_D19__USBH2_DATA3 0x0
882 MX51_PAD_EIM_D20__USBH 882 MX51_PAD_EIM_D20__USBH2_DATA4 0x0
883 MX51_PAD_EIM_D21__USBH 883 MX51_PAD_EIM_D21__USBH2_DATA5 0x0
884 MX51_PAD_EIM_D22__USBH 884 MX51_PAD_EIM_D22__USBH2_DATA6 0x0
885 MX51_PAD_EIM_D23__USBH 885 MX51_PAD_EIM_D23__USBH2_DATA7 0x0
886 >; 886 >;
887 }; 887 };
888 888
889 pinctrl_usbh2phy: usbh2phygrp { 889 pinctrl_usbh2phy: usbh2phygrp {
890 fsl,pins = < 890 fsl,pins = <
891 MX51_PAD_NANDF_D1__GPI 891 MX51_PAD_NANDF_D1__GPIO4_7 0x85
892 >; 892 >;
893 }; 893 };
894 }; 894 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.