1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+ 2 // 2 // 3 // Copyright 2023 Linaro Ltd. 3 // Copyright 2023 Linaro Ltd. 4 4 5 /dts-v1/; 5 /dts-v1/; 6 6 7 #include <dt-bindings/pwm/pwm.h> 7 #include <dt-bindings/pwm/pwm.h> 8 #include "imx53-sk-imx53-atm0700d4.dtsi" 8 #include "imx53-sk-imx53-atm0700d4.dtsi" 9 9 10 / { 10 / { 11 display: disp0 { 11 display: disp0 { 12 compatible = "fsl,imx-parallel 12 compatible = "fsl,imx-parallel-display"; 13 interface-pix-fmt = "rgb24"; 13 interface-pix-fmt = "rgb24"; 14 pinctrl-0 = <&pinctrl_rgb24>; 14 pinctrl-0 = <&pinctrl_rgb24>; 15 pinctrl-names = "default"; 15 pinctrl-names = "default"; 16 16 17 #address-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 18 #size-cells = <0>; 19 19 20 port@0 { 20 port@0 { 21 reg = <0>; 21 reg = <0>; 22 22 23 display0_in: endpoint 23 display0_in: endpoint { 24 remote-endpoin 24 remote-endpoint = <&ipu_di0_disp0>; 25 }; 25 }; 26 }; 26 }; 27 27 28 port@1 { 28 port@1 { 29 reg = <1>; 29 reg = <1>; 30 30 31 display_out: endpoint 31 display_out: endpoint { 32 remote-endpoin 32 remote-endpoint = <&panel_rgb_in>; 33 }; 33 }; 34 }; 34 }; 35 }; 35 }; 36 36 37 }; 37 }; 38 38 39 &iomuxc { 39 &iomuxc { 40 pinctrl_rgb24: rgb24grp { 40 pinctrl_rgb24: rgb24grp { 41 fsl,pins = < 41 fsl,pins = < 42 MX53_PAD_DI0_DISP_CLK_ 42 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 43 MX53_PAD_DI0_PIN15__IP 43 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 44 MX53_PAD_DI0_PIN2__IPU 44 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 45 MX53_PAD_DI0_PIN3__IPU 45 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 46 MX53_PAD_DISP0_DAT0__I 46 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 47 MX53_PAD_DISP0_DAT1__I 47 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 48 MX53_PAD_DISP0_DAT2__I 48 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 49 MX53_PAD_DISP0_DAT3__I 49 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 50 MX53_PAD_DISP0_DAT4__I 50 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 51 MX53_PAD_DISP0_DAT5__I 51 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 52 MX53_PAD_DISP0_DAT6__I 52 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 53 MX53_PAD_DISP0_DAT7__I 53 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 54 MX53_PAD_DISP0_DAT8__I 54 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 55 MX53_PAD_DISP0_DAT9__I 55 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 56 MX53_PAD_DISP0_DAT10__ 56 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 57 MX53_PAD_DISP0_DAT11__ 57 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 58 MX53_PAD_DISP0_DAT12__ 58 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 59 MX53_PAD_DISP0_DAT13__ 59 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 60 MX53_PAD_DISP0_DAT14__ 60 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 61 MX53_PAD_DISP0_DAT15__ 61 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 62 MX53_PAD_DISP0_DAT16__ 62 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 63 MX53_PAD_DISP0_DAT17__ 63 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 64 MX53_PAD_DISP0_DAT18__ 64 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 65 MX53_PAD_DISP0_DAT19__ 65 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 66 MX53_PAD_DISP0_DAT20__ 66 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 67 MX53_PAD_DISP0_DAT21__ 67 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 68 MX53_PAD_DISP0_DAT22__ 68 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 69 MX53_PAD_DISP0_DAT23__ 69 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 70 >; 70 >; 71 }; 71 }; 72 72 73 pinctrl_spi_gpio: spigrp { 73 pinctrl_spi_gpio: spigrp { 74 fsl,pins = < 74 fsl,pins = < 75 MX53_PAD_SD1_DATA1__GP 75 MX53_PAD_SD1_DATA1__GPIO1_17 0x1f4 76 MX53_PAD_GPIO_7__GPIO1 76 MX53_PAD_GPIO_7__GPIO1_7 0x1f4 77 MX53_PAD_PATA_DATA3__G 77 MX53_PAD_PATA_DATA3__GPIO2_3 0x1f4 78 MX53_PAD_PATA_DATA8__G 78 MX53_PAD_PATA_DATA8__GPIO2_8 0x1f4 79 >; 79 >; 80 }; 80 }; 81 }; 81 }; 82 82 83 &ipu_di0_disp0 { 83 &ipu_di0_disp0 { 84 remote-endpoint = <&display0_in>; 84 remote-endpoint = <&display0_in>; 85 }; 85 }; 86 86 87 &panel { 87 &panel { 88 enable-gpios = <&gpio1 9 GPIO_ACTIVE_H 88 enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 89 }; 89 }; 90 90 91 &panel_rgb_in { 91 &panel_rgb_in { 92 remote-endpoint = <&display_out>; 92 remote-endpoint = <&display_out>; 93 }; 93 }; 94 94 95 &pwm1 { 95 &pwm1 { 96 status = "disabled"; 96 status = "disabled"; 97 }; 97 }; 98 98 99 &spi_ts { 99 &spi_ts { 100 pinctrl-0 = <&pinctrl_spi_gpio>; 100 pinctrl-0 = <&pinctrl_spi_gpio>; 101 pinctrl-names = "default"; 101 pinctrl-names = "default"; 102 102 103 sck-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH 103 sck-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 104 mosi-gpios = <&gpio2 3 GPIO_ACTIVE_HIG 104 mosi-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 105 miso-gpios = <&gpio1 17 GPIO_ACTIVE_HI 105 miso-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 106 cs-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH> 106 cs-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 107 }; 107 }; 108 108 109 &touchscreen { 109 &touchscreen { 110 interrupts-extended = <&gpio2 6 IRQ_TY 110 interrupts-extended = <&gpio2 6 IRQ_TYPE_EDGE_BOTH>; 111 pendown-gpio = <&gpio2 6 GPIO_ACTIVE_L 111 pendown-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; 112 }; 112 };
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