1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 // 2 //
3 // Copyright 2011 Freescale Semiconductor, Inc 3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd. 4 // Copyright 2011 Linaro Ltd.
5 5
6 #include "imx53-pinfunc.h" 6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h> 7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 11
12 / { 12 / {
13 #address-cells = <1>; 13 #address-cells = <1>;
14 #size-cells = <1>; 14 #size-cells = <1>;
15 /* 15 /*
16 * The decompressor and also some boot 16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be ava 17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS 18 * command line and merge other ATAGS info.
19 */ 19 */
20 chosen {}; 20 chosen {};
21 21
22 aliases { 22 aliases {
23 ethernet0 = &fec; 23 ethernet0 = &fec;
24 gpio0 = &gpio1; 24 gpio0 = &gpio1;
25 gpio1 = &gpio2; 25 gpio1 = &gpio2;
26 gpio2 = &gpio3; 26 gpio2 = &gpio3;
27 gpio3 = &gpio4; 27 gpio3 = &gpio4;
28 gpio4 = &gpio5; 28 gpio4 = &gpio5;
29 gpio5 = &gpio6; 29 gpio5 = &gpio6;
30 gpio6 = &gpio7; 30 gpio6 = &gpio7;
31 i2c0 = &i2c1; 31 i2c0 = &i2c1;
32 i2c1 = &i2c2; 32 i2c1 = &i2c2;
33 i2c2 = &i2c3; 33 i2c2 = &i2c3;
34 ipu0 = &ipu; 34 ipu0 = &ipu;
35 mmc0 = &esdhc1; 35 mmc0 = &esdhc1;
36 mmc1 = &esdhc2; 36 mmc1 = &esdhc2;
37 mmc2 = &esdhc3; 37 mmc2 = &esdhc3;
38 mmc3 = &esdhc4; 38 mmc3 = &esdhc4;
39 serial0 = &uart1; 39 serial0 = &uart1;
40 serial1 = &uart2; 40 serial1 = &uart2;
41 serial2 = &uart3; 41 serial2 = &uart3;
42 serial3 = &uart4; 42 serial3 = &uart4;
43 serial4 = &uart5; 43 serial4 = &uart5;
44 spi0 = &ecspi1; 44 spi0 = &ecspi1;
45 spi1 = &ecspi2; 45 spi1 = &ecspi2;
46 spi2 = &cspi; 46 spi2 = &cspi;
47 }; 47 };
48 48
49 cpus { 49 cpus {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 cpu0: cpu@0 { 52 cpu0: cpu@0 {
53 device_type = "cpu"; 53 device_type = "cpu";
54 compatible = "arm,cort 54 compatible = "arm,cortex-a8";
55 reg = <0x0>; 55 reg = <0x0>;
56 clocks = <&clks IMX5_C 56 clocks = <&clks IMX5_CLK_ARM>;
57 clock-latency = <61036 57 clock-latency = <61036>;
58 voltage-tolerance = <5 58 voltage-tolerance = <5>;
59 operating-points = < 59 operating-points = <
60 /* kHz */ 60 /* kHz */
61 166666 85000 61 166666 850000
62 400000 90000 62 400000 900000
63 800000 105000 63 800000 1050000
64 1000000 120000 64 1000000 1200000
65 1200000 130000 65 1200000 1300000
66 >; 66 >;
67 }; 67 };
68 }; 68 };
69 69
70 display-subsystem { 70 display-subsystem {
71 compatible = "fsl,imx-display- 71 compatible = "fsl,imx-display-subsystem";
72 ports = <&ipu_di0>, <&ipu_di1> 72 ports = <&ipu_di0>, <&ipu_di1>;
73 }; 73 };
74 74
75 capture_subsystem { 75 capture_subsystem {
76 compatible = "fsl,imx-capture- 76 compatible = "fsl,imx-capture-subsystem";
77 ports = <&ipu_csi0>, <&ipu_csi 77 ports = <&ipu_csi0>, <&ipu_csi1>;
78 }; 78 };
79 79
80 tzic: tz-interrupt-controller@fffc000 80 tzic: tz-interrupt-controller@fffc000 {
81 compatible = "fsl,imx53-tzic", 81 compatible = "fsl,imx53-tzic", "fsl,tzic";
82 interrupt-controller; 82 interrupt-controller;
83 #interrupt-cells = <1>; 83 #interrupt-cells = <1>;
84 reg = <0x0fffc000 0x4000>; 84 reg = <0x0fffc000 0x4000>;
85 }; 85 };
86 86
87 clocks { 87 clocks {
88 ckil { 88 ckil {
89 compatible = "fixed-cl 89 compatible = "fixed-clock";
90 #clock-cells = <0>; 90 #clock-cells = <0>;
91 clock-frequency = <327 91 clock-frequency = <32768>;
92 }; 92 };
93 93
94 ckih1 { 94 ckih1 {
95 compatible = "fixed-cl 95 compatible = "fixed-clock";
96 #clock-cells = <0>; 96 #clock-cells = <0>;
97 clock-frequency = <225 97 clock-frequency = <22579200>;
98 }; 98 };
99 99
100 ckih2 { 100 ckih2 {
101 compatible = "fixed-cl 101 compatible = "fixed-clock";
102 #clock-cells = <0>; 102 #clock-cells = <0>;
103 clock-frequency = <0>; 103 clock-frequency = <0>;
104 }; 104 };
105 105
106 osc { 106 osc {
107 compatible = "fixed-cl 107 compatible = "fixed-clock";
108 #clock-cells = <0>; 108 #clock-cells = <0>;
109 clock-frequency = <240 109 clock-frequency = <24000000>;
110 }; 110 };
111 }; 111 };
112 112
113 pmu: pmu { 113 pmu: pmu {
114 compatible = "arm,cortex-a8-pm 114 compatible = "arm,cortex-a8-pmu";
115 interrupt-parent = <&tzic>; 115 interrupt-parent = <&tzic>;
116 interrupts = <77>; 116 interrupts = <77>;
117 }; 117 };
118 118
119 usbphy0: usbphy-0 { 119 usbphy0: usbphy-0 {
120 compatible = "usb-nop-xceiv"; 120 compatible = "usb-nop-xceiv";
121 clocks = <&clks IMX5_CLK_USB_P 121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clock-names = "main_clk"; 122 clock-names = "main_clk";
123 #phy-cells = <0>; 123 #phy-cells = <0>;
124 status = "okay"; 124 status = "okay";
125 }; 125 };
126 126
127 usbphy1: usbphy-1 { 127 usbphy1: usbphy-1 {
128 compatible = "usb-nop-xceiv"; 128 compatible = "usb-nop-xceiv";
129 clocks = <&clks IMX5_CLK_USB_P 129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
130 clock-names = "main_clk"; 130 clock-names = "main_clk";
131 #phy-cells = <0>; 131 #phy-cells = <0>;
132 status = "okay"; 132 status = "okay";
133 }; 133 };
134 134
135 soc: soc { 135 soc: soc {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <1>; 137 #size-cells = <1>;
138 compatible = "simple-bus"; 138 compatible = "simple-bus";
139 interrupt-parent = <&tzic>; 139 interrupt-parent = <&tzic>;
140 ranges; 140 ranges;
141 141
142 sata: sata@10000000 { 142 sata: sata@10000000 {
143 compatible = "fsl,imx5 143 compatible = "fsl,imx53-ahci";
144 reg = <0x10000000 0x10 144 reg = <0x10000000 0x1000>;
145 interrupts = <28>; 145 interrupts = <28>;
146 clocks = <&clks IMX5_C 146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_C 147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_C 148 <&clks IMX5_CLK_AHB>;
149 clock-names = "sata", 149 clock-names = "sata", "sata_ref", "ahb";
150 status = "disabled"; 150 status = "disabled";
151 }; 151 };
152 152
153 ipu: ipu@18000000 { 153 ipu: ipu@18000000 {
154 #address-cells = <1>; 154 #address-cells = <1>;
155 #size-cells = <0>; 155 #size-cells = <0>;
156 compatible = "fsl,imx5 156 compatible = "fsl,imx53-ipu";
157 reg = <0x18000000 0x08 157 reg = <0x18000000 0x08000000>;
158 interrupts = <11 10>; 158 interrupts = <11 10>;
159 clocks = <&clks IMX5_C 159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_C 160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_C 161 <&clks IMX5_CLK_IPU_DI1_GATE>;
162 clock-names = "bus", " 162 clock-names = "bus", "di0", "di1";
163 resets = <&src 2>; 163 resets = <&src 2>;
164 164
165 ipu_csi0: port@0 { 165 ipu_csi0: port@0 {
166 reg = <0>; 166 reg = <0>;
167 167
168 ipu_csi0_from_ 168 ipu_csi0_from_parallel_sensor: endpoint {
169 }; 169 };
170 }; 170 };
171 171
172 ipu_csi1: port@1 { 172 ipu_csi1: port@1 {
173 reg = <1>; 173 reg = <1>;
174 174
175 ipu_csi1_from_ 175 ipu_csi1_from_parallel_sensor: endpoint {
176 }; 176 };
177 }; 177 };
178 178
179 ipu_di0: port@2 { 179 ipu_di0: port@2 {
180 #address-cells 180 #address-cells = <1>;
181 #size-cells = 181 #size-cells = <0>;
182 reg = <2>; 182 reg = <2>;
183 183
184 ipu_di0_disp0: 184 ipu_di0_disp0: endpoint@0 {
185 reg = 185 reg = <0>;
186 }; 186 };
187 187
188 ipu_di0_lvds0: 188 ipu_di0_lvds0: endpoint@1 {
189 reg = 189 reg = <1>;
190 remote 190 remote-endpoint = <&lvds0_in>;
191 }; 191 };
192 }; 192 };
193 193
194 ipu_di1: port@3 { 194 ipu_di1: port@3 {
195 #address-cells 195 #address-cells = <1>;
196 #size-cells = 196 #size-cells = <0>;
197 reg = <3>; 197 reg = <3>;
198 198
199 ipu_di1_disp1: 199 ipu_di1_disp1: endpoint@0 {
200 reg = 200 reg = <0>;
201 }; 201 };
202 202
203 ipu_di1_lvds1: 203 ipu_di1_lvds1: endpoint@1 {
204 reg = 204 reg = <1>;
205 remote 205 remote-endpoint = <&lvds1_in>;
206 }; 206 };
207 207
208 ipu_di1_tve: e 208 ipu_di1_tve: endpoint@2 {
209 reg = 209 reg = <2>;
210 remote 210 remote-endpoint = <&tve_in>;
211 }; 211 };
212 }; 212 };
213 }; 213 };
214 214
215 gpu: gpu@30000000 { 215 gpu: gpu@30000000 {
216 compatible = "amd,imag 216 compatible = "amd,imageon-200.0", "amd,imageon";
217 reg = <0x30000000 0x20 217 reg = <0x30000000 0x20000>;
218 reg-names = "kgsl_3d0_ 218 reg-names = "kgsl_3d0_reg_memory";
219 interrupts = <12>; 219 interrupts = <12>;
220 interrupt-names = "kgs 220 interrupt-names = "kgsl_3d0_irq";
221 clocks = <&clks IMX5_C 221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
222 clock-names = "core_cl 222 clock-names = "core_clk", "mem_iface_clk";
223 }; 223 };
224 224
225 aips1: bus@50000000 { /* AIPS1 225 aips1: bus@50000000 { /* AIPS1 */
226 compatible = "fsl,aips 226 compatible = "fsl,aips-bus", "simple-bus";
227 #address-cells = <1>; 227 #address-cells = <1>;
228 #size-cells = <1>; 228 #size-cells = <1>;
229 reg = <0x50000000 0x10 229 reg = <0x50000000 0x10000000>;
230 ranges; 230 ranges;
231 231
232 spba-bus@50000000 { 232 spba-bus@50000000 {
233 compatible = " 233 compatible = "fsl,spba-bus", "simple-bus";
234 #address-cells 234 #address-cells = <1>;
235 #size-cells = 235 #size-cells = <1>;
236 reg = <0x50000 236 reg = <0x50000000 0x40000>;
237 ranges; 237 ranges;
238 238
239 esdhc1: mmc@50 239 esdhc1: mmc@50004000 {
240 compat 240 compatible = "fsl,imx53-esdhc";
241 reg = 241 reg = <0x50004000 0x4000>;
242 interr 242 interrupts = <1>;
243 clocks 243 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
244 244 <&clks IMX5_CLK_DUMMY>,
245 245 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
246 clock- 246 clock-names = "ipg", "ahb", "per";
247 bus-wi 247 bus-width = <4>;
248 status 248 status = "disabled";
249 }; 249 };
250 250
251 esdhc2: mmc@50 251 esdhc2: mmc@50008000 {
252 compat 252 compatible = "fsl,imx53-esdhc";
253 reg = 253 reg = <0x50008000 0x4000>;
254 interr 254 interrupts = <2>;
255 clocks 255 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
256 256 <&clks IMX5_CLK_DUMMY>,
257 257 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
258 clock- 258 clock-names = "ipg", "ahb", "per";
259 bus-wi 259 bus-width = <4>;
260 status 260 status = "disabled";
261 }; 261 };
262 262
263 uart3: serial@ 263 uart3: serial@5000c000 {
264 compat 264 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
265 reg = 265 reg = <0x5000c000 0x4000>;
266 interr 266 interrupts = <33>;
267 clocks 267 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
268 268 <&clks IMX5_CLK_UART3_PER_GATE>;
269 clock- 269 clock-names = "ipg", "per";
270 dmas = 270 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
271 dma-na 271 dma-names = "rx", "tx";
272 status 272 status = "disabled";
273 }; 273 };
274 274
275 ecspi1: spi@50 275 ecspi1: spi@50010000 {
276 #addre 276 #address-cells = <1>;
277 #size- 277 #size-cells = <0>;
278 compat 278 compatible = "fsl,imx53-ecspi";
279 reg = 279 reg = <0x50010000 0x4000>;
280 interr 280 interrupts = <36>;
281 clocks 281 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
282 282 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
283 clock- 283 clock-names = "ipg", "per";
284 status 284 status = "disabled";
285 }; 285 };
286 286
287 ssi2: ssi@5001 287 ssi2: ssi@50014000 {
288 #sound 288 #sound-dai-cells = <0>;
289 compat 289 compatible = "fsl,imx53-ssi",
290 290 "fsl,imx51-ssi",
291 291 "fsl,imx21-ssi";
292 reg = 292 reg = <0x50014000 0x4000>;
293 interr 293 interrupts = <30>;
294 clocks 294 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
295 295 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
296 clock- 296 clock-names = "ipg", "baud";
297 dmas = 297 dmas = <&sdma 24 1 0>,
298 298 <&sdma 25 1 0>;
299 dma-na 299 dma-names = "rx", "tx";
300 fsl,fi 300 fsl,fifo-depth = <15>;
301 status 301 status = "disabled";
302 }; 302 };
303 303
304 esdhc3: mmc@50 304 esdhc3: mmc@50020000 {
305 compat 305 compatible = "fsl,imx53-esdhc";
306 reg = 306 reg = <0x50020000 0x4000>;
307 interr 307 interrupts = <3>;
308 clocks 308 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
309 309 <&clks IMX5_CLK_DUMMY>,
310 310 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
311 clock- 311 clock-names = "ipg", "ahb", "per";
312 bus-wi 312 bus-width = <4>;
313 status 313 status = "disabled";
314 }; 314 };
315 315
316 esdhc4: mmc@50 316 esdhc4: mmc@50024000 {
317 compat 317 compatible = "fsl,imx53-esdhc";
318 reg = 318 reg = <0x50024000 0x4000>;
319 interr 319 interrupts = <4>;
320 clocks 320 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
321 321 <&clks IMX5_CLK_DUMMY>,
322 322 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
323 clock- 323 clock-names = "ipg", "ahb", "per";
324 bus-wi 324 bus-width = <4>;
325 status 325 status = "disabled";
326 }; 326 };
327 }; 327 };
328 328
329 aipstz1: bridge@53f000 329 aipstz1: bridge@53f00000 {
330 compatible = " 330 compatible = "fsl,imx53-aipstz";
331 reg = <0x53f00 331 reg = <0x53f00000 0x60>;
332 }; 332 };
333 333
334 usbotg: usb@53f80000 { 334 usbotg: usb@53f80000 {
335 compatible = " 335 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
336 reg = <0x53f80 336 reg = <0x53f80000 0x0200>;
337 interrupts = < 337 interrupts = <18>;
338 clocks = <&clk 338 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
339 fsl,usbmisc = 339 fsl,usbmisc = <&usbmisc 0>;
340 fsl,usbphy = < 340 fsl,usbphy = <&usbphy0>;
341 status = "disa 341 status = "disabled";
342 }; 342 };
343 343
344 usbh1: usb@53f80200 { 344 usbh1: usb@53f80200 {
345 compatible = " 345 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
346 reg = <0x53f80 346 reg = <0x53f80200 0x0200>;
347 interrupts = < 347 interrupts = <14>;
348 clocks = <&clk 348 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
349 fsl,usbmisc = 349 fsl,usbmisc = <&usbmisc 1>;
350 fsl,usbphy = < 350 fsl,usbphy = <&usbphy1>;
351 dr_mode = "hos 351 dr_mode = "host";
352 status = "disa 352 status = "disabled";
353 }; 353 };
354 354
355 usbh2: usb@53f80400 { 355 usbh2: usb@53f80400 {
356 compatible = " 356 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
357 reg = <0x53f80 357 reg = <0x53f80400 0x0200>;
358 interrupts = < 358 interrupts = <16>;
359 clocks = <&clk 359 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
360 fsl,usbmisc = 360 fsl,usbmisc = <&usbmisc 2>;
361 dr_mode = "hos 361 dr_mode = "host";
362 status = "disa 362 status = "disabled";
363 }; 363 };
364 364
365 usbh3: usb@53f80600 { 365 usbh3: usb@53f80600 {
366 compatible = " 366 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
367 reg = <0x53f80 367 reg = <0x53f80600 0x0200>;
368 interrupts = < 368 interrupts = <17>;
369 clocks = <&clk 369 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
370 fsl,usbmisc = 370 fsl,usbmisc = <&usbmisc 3>;
371 dr_mode = "hos 371 dr_mode = "host";
372 status = "disa 372 status = "disabled";
373 }; 373 };
374 374
375 usbmisc: usbmisc@53f80 375 usbmisc: usbmisc@53f80800 {
376 #index-cells = 376 #index-cells = <1>;
377 compatible = " 377 compatible = "fsl,imx53-usbmisc";
378 reg = <0x53f80 378 reg = <0x53f80800 0x200>;
379 clocks = <&clk 379 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
380 }; 380 };
381 381
382 gpio1: gpio@53f84000 { 382 gpio1: gpio@53f84000 {
383 compatible = " 383 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
384 reg = <0x53f84 384 reg = <0x53f84000 0x4000>;
385 interrupts = < 385 interrupts = <50 51>;
386 gpio-controlle 386 gpio-controller;
387 #gpio-cells = 387 #gpio-cells = <2>;
388 interrupt-cont 388 interrupt-controller;
389 #interrupt-cel 389 #interrupt-cells = <2>;
390 }; 390 };
391 391
392 gpio2: gpio@53f88000 { 392 gpio2: gpio@53f88000 {
393 compatible = " 393 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
394 reg = <0x53f88 394 reg = <0x53f88000 0x4000>;
395 interrupts = < 395 interrupts = <52 53>;
396 gpio-controlle 396 gpio-controller;
397 #gpio-cells = 397 #gpio-cells = <2>;
398 interrupt-cont 398 interrupt-controller;
399 #interrupt-cel 399 #interrupt-cells = <2>;
400 }; 400 };
401 401
402 gpio3: gpio@53f8c000 { 402 gpio3: gpio@53f8c000 {
403 compatible = " 403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
404 reg = <0x53f8c 404 reg = <0x53f8c000 0x4000>;
405 interrupts = < 405 interrupts = <54 55>;
406 gpio-controlle 406 gpio-controller;
407 #gpio-cells = 407 #gpio-cells = <2>;
408 interrupt-cont 408 interrupt-controller;
409 #interrupt-cel 409 #interrupt-cells = <2>;
410 }; 410 };
411 411
412 gpio4: gpio@53f90000 { 412 gpio4: gpio@53f90000 {
413 compatible = " 413 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
414 reg = <0x53f90 414 reg = <0x53f90000 0x4000>;
415 interrupts = < 415 interrupts = <56 57>;
416 gpio-controlle 416 gpio-controller;
417 #gpio-cells = 417 #gpio-cells = <2>;
418 interrupt-cont 418 interrupt-controller;
419 #interrupt-cel 419 #interrupt-cells = <2>;
420 }; 420 };
421 421
422 kpp: kpp@53f94000 { 422 kpp: kpp@53f94000 {
423 compatible = " 423 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
424 reg = <0x53f94 424 reg = <0x53f94000 0x4000>;
425 interrupts = < 425 interrupts = <60>;
426 clocks = <&clk 426 clocks = <&clks IMX5_CLK_DUMMY>;
427 status = "disa 427 status = "disabled";
428 }; 428 };
429 429
430 wdog1: watchdog@53f980 430 wdog1: watchdog@53f98000 {
431 compatible = " 431 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
432 reg = <0x53f98 432 reg = <0x53f98000 0x4000>;
433 interrupts = < 433 interrupts = <58>;
434 clocks = <&clk 434 clocks = <&clks IMX5_CLK_DUMMY>;
435 }; 435 };
436 436
437 wdog2: watchdog@53f9c0 437 wdog2: watchdog@53f9c000 {
438 compatible = " 438 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
439 reg = <0x53f9c 439 reg = <0x53f9c000 0x4000>;
440 interrupts = < 440 interrupts = <59>;
441 clocks = <&clk 441 clocks = <&clks IMX5_CLK_DUMMY>;
442 status = "disa 442 status = "disabled";
443 }; 443 };
444 444
445 gpt: timer@53fa0000 { 445 gpt: timer@53fa0000 {
446 compatible = " 446 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
447 reg = <0x53fa0 447 reg = <0x53fa0000 0x4000>;
448 interrupts = < 448 interrupts = <39>;
449 clocks = <&clk 449 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
450 <&clk 450 <&clks IMX5_CLK_GPT_HF_GATE>;
451 clock-names = 451 clock-names = "ipg", "per";
452 }; 452 };
453 453
454 srtc: rtc@53fa4000 { 454 srtc: rtc@53fa4000 {
455 compatible = " 455 compatible = "fsl,imx53-rtc";
456 reg = <0x53fa4 456 reg = <0x53fa4000 0x4000>;
457 interrupts = < 457 interrupts = <24>;
458 clocks = <&clk 458 clocks = <&clks IMX5_CLK_SRTC_GATE>;
459 }; 459 };
460 460
461 iomuxc: iomuxc@53fa800 461 iomuxc: iomuxc@53fa8000 {
462 compatible = " 462 compatible = "fsl,imx53-iomuxc";
463 reg = <0x53fa8 463 reg = <0x53fa8000 0x4000>;
464 }; 464 };
465 465
466 gpr: iomuxc-gpr@53fa80 466 gpr: iomuxc-gpr@53fa8000 {
467 compatible = " 467 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
468 reg = <0x53fa8 468 reg = <0x53fa8000 0xc>;
469 }; 469 };
470 470
471 ldb: ldb@53fa8008 { 471 ldb: ldb@53fa8008 {
472 #address-cells 472 #address-cells = <1>;
473 #size-cells = 473 #size-cells = <0>;
474 compatible = " 474 compatible = "fsl,imx53-ldb";
475 reg = <0x53fa8 475 reg = <0x53fa8008 0x4>;
476 gpr = <&gpr>; 476 gpr = <&gpr>;
477 clocks = <&clk 477 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
478 <&clk 478 <&clks IMX5_CLK_LDB_DI1_SEL>,
479 <&clk 479 <&clks IMX5_CLK_IPU_DI0_SEL>,
480 <&clk 480 <&clks IMX5_CLK_IPU_DI1_SEL>,
481 <&clk 481 <&clks IMX5_CLK_LDB_DI0_GATE>,
482 <&clk 482 <&clks IMX5_CLK_LDB_DI1_GATE>;
483 clock-names = 483 clock-names = "di0_pll", "di1_pll",
484 484 "di0_sel", "di1_sel",
485 485 "di0", "di1";
486 status = "disa 486 status = "disabled";
487 487
488 lvds-channel@0 488 lvds-channel@0 {
489 #addre 489 #address-cells = <1>;
490 #size- 490 #size-cells = <0>;
491 reg = 491 reg = <0>;
492 status 492 status = "disabled";
493 493
494 port@0 494 port@0 {
495 495 reg = <0>;
496 496
497 497 lvds0_in: endpoint {
498 498 remote-endpoint = <&ipu_di0_lvds0>;
499 499 };
500 }; 500 };
501 501
502 port@2 502 port@2 {
503 503 reg = <2>;
504 }; 504 };
505 }; 505 };
506 506
507 lvds-channel@1 507 lvds-channel@1 {
508 #addre 508 #address-cells = <1>;
509 #size- 509 #size-cells = <0>;
510 reg = 510 reg = <1>;
511 status 511 status = "disabled";
512 512
513 port@1 513 port@1 {
514 514 reg = <1>;
515 515
516 516 lvds1_in: endpoint {
517 517 remote-endpoint = <&ipu_di1_lvds1>;
518 518 };
519 }; 519 };
520 520
521 port@2 521 port@2 {
522 522 reg = <2>;
523 }; 523 };
524 }; 524 };
525 }; 525 };
526 526
527 pwm1: pwm@53fb4000 { 527 pwm1: pwm@53fb4000 {
528 #pwm-cells = < 528 #pwm-cells = <3>;
529 compatible = " 529 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
530 reg = <0x53fb4 530 reg = <0x53fb4000 0x4000>;
531 clocks = <&clk 531 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
532 <&clk 532 <&clks IMX5_CLK_PWM1_HF_GATE>;
533 clock-names = 533 clock-names = "ipg", "per";
534 interrupts = < 534 interrupts = <61>;
535 }; 535 };
536 536
537 pwm2: pwm@53fb8000 { 537 pwm2: pwm@53fb8000 {
538 #pwm-cells = < 538 #pwm-cells = <3>;
539 compatible = " 539 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
540 reg = <0x53fb8 540 reg = <0x53fb8000 0x4000>;
541 clocks = <&clk 541 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
542 <&clk 542 <&clks IMX5_CLK_PWM2_HF_GATE>;
543 clock-names = 543 clock-names = "ipg", "per";
544 interrupts = < 544 interrupts = <94>;
545 }; 545 };
546 546
547 uart1: serial@53fbc000 547 uart1: serial@53fbc000 {
548 compatible = " 548 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
549 reg = <0x53fbc 549 reg = <0x53fbc000 0x4000>;
550 interrupts = < 550 interrupts = <31>;
551 clocks = <&clk 551 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
552 <&clk 552 <&clks IMX5_CLK_UART1_PER_GATE>;
553 clock-names = 553 clock-names = "ipg", "per";
554 dmas = <&sdma 554 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
555 dma-names = "r 555 dma-names = "rx", "tx";
556 status = "disa 556 status = "disabled";
557 }; 557 };
558 558
559 uart2: serial@53fc0000 559 uart2: serial@53fc0000 {
560 compatible = " 560 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
561 reg = <0x53fc0 561 reg = <0x53fc0000 0x4000>;
562 interrupts = < 562 interrupts = <32>;
563 clocks = <&clk 563 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
564 <&clk 564 <&clks IMX5_CLK_UART2_PER_GATE>;
565 clock-names = 565 clock-names = "ipg", "per";
566 dmas = <&sdma 566 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
567 dma-names = "r 567 dma-names = "rx", "tx";
568 status = "disa 568 status = "disabled";
569 }; 569 };
570 570
571 can1: can@53fc8000 { 571 can1: can@53fc8000 {
572 compatible = " 572 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
573 reg = <0x53fc8 573 reg = <0x53fc8000 0x4000>;
574 interrupts = < 574 interrupts = <82>;
575 clocks = <&clk 575 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
576 <&clk 576 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
577 clock-names = 577 clock-names = "ipg", "per";
578 status = "disa 578 status = "disabled";
579 }; 579 };
580 580
581 can2: can@53fcc000 { 581 can2: can@53fcc000 {
582 compatible = " 582 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
583 reg = <0x53fcc 583 reg = <0x53fcc000 0x4000>;
584 interrupts = < 584 interrupts = <83>;
585 clocks = <&clk 585 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
586 <&clk 586 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
587 clock-names = 587 clock-names = "ipg", "per";
588 status = "disa 588 status = "disabled";
589 }; 589 };
590 590
591 src: reset-controller@ 591 src: reset-controller@53fd0000 {
592 compatible = " 592 compatible = "fsl,imx53-src", "fsl,imx51-src";
593 reg = <0x53fd0 593 reg = <0x53fd0000 0x4000>;
594 interrupts = < 594 interrupts = <75>;
595 #reset-cells = 595 #reset-cells = <1>;
596 }; 596 };
597 597
598 clks: ccm@53fd4000 { 598 clks: ccm@53fd4000 {
599 compatible = " 599 compatible = "fsl,imx53-ccm";
600 reg = <0x53fd4 600 reg = <0x53fd4000 0x4000>;
601 interrupts = < 601 interrupts = <0 71 0x04 0 72 0x04>;
602 #clock-cells = 602 #clock-cells = <1>;
603 }; 603 };
604 604
605 gpio5: gpio@53fdc000 { 605 gpio5: gpio@53fdc000 {
606 compatible = " 606 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
607 reg = <0x53fdc 607 reg = <0x53fdc000 0x4000>;
608 interrupts = < 608 interrupts = <103 104>;
609 gpio-controlle 609 gpio-controller;
610 #gpio-cells = 610 #gpio-cells = <2>;
611 interrupt-cont 611 interrupt-controller;
612 #interrupt-cel 612 #interrupt-cells = <2>;
613 }; 613 };
614 614
615 gpio6: gpio@53fe0000 { 615 gpio6: gpio@53fe0000 {
616 compatible = " 616 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
617 reg = <0x53fe0 617 reg = <0x53fe0000 0x4000>;
618 interrupts = < 618 interrupts = <105 106>;
619 gpio-controlle 619 gpio-controller;
620 #gpio-cells = 620 #gpio-cells = <2>;
621 interrupt-cont 621 interrupt-controller;
622 #interrupt-cel 622 #interrupt-cells = <2>;
623 }; 623 };
624 624
625 gpio7: gpio@53fe4000 { 625 gpio7: gpio@53fe4000 {
626 compatible = " 626 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
627 reg = <0x53fe4 627 reg = <0x53fe4000 0x4000>;
628 interrupts = < 628 interrupts = <107 108>;
629 gpio-controlle 629 gpio-controller;
630 #gpio-cells = 630 #gpio-cells = <2>;
631 interrupt-cont 631 interrupt-controller;
632 #interrupt-cel 632 #interrupt-cells = <2>;
633 }; 633 };
634 634
635 i2c3: i2c@53fec000 { 635 i2c3: i2c@53fec000 {
636 #address-cells 636 #address-cells = <1>;
637 #size-cells = 637 #size-cells = <0>;
638 compatible = " 638 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
639 reg = <0x53fec 639 reg = <0x53fec000 0x4000>;
640 interrupts = < 640 interrupts = <64>;
641 clocks = <&clk 641 clocks = <&clks IMX5_CLK_I2C3_GATE>;
642 status = "disa 642 status = "disabled";
643 }; 643 };
644 644
645 uart4: serial@53ff0000 645 uart4: serial@53ff0000 {
646 compatible = " 646 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
647 reg = <0x53ff0 647 reg = <0x53ff0000 0x4000>;
648 interrupts = < 648 interrupts = <13>;
649 clocks = <&clk 649 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
650 <&clk 650 <&clks IMX5_CLK_UART4_PER_GATE>;
651 clock-names = 651 clock-names = "ipg", "per";
652 dmas = <&sdma 652 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
653 dma-names = "r 653 dma-names = "rx", "tx";
654 status = "disa 654 status = "disabled";
655 }; 655 };
656 }; 656 };
657 657
658 aips2: bus@60000000 { /* AIP 658 aips2: bus@60000000 { /* AIPS2 */
659 compatible = "fsl,aips 659 compatible = "fsl,aips-bus", "simple-bus";
660 #address-cells = <1>; 660 #address-cells = <1>;
661 #size-cells = <1>; 661 #size-cells = <1>;
662 reg = <0x60000000 0x10 662 reg = <0x60000000 0x10000000>;
663 ranges; 663 ranges;
664 664
665 aipstz2: bridge@63f000 665 aipstz2: bridge@63f00000 {
666 compatible = " 666 compatible = "fsl,imx53-aipstz";
667 reg = <0x63f00 667 reg = <0x63f00000 0x60>;
668 }; 668 };
669 669
670 iim: efuse@63f98000 { 670 iim: efuse@63f98000 {
671 compatible = " 671 compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon";
672 reg = <0x63f98 672 reg = <0x63f98000 0x4000>;
673 interrupts = < 673 interrupts = <69>;
674 clocks = <&clk 674 clocks = <&clks IMX5_CLK_IIM_GATE>;
675 }; 675 };
676 676
677 uart5: serial@63f90000 677 uart5: serial@63f90000 {
678 compatible = " 678 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
679 reg = <0x63f90 679 reg = <0x63f90000 0x4000>;
680 interrupts = < 680 interrupts = <86>;
681 clocks = <&clk 681 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
682 <&clk 682 <&clks IMX5_CLK_UART5_PER_GATE>;
683 clock-names = 683 clock-names = "ipg", "per";
684 dmas = <&sdma 684 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
685 dma-names = "r 685 dma-names = "rx", "tx";
686 status = "disa 686 status = "disabled";
687 }; 687 };
688 688
689 tigerp: tigerp@63fa000 689 tigerp: tigerp@63fa0000 {
690 compatible = " 690 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
691 reg = <0x63fa0 691 reg = <0x63fa0000 0x28>;
692 }; 692 };
693 693
694 owire: owire@63fa4000 694 owire: owire@63fa4000 {
695 compatible = " 695 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
696 reg = <0x63fa4 696 reg = <0x63fa4000 0x4000>;
697 clocks = <&clk 697 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
698 status = "disa 698 status = "disabled";
699 }; 699 };
700 700
701 ecspi2: spi@63fac000 { 701 ecspi2: spi@63fac000 {
702 #address-cells 702 #address-cells = <1>;
703 #size-cells = 703 #size-cells = <0>;
704 compatible = " 704 compatible = "fsl,imx53-ecspi";
705 reg = <0x63fac 705 reg = <0x63fac000 0x4000>;
706 interrupts = < 706 interrupts = <37>;
707 clocks = <&clk 707 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
708 <&clk 708 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
709 clock-names = 709 clock-names = "ipg", "per";
710 status = "disa 710 status = "disabled";
711 }; 711 };
712 712
713 sdma: dma-controller@6 713 sdma: dma-controller@63fb0000 {
714 compatible = " 714 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
715 reg = <0x63fb0 715 reg = <0x63fb0000 0x4000>;
716 interrupts = < 716 interrupts = <6>;
717 clocks = <&clk 717 clocks = <&clks IMX5_CLK_SDMA_GATE>,
718 <&clk 718 <&clks IMX5_CLK_AHB>;
719 clock-names = 719 clock-names = "ipg", "ahb";
720 #dma-cells = < 720 #dma-cells = <3>;
721 fsl,sdma-ram-s 721 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
722 }; 722 };
723 723
724 cspi: spi@63fc0000 { 724 cspi: spi@63fc0000 {
725 #address-cells 725 #address-cells = <1>;
726 #size-cells = 726 #size-cells = <0>;
727 compatible = " 727 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
728 reg = <0x63fc0 728 reg = <0x63fc0000 0x4000>;
729 interrupts = < 729 interrupts = <38>;
730 clocks = <&clk 730 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
731 <&clk 731 <&clks IMX5_CLK_CSPI_IPG_GATE>;
732 clock-names = 732 clock-names = "ipg", "per";
733 status = "disa 733 status = "disabled";
734 }; 734 };
735 735
736 i2c2: i2c@63fc4000 { 736 i2c2: i2c@63fc4000 {
737 #address-cells 737 #address-cells = <1>;
738 #size-cells = 738 #size-cells = <0>;
739 compatible = " 739 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
740 reg = <0x63fc4 740 reg = <0x63fc4000 0x4000>;
741 interrupts = < 741 interrupts = <63>;
742 clocks = <&clk 742 clocks = <&clks IMX5_CLK_I2C2_GATE>;
743 status = "disa 743 status = "disabled";
744 }; 744 };
745 745
746 i2c1: i2c@63fc8000 { 746 i2c1: i2c@63fc8000 {
747 #address-cells 747 #address-cells = <1>;
748 #size-cells = 748 #size-cells = <0>;
749 compatible = " 749 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
750 reg = <0x63fc8 750 reg = <0x63fc8000 0x4000>;
751 interrupts = < 751 interrupts = <62>;
752 clocks = <&clk 752 clocks = <&clks IMX5_CLK_I2C1_GATE>;
753 status = "disa 753 status = "disabled";
754 }; 754 };
755 755
756 ssi1: ssi@63fcc000 { 756 ssi1: ssi@63fcc000 {
757 #sound-dai-cel 757 #sound-dai-cells = <0>;
758 compatible = " 758 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
759 759 "fsl,imx21-ssi";
760 reg = <0x63fcc 760 reg = <0x63fcc000 0x4000>;
761 interrupts = < 761 interrupts = <29>;
762 clocks = <&clk 762 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
763 <&clk 763 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
764 clock-names = 764 clock-names = "ipg", "baud";
765 dmas = <&sdma 765 dmas = <&sdma 28 0 0>,
766 <&sdma 766 <&sdma 29 0 0>;
767 dma-names = "r 767 dma-names = "rx", "tx";
768 fsl,fifo-depth 768 fsl,fifo-depth = <15>;
769 status = "disa 769 status = "disabled";
770 }; 770 };
771 771
772 audmux: audmux@63fd000 772 audmux: audmux@63fd0000 {
773 compatible = " 773 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
774 reg = <0x63fd0 774 reg = <0x63fd0000 0x4000>;
775 status = "disa 775 status = "disabled";
776 }; 776 };
777 777
778 nfc: nand@63fdb000 { 778 nfc: nand@63fdb000 {
779 compatible = " 779 compatible = "fsl,imx53-nand";
780 reg = <0x63fdb 780 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
781 interrupts = < 781 interrupts = <8>;
782 clocks = <&clk 782 clocks = <&clks IMX5_CLK_NFC_GATE>;
783 status = "disa 783 status = "disabled";
784 }; 784 };
785 785
786 ssi3: ssi@63fe8000 { 786 ssi3: ssi@63fe8000 {
787 #sound-dai-cel 787 #sound-dai-cells = <0>;
788 compatible = " 788 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
789 789 "fsl,imx21-ssi";
790 reg = <0x63fe8 790 reg = <0x63fe8000 0x4000>;
791 interrupts = < 791 interrupts = <96>;
792 clocks = <&clk 792 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
793 <&clk 793 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
794 clock-names = 794 clock-names = "ipg", "baud";
795 dmas = <&sdma 795 dmas = <&sdma 46 0 0>,
796 <&sdma 796 <&sdma 47 0 0>;
797 dma-names = "r 797 dma-names = "rx", "tx";
798 fsl,fifo-depth 798 fsl,fifo-depth = <15>;
799 status = "disa 799 status = "disabled";
800 }; 800 };
801 801
802 fec: ethernet@63fec000 802 fec: ethernet@63fec000 {
803 compatible = " 803 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
804 reg = <0x63fec 804 reg = <0x63fec000 0x4000>;
805 interrupts = < 805 interrupts = <87>;
806 clocks = <&clk 806 clocks = <&clks IMX5_CLK_FEC_GATE>,
807 <&clk 807 <&clks IMX5_CLK_FEC_GATE>,
808 <&clk 808 <&clks IMX5_CLK_FEC_GATE>;
809 clock-names = 809 clock-names = "ipg", "ahb", "ptp";
810 status = "disa 810 status = "disabled";
811 }; 811 };
812 812
813 tve: tve@63ff0000 { 813 tve: tve@63ff0000 {
814 compatible = " 814 compatible = "fsl,imx53-tve";
815 reg = <0x63ff0 815 reg = <0x63ff0000 0x1000>;
816 interrupts = < 816 interrupts = <92>;
817 clocks = <&clk 817 clocks = <&clks IMX5_CLK_TVE_GATE>,
818 <&clk 818 <&clks IMX5_CLK_IPU_DI1_SEL>;
819 clock-names = 819 clock-names = "tve", "di_sel";
820 status = "disa 820 status = "disabled";
821 821
822 port { 822 port {
823 tve_in 823 tve_in: endpoint {
824 824 remote-endpoint = <&ipu_di1_tve>;
825 }; 825 };
826 }; 826 };
827 }; 827 };
828 828
829 vpu: vpu@63ff4000 { 829 vpu: vpu@63ff4000 {
830 compatible = " 830 compatible = "fsl,imx53-vpu", "cnm,coda7541";
831 reg = <0x63ff4 831 reg = <0x63ff4000 0x1000>;
832 interrupts = < 832 interrupts = <9>;
833 clocks = <&clk 833 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
834 <&clk 834 <&clks IMX5_CLK_VPU_GATE>;
835 clock-names = 835 clock-names = "per", "ahb";
836 resets = <&src 836 resets = <&src 1>;
837 iram = <&ocram 837 iram = <&ocram>;
838 }; 838 };
839 839
840 sahara: crypto@63ff800 840 sahara: crypto@63ff8000 {
841 compatible = " 841 compatible = "fsl,imx53-sahara";
842 reg = <0x63ff8 842 reg = <0x63ff8000 0x4000>;
843 interrupts = < 843 interrupts = <19 20>;
844 clocks = <&clk 844 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
845 <&clk 845 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
846 clock-names = 846 clock-names = "ipg", "ahb";
847 }; 847 };
848 }; 848 };
849 849
850 ocram: sram@f8000000 { 850 ocram: sram@f8000000 {
851 compatible = "mmio-sra 851 compatible = "mmio-sram";
852 reg = <0xf8000000 0x20 852 reg = <0xf8000000 0x20000>;
853 ranges = <0 0xf8000000 853 ranges = <0 0xf8000000 0x20000>;
854 #address-cells = <1>; 854 #address-cells = <1>;
855 #size-cells = <1>; 855 #size-cells = <1>;
856 clocks = <&clks IMX5_C 856 clocks = <&clks IMX5_CLK_OCRAM>;
857 }; 857 };
858 }; 858 };
859 }; 859 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.