1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Copyright 2013 Gateworks Corporation 3 * Copyright 2013 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include "imx6q.dtsi" 7 #include "imx6q.dtsi"
8 #include "imx6qdl-gw52xx.dtsi" 8 #include "imx6qdl-gw52xx.dtsi"
9 9
10 / { 10 / {
11 model = "Gateworks Ventana i.MX6 Dual/ 11 model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
12 compatible = "gw,imx6q-gw52xx", "gw,ve 12 compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
13 }; 13 };
14 14
15 &i2c3 { 15 &i2c3 {
16 adv7180: camera@20 { 16 adv7180: camera@20 {
17 compatible = "adi,adv7180"; 17 compatible = "adi,adv7180";
18 pinctrl-names = "default"; 18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_adv7180> 19 pinctrl-0 = <&pinctrl_adv7180>;
20 reg = <0x20>; 20 reg = <0x20>;
21 powerdown-gpios = <&gpio3 31 G 21 powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
22 interrupt-parent = <&gpio3>; 22 interrupt-parent = <&gpio3>;
23 interrupts = <30 IRQ_TYPE_LEVE 23 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
24 24
25 port { 25 port {
26 adv7180_to_ipu2_csi1_m 26 adv7180_to_ipu2_csi1_mux: endpoint {
27 remote-endpoin 27 remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
28 bus-width = <8 28 bus-width = <8>;
29 }; 29 };
30 }; 30 };
31 }; 31 };
32 }; 32 };
33 33
34 &ipu2_csi1_from_ipu2_csi1_mux { 34 &ipu2_csi1_from_ipu2_csi1_mux {
35 bus-width = <8>; 35 bus-width = <8>;
36 }; 36 };
37 37
38 &ipu2_csi1_mux_from_parallel_sensor { 38 &ipu2_csi1_mux_from_parallel_sensor {
39 remote-endpoint = <&adv7180_to_ipu2_cs 39 remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
40 bus-width = <8>; 40 bus-width = <8>;
41 }; 41 };
42 42
43 &ipu2_csi1 { 43 &ipu2_csi1 {
44 pinctrl-names = "default"; 44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_ipu2_csi1>; 45 pinctrl-0 = <&pinctrl_ipu2_csi1>;
46 }; 46 };
47 47
48 &iomuxc { 48 &iomuxc {
49 pinctrl_adv7180: adv7180grp { 49 pinctrl_adv7180: adv7180grp {
50 fsl,pins = < 50 fsl,pins = <
51 MX6QDL_PAD_EIM_D30__GP 51 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
52 MX6QDL_PAD_EIM_D31__GP 52 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
53 >; 53 >;
54 }; 54 };
55 55
56 pinctrl_ipu2_csi1: ipu2_csi1grp { 56 pinctrl_ipu2_csi1: ipu2_csi1grp {
57 fsl,pins = < 57 fsl,pins = <
58 MX6QDL_PAD_EIM_EB2__IP 58 MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
59 MX6QDL_PAD_EIM_D16__IP 59 MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
60 MX6QDL_PAD_EIM_D18__IP 60 MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
61 MX6QDL_PAD_EIM_D19__IP 61 MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
62 MX6QDL_PAD_EIM_D20__IP 62 MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
63 MX6QDL_PAD_EIM_D26__IP 63 MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
64 MX6QDL_PAD_EIM_D27__IP 64 MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
65 MX6QDL_PAD_EIM_A17__IP 65 MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
66 MX6QDL_PAD_EIM_D29__IP 66 MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
67 MX6QDL_PAD_EIM_EB3__IP 67 MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
68 MX6QDL_PAD_EIM_A16__IP 68 MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
69 >; 69 >;
70 }; 70 };
71 }; 71 };
72 72
73 &sata { 73 &sata {
74 status = "okay"; 74 status = "okay";
75 }; 75 };
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