1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * Copyright 2013 Gateworks Corporation 3 * Copyright 2013 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include "imx6q.dtsi" 7 #include "imx6q.dtsi"
8 #include "imx6qdl-gw54xx.dtsi" 8 #include "imx6qdl-gw54xx.dtsi"
9 #include <dt-bindings/media/tda1997x.h> 9 #include <dt-bindings/media/tda1997x.h>
10 10
11 / { 11 / {
12 model = "Gateworks Ventana i.MX6 Dual/ 12 model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
13 compatible = "gw,imx6q-gw54xx", "gw,ve 13 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
14 14
15 sound-digital { 15 sound-digital {
16 compatible = "simple-audio-car 16 compatible = "simple-audio-card";
17 simple-audio-card,name = "tda1 17 simple-audio-card,name = "tda1997x-audio";
18 simple-audio-card,format = "i2 18 simple-audio-card,format = "i2s";
19 simple-audio-card,bitclock-mas 19 simple-audio-card,bitclock-master = <&sound_codec>;
20 simple-audio-card,frame-master 20 simple-audio-card,frame-master = <&sound_codec>;
21 21
22 sound_cpu: simple-audio-card,c 22 sound_cpu: simple-audio-card,cpu {
23 sound-dai = <&ssi2>; 23 sound-dai = <&ssi2>;
24 }; 24 };
25 25
26 sound_codec: simple-audio-card 26 sound_codec: simple-audio-card,codec {
27 sound-dai = <&hdmi_rec 27 sound-dai = <&hdmi_receiver>;
28 }; 28 };
29 }; 29 };
30 }; 30 };
31 31
32 &i2c3 { 32 &i2c3 {
33 adv7180: camera@20 { 33 adv7180: camera@20 {
34 compatible = "adi,adv7180"; 34 compatible = "adi,adv7180";
35 pinctrl-names = "default"; 35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_adv7180> 36 pinctrl-0 = <&pinctrl_adv7180>;
37 reg = <0x20>; 37 reg = <0x20>;
38 powerdown-gpios = <&gpio3 31 G 38 powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
39 interrupt-parent = <&gpio3>; 39 interrupt-parent = <&gpio3>;
40 interrupts = <30 IRQ_TYPE_LEVE 40 interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
41 41
42 port { 42 port {
43 adv7180_to_ipu2_csi1_m 43 adv7180_to_ipu2_csi1_mux: endpoint {
44 remote-endpoin 44 remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
45 bus-width = <8 45 bus-width = <8>;
46 }; 46 };
47 }; 47 };
48 }; 48 };
49 49
50 hdmi_receiver: hdmi-receiver@48 { 50 hdmi_receiver: hdmi-receiver@48 {
51 compatible = "nxp,tda19971"; 51 compatible = "nxp,tda19971";
52 pinctrl-names = "default"; 52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_tda1997x 53 pinctrl-0 = <&pinctrl_tda1997x>;
54 reg = <0x48>; 54 reg = <0x48>;
55 interrupt-parent = <&gpio1>; 55 interrupt-parent = <&gpio1>;
56 interrupts = <7 IRQ_TYPE_LEVEL 56 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
57 DOVDD-supply = <®_3p3v>; 57 DOVDD-supply = <®_3p3v>;
58 AVDD-supply = <&sw4_reg>; 58 AVDD-supply = <&sw4_reg>;
59 DVDD-supply = <&sw4_reg>; 59 DVDD-supply = <&sw4_reg>;
60 #sound-dai-cells = <0>; 60 #sound-dai-cells = <0>;
61 nxp,audout-format = "i2s"; 61 nxp,audout-format = "i2s";
62 nxp,audout-layout = <0>; 62 nxp,audout-layout = <0>;
63 nxp,audout-width = <16>; 63 nxp,audout-width = <16>;
64 nxp,audout-mclk-fs = <128>; 64 nxp,audout-mclk-fs = <128>;
65 /* 65 /*
66 * The 8bpp YUV422 semi-planar 66 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
67 * and Y[11:4] across 16bits i 67 * and Y[11:4] across 16bits in the same cycle
68 * which we map to VP[15:08]<- 68 * which we map to VP[15:08]<->CSI_DATA[19:12]
69 */ 69 */
70 nxp,vidout-portcfg = 70 nxp,vidout-portcfg =
71 /*G_Y_11_8<->VP[15:12] 71 /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
72 < TDA1997X_VP24_V15_12 72 < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
73 /*G_Y_7_4<->VP[11:08]< 73 /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
74 < TDA1997X_VP24_V11_08 74 < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
75 /*R_CR_CBCR_11_8<->VP[ 75 /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
76 < TDA1997X_VP24_V07_04 76 < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
77 /*R_CR_CBCR_7_4<->VP[0 77 /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
78 < TDA1997X_VP24_V03_00 78 < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
79 79
80 port { 80 port {
81 tda1997x_to_ipu1_csi0_ 81 tda1997x_to_ipu1_csi0_mux: endpoint {
82 remote-endpoin 82 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
83 bus-width = <1 83 bus-width = <16>;
84 hsync-active = 84 hsync-active = <1>;
85 vsync-active = 85 vsync-active = <1>;
86 data-active = 86 data-active = <1>;
87 }; 87 };
88 }; 88 };
89 }; 89 };
90 }; 90 };
91 91
92 &ipu1_csi0_from_ipu1_csi0_mux { 92 &ipu1_csi0_from_ipu1_csi0_mux {
93 bus-width = <16>; 93 bus-width = <16>;
94 }; 94 };
95 95
96 &ipu1_csi0_mux_from_parallel_sensor { 96 &ipu1_csi0_mux_from_parallel_sensor {
97 remote-endpoint = <&tda1997x_to_ipu1_c 97 remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
98 bus-width = <16>; 98 bus-width = <16>;
99 }; 99 };
100 100
101 &ipu1_csi0 { 101 &ipu1_csi0 {
102 pinctrl-names = "default"; 102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ipu1_csi0>; 103 pinctrl-0 = <&pinctrl_ipu1_csi0>;
104 }; 104 };
105 105
106 &ipu2_csi1_from_ipu2_csi1_mux { 106 &ipu2_csi1_from_ipu2_csi1_mux {
107 bus-width = <8>; 107 bus-width = <8>;
108 }; 108 };
109 109
110 &ipu2_csi1_mux_from_parallel_sensor { 110 &ipu2_csi1_mux_from_parallel_sensor {
111 remote-endpoint = <&adv7180_to_ipu2_cs 111 remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
112 bus-width = <8>; 112 bus-width = <8>;
113 }; 113 };
114 114
115 &ipu2_csi1 { 115 &ipu2_csi1 {
116 pinctrl-names = "default"; 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ipu2_csi1>; 117 pinctrl-0 = <&pinctrl_ipu2_csi1>;
118 }; 118 };
119 119
120 &sata { 120 &sata {
121 status = "okay"; 121 status = "okay";
122 }; 122 };
123 123
124 &iomuxc { 124 &iomuxc {
125 pinctrl_adv7180: adv7180grp { 125 pinctrl_adv7180: adv7180grp {
126 fsl,pins = < 126 fsl,pins = <
127 MX6QDL_PAD_EIM_D30__GP 127 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0001b0b0
128 MX6QDL_PAD_EIM_D31__GP 128 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
129 >; 129 >;
130 }; 130 };
131 131
132 pinctrl_ipu1_csi0: ipu1_csi0grp { 132 pinctrl_ipu1_csi0: ipu1_csi0grp {
133 fsl,pins = < 133 fsl,pins = <
134 MX6QDL_PAD_CSI0_DAT4__ 134 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
135 MX6QDL_PAD_CSI0_DAT5__ 135 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
136 MX6QDL_PAD_CSI0_DAT6__ 136 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
137 MX6QDL_PAD_CSI0_DAT7__ 137 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
138 MX6QDL_PAD_CSI0_DAT8__ 138 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
139 MX6QDL_PAD_CSI0_DAT9__ 139 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
140 MX6QDL_PAD_CSI0_DAT10_ 140 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
141 MX6QDL_PAD_CSI0_DAT11_ 141 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
142 MX6QDL_PAD_CSI0_DAT12_ 142 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
143 MX6QDL_PAD_CSI0_DAT13_ 143 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
144 MX6QDL_PAD_CSI0_DAT14_ 144 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
145 MX6QDL_PAD_CSI0_DAT15_ 145 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
146 MX6QDL_PAD_CSI0_DAT16_ 146 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
147 MX6QDL_PAD_CSI0_DAT17_ 147 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
148 MX6QDL_PAD_CSI0_DAT18_ 148 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
149 MX6QDL_PAD_CSI0_DAT19_ 149 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
150 MX6QDL_PAD_CSI0_MCLK__ 150 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
151 MX6QDL_PAD_CSI0_PIXCLK 151 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
152 MX6QDL_PAD_CSI0_VSYNC_ 152 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
153 >; 153 >;
154 }; 154 };
155 155
156 pinctrl_ipu2_csi1: ipu2_csi1grp { 156 pinctrl_ipu2_csi1: ipu2_csi1grp {
157 fsl,pins = < 157 fsl,pins = <
158 MX6QDL_PAD_EIM_EB2__IP 158 MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
159 MX6QDL_PAD_EIM_D16__IP 159 MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b0
160 MX6QDL_PAD_EIM_D18__IP 160 MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b0
161 MX6QDL_PAD_EIM_D19__IP 161 MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b0
162 MX6QDL_PAD_EIM_D20__IP 162 MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b0
163 MX6QDL_PAD_EIM_D26__IP 163 MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b0
164 MX6QDL_PAD_EIM_D27__IP 164 MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b0
165 MX6QDL_PAD_EIM_A17__IP 165 MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b0
166 MX6QDL_PAD_EIM_D29__IP 166 MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b0
167 MX6QDL_PAD_EIM_EB3__IP 167 MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
168 MX6QDL_PAD_EIM_A16__IP 168 MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
169 >; 169 >;
170 }; 170 };
171 171
172 pinctrl_tda1997x: tda1997xgrp { 172 pinctrl_tda1997x: tda1997xgrp {
173 fsl,pins = < 173 fsl,pins = <
174 MX6QDL_PAD_GPIO_7__GPI 174 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
175 >; 175 >;
176 }; 176 };
177 }; 177 };
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