1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright 2016-2017 3 * Copyright 2016-2017
4 * Lukasz Majewski, DENX Software Engineering, 4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "imx6q.dtsi" 9 #include "imx6q.dtsi"
10 10
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h> 12 #include <dt-bindings/pwm/pwm.h>
13 13
14 / { 14 / {
15 model = "Liebherr (LWN) monitor6 i.MX6 15 model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
16 compatible = "lwn,mccmon6", "fsl,imx6q 16 compatible = "lwn,mccmon6", "fsl,imx6q";
17 17
18 memory@10000000 { 18 memory@10000000 {
19 device_type = "memory"; 19 device_type = "memory";
20 reg = <0x10000000 0x80000000>; 20 reg = <0x10000000 0x80000000>;
21 }; 21 };
22 22
23 backlight_lvds: backlight { 23 backlight_lvds: backlight {
24 compatible = "pwm-backlight"; 24 compatible = "pwm-backlight";
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_backligh 26 pinctrl-0 = <&pinctrl_backlight>;
27 pwms = <&pwm2 0 5000000 PWM_PO 27 pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>;
28 brightness-levels = < 0 1 28 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
29 10 11 29 10 11 12 13 14 15 16 17 18 19
30 20 21 30 20 21 22 23 24 25 26 27 28 29
31 30 31 31 30 31 32 33 34 35 36 37 38 39
32 40 41 32 40 41 42 43 44 45 46 47 48 49
33 50 51 33 50 51 52 53 54 55 56 57 58 59
34 60 61 34 60 61 62 63 64 65 66 67 68 69
35 70 71 35 70 71 72 73 74 75 76 77 78 79
36 80 81 36 80 81 82 83 84 85 86 87 88 89
37 90 91 37 90 91 92 93 94 95 96 97 98 99
38 100 101 1 38 100 101 102 103 104 105 106 107 108 109
39 110 111 1 39 110 111 112 113 114 115 116 117 118 119
40 120 121 1 40 120 121 122 123 124 125 126 127 128 129
41 130 131 1 41 130 131 132 133 134 135 136 137 138 139
42 140 141 1 42 140 141 142 143 144 145 146 147 148 149
43 150 151 1 43 150 151 152 153 154 155 156 157 158 159
44 160 161 1 44 160 161 162 163 164 165 166 167 168 169
45 170 171 1 45 170 171 172 173 174 175 176 177 178 179
46 180 181 1 46 180 181 182 183 184 185 186 187 188 189
47 190 191 1 47 190 191 192 193 194 195 196 197 198 199
48 200 201 2 48 200 201 202 203 204 205 206 207 208 209
49 210 211 2 49 210 211 212 213 214 215 216 217 218 219
50 220 221 2 50 220 221 222 223 224 225 226 227 228 229
51 230 231 2 51 230 231 232 233 234 235 236 237 238 239
52 240 241 2 52 240 241 242 243 244 245 246 247 248 249
53 250 251 2 53 250 251 252 253 254 255>;
54 default-brightness-level = <50 54 default-brightness-level = <50>;
55 enable-gpios = <&gpio1 2 GPIO_ 55 enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
56 }; 56 };
57 57
58 reg_lvds: regulator-lvds { 58 reg_lvds: regulator-lvds {
59 compatible = "regulator-fixed" 59 compatible = "regulator-fixed";
60 regulator-name = "lvds_ppen"; 60 regulator-name = "lvds_ppen";
61 regulator-min-microvolt = <330 61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <330 62 regulator-max-microvolt = <3300000>;
63 regulator-boot-on; 63 regulator-boot-on;
64 pinctrl-names = "default"; 64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_reg_lvds 65 pinctrl-0 = <&pinctrl_reg_lvds>;
66 gpio = <&gpio1 19 GPIO_ACTIVE_ 66 gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>;
67 enable-active-high; 67 enable-active-high;
68 }; 68 };
69 69
70 panel-lvds0 { 70 panel-lvds0 {
71 compatible = "innolux,g121x1-l 71 compatible = "innolux,g121x1-l03";
72 backlight = <&backlight_lvds>; 72 backlight = <&backlight_lvds>;
73 power-supply = <®_lvds>; 73 power-supply = <®_lvds>;
74 74
75 port { 75 port {
76 panel_in_lvds0: endpoi 76 panel_in_lvds0: endpoint {
77 remote-endpoin 77 remote-endpoint = <&lvds0_out>;
78 }; 78 };
79 }; 79 };
80 }; 80 };
81 }; 81 };
82 82
83 &ecspi3 { 83 &ecspi3 {
84 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW> 84 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
85 pinctrl-names = "default"; 85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ 86 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
87 status = "okay"; 87 status = "okay";
88 88
89 s25sl032p: flash@0 { 89 s25sl032p: flash@0 {
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <1>; 91 #size-cells = <1>;
92 compatible = "jedec,spi-nor"; 92 compatible = "jedec,spi-nor";
93 spi-max-frequency = <40000000> 93 spi-max-frequency = <40000000>;
94 reg = <0>; 94 reg = <0>;
95 }; 95 };
96 }; 96 };
97 97
98 &fec { 98 &fec {
99 pinctrl-names = "default"; 99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_enet>; 100 pinctrl-0 = <&pinctrl_enet>;
101 phy-mode = "rgmii"; 101 phy-mode = "rgmii";
102 phy-reset-gpios = <&gpio1 27 GPIO_ACTI 102 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
103 /delete-property/ interrupts; 103 /delete-property/ interrupts;
104 interrupts-extended = <&gpio1 6 IRQ_TY 104 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
105 <&intc 0 119 IRQ 105 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
106 fsl,err006687-workaround-present; 106 fsl,err006687-workaround-present;
107 status = "okay"; 107 status = "okay";
108 }; 108 };
109 109
110 &i2c1 { 110 &i2c1 {
111 clock-frequency = <100000>; 111 clock-frequency = <100000>;
112 pinctrl-names = "default"; 112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_i2c1>; 113 pinctrl-0 = <&pinctrl_i2c1>;
114 status = "okay"; 114 status = "okay";
115 }; 115 };
116 116
117 &i2c2 { 117 &i2c2 {
118 clock-frequency = <100000>; 118 clock-frequency = <100000>;
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_i2c2>; 120 pinctrl-0 = <&pinctrl_i2c2>;
121 status = "okay"; 121 status = "okay";
122 122
123 pfuze100: pmic@8 { 123 pfuze100: pmic@8 {
124 compatible = "fsl,pfuze100"; 124 compatible = "fsl,pfuze100";
125 reg = <0x08>; 125 reg = <0x08>;
126 126
127 regulators { 127 regulators {
128 sw1a_reg: sw1ab { 128 sw1a_reg: sw1ab {
129 regulator-min- 129 regulator-min-microvolt = <300000>;
130 regulator-max- 130 regulator-max-microvolt = <1875000>;
131 regulator-boot 131 regulator-boot-on;
132 regulator-alwa 132 regulator-always-on;
133 regulator-ramp 133 regulator-ramp-delay = <6250>;
134 }; 134 };
135 135
136 sw1c_reg: sw1c { 136 sw1c_reg: sw1c {
137 regulator-min- 137 regulator-min-microvolt = <300000>;
138 regulator-max- 138 regulator-max-microvolt = <1875000>;
139 regulator-boot 139 regulator-boot-on;
140 regulator-alwa 140 regulator-always-on;
141 regulator-ramp 141 regulator-ramp-delay = <6250>;
142 }; 142 };
143 143
144 sw2_reg: sw2 { 144 sw2_reg: sw2 {
145 regulator-min- 145 regulator-min-microvolt = <800000>;
146 regulator-max- 146 regulator-max-microvolt = <3950000>;
147 regulator-boot 147 regulator-boot-on;
148 regulator-alwa 148 regulator-always-on;
149 }; 149 };
150 150
151 sw3a_reg: sw3a { 151 sw3a_reg: sw3a {
152 regulator-min- 152 regulator-min-microvolt = <400000>;
153 regulator-max- 153 regulator-max-microvolt = <1975000>;
154 regulator-boot 154 regulator-boot-on;
155 regulator-alwa 155 regulator-always-on;
156 }; 156 };
157 157
158 sw3b_reg: sw3b { 158 sw3b_reg: sw3b {
159 regulator-min- 159 regulator-min-microvolt = <400000>;
160 regulator-max- 160 regulator-max-microvolt = <1975000>;
161 regulator-boot 161 regulator-boot-on;
162 regulator-alwa 162 regulator-always-on;
163 }; 163 };
164 164
165 sw4_reg: sw4 { 165 sw4_reg: sw4 {
166 regulator-min- 166 regulator-min-microvolt = <800000>;
167 regulator-max- 167 regulator-max-microvolt = <3300000>;
168 }; 168 };
169 169
170 swbst_reg: swbst { 170 swbst_reg: swbst {
171 regulator-min- 171 regulator-min-microvolt = <5000000>;
172 regulator-max- 172 regulator-max-microvolt = <5150000>;
173 }; 173 };
174 174
175 snvs_reg: vsnvs { 175 snvs_reg: vsnvs {
176 regulator-min- 176 regulator-min-microvolt = <1000000>;
177 regulator-max- 177 regulator-max-microvolt = <3000000>;
178 regulator-boot 178 regulator-boot-on;
179 regulator-alwa 179 regulator-always-on;
180 }; 180 };
181 181
182 vref_reg: vrefddr { 182 vref_reg: vrefddr {
183 regulator-boot 183 regulator-boot-on;
184 regulator-alwa 184 regulator-always-on;
185 }; 185 };
186 186
187 vgen1_reg: vgen1 { 187 vgen1_reg: vgen1 {
188 regulator-min- 188 regulator-min-microvolt = <800000>;
189 regulator-max- 189 regulator-max-microvolt = <1550000>;
190 }; 190 };
191 191
192 vgen2_reg: vgen2 { 192 vgen2_reg: vgen2 {
193 regulator-min- 193 regulator-min-microvolt = <800000>;
194 regulator-max- 194 regulator-max-microvolt = <1550000>;
195 }; 195 };
196 196
197 vgen3_reg: vgen3 { 197 vgen3_reg: vgen3 {
198 regulator-min- 198 regulator-min-microvolt = <1800000>;
199 regulator-max- 199 regulator-max-microvolt = <3300000>;
200 }; 200 };
201 201
202 vgen4_reg: vgen4 { 202 vgen4_reg: vgen4 {
203 regulator-min- 203 regulator-min-microvolt = <1800000>;
204 regulator-max- 204 regulator-max-microvolt = <3300000>;
205 regulator-alwa 205 regulator-always-on;
206 }; 206 };
207 207
208 vgen5_reg: vgen5 { 208 vgen5_reg: vgen5 {
209 regulator-min- 209 regulator-min-microvolt = <1800000>;
210 regulator-max- 210 regulator-max-microvolt = <3300000>;
211 regulator-alwa 211 regulator-always-on;
212 }; 212 };
213 213
214 vgen6_reg: vgen6 { 214 vgen6_reg: vgen6 {
215 regulator-min- 215 regulator-min-microvolt = <1800000>;
216 regulator-max- 216 regulator-max-microvolt = <3300000>;
217 regulator-alwa 217 regulator-always-on;
218 }; 218 };
219 }; 219 };
220 }; 220 };
221 }; 221 };
222 222
223 &ldb { 223 &ldb {
224 status = "okay"; 224 status = "okay";
225 225
226 lvds0: lvds-channel@0 { 226 lvds0: lvds-channel@0 {
227 fsl,data-mapping = "spwg"; 227 fsl,data-mapping = "spwg";
228 fsl,data-width = <24>; 228 fsl,data-width = <24>;
229 status = "okay"; 229 status = "okay";
230 230
231 port@4 { 231 port@4 {
232 reg = <4>; 232 reg = <4>;
233 233
234 lvds0_out: endpoint { 234 lvds0_out: endpoint {
235 remote-endpoin 235 remote-endpoint = <&panel_in_lvds0>;
236 }; 236 };
237 }; 237 };
238 }; 238 };
239 }; 239 };
240 240
241 &pwm2 { 241 &pwm2 {
242 pinctrl-names = "default"; 242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_pwm2>; 243 pinctrl-0 = <&pinctrl_pwm2>;
244 status = "okay"; 244 status = "okay";
245 }; 245 };
246 246
247 &uart1 { 247 &uart1 {
248 pinctrl-names = "default"; 248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_uart1>; 249 pinctrl-0 = <&pinctrl_uart1>;
250 status = "okay"; 250 status = "okay";
251 }; 251 };
252 252
253 &uart4 { 253 &uart4 {
254 pinctrl-names = "default"; 254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart4>; 255 pinctrl-0 = <&pinctrl_uart4>;
256 uart-has-rtscts; 256 uart-has-rtscts;
257 status = "okay"; 257 status = "okay";
258 }; 258 };
259 259
260 &usdhc2 { 260 &usdhc2 {
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_usdhc2>; 262 pinctrl-0 = <&pinctrl_usdhc2>;
263 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 263 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
264 bus-width = <4>; 264 bus-width = <4>;
265 status = "okay"; 265 status = "okay";
266 }; 266 };
267 267
268 &usdhc3 { 268 &usdhc3 {
269 pinctrl-names = "default"; 269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_usdhc3>; 270 pinctrl-0 = <&pinctrl_usdhc3>;
271 bus-width = <8>; 271 bus-width = <8>;
272 non-removable; 272 non-removable;
273 status = "okay"; 273 status = "okay";
274 }; 274 };
275 275
276 &weim { 276 &weim {
277 pinctrl-names = "default"; 277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_weim_nor &pinctr 278 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
279 ranges = <0 0 0x08000000 0x08000000>; 279 ranges = <0 0 0x08000000 0x08000000>;
280 status = "okay"; 280 status = "okay";
281 281
282 nor@0,0 { 282 nor@0,0 {
283 compatible = "cfi-flash"; 283 compatible = "cfi-flash";
284 reg = <0 0 0x02000000>; 284 reg = <0 0 0x02000000>;
285 #address-cells = <1>; 285 #address-cells = <1>;
286 #size-cells = <1>; 286 #size-cells = <1>;
287 bank-width = <2>; 287 bank-width = <2>;
288 use-advanced-sector-protection 288 use-advanced-sector-protection;
289 fsl,weim-cs-timing = <0x006200 289 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
290 0x0000c000 0x1 290 0x0000c000 0x1404a38e 0x00000000>;
291 }; 291 };
292 }; 292 };
293 293
294 &iomuxc { 294 &iomuxc {
295 pinctrl-names = "default"; 295 pinctrl-names = "default";
296 296
297 pinctrl_backlight: dispgrp { 297 pinctrl_backlight: dispgrp {
298 fsl,pins = < 298 fsl,pins = <
299 /* BLEN_OUT */ 299 /* BLEN_OUT */
300 MX6QDL_PAD_GPIO_2__GPI 300 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
301 >; 301 >;
302 }; 302 };
303 303
304 pinctrl_ecspi3: ecspi3grp { 304 pinctrl_ecspi3: ecspi3grp {
305 fsl,pins = < 305 fsl,pins = <
306 MX6QDL_PAD_DISP0_DAT2_ 306 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
307 MX6QDL_PAD_DISP0_DAT1_ 307 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
308 MX6QDL_PAD_DISP0_DAT0_ 308 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
309 >; 309 >;
310 }; 310 };
311 311
312 pinctrl_ecspi3_cs: ecspi3csgrp { 312 pinctrl_ecspi3_cs: ecspi3csgrp {
313 fsl,pins = < 313 fsl,pins = <
314 MX6QDL_PAD_DISP0_DAT3_ 314 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000
315 >; 315 >;
316 }; 316 };
317 317
318 pinctrl_ecspi3_flwp: ecspi3flwpgrp { 318 pinctrl_ecspi3_flwp: ecspi3flwpgrp {
319 fsl,pins = < 319 fsl,pins = <
320 MX6QDL_PAD_DISP0_DAT6_ 320 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000
321 >; 321 >;
322 }; 322 };
323 323
324 pinctrl_enet: enetgrp { 324 pinctrl_enet: enetgrp {
325 fsl,pins = < 325 fsl,pins = <
326 MX6QDL_PAD_ENET_MDIO__ 326 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
327 MX6QDL_PAD_ENET_MDC__E 327 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
328 MX6QDL_PAD_RGMII_TXC__ 328 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
329 MX6QDL_PAD_RGMII_TD0__ 329 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
330 MX6QDL_PAD_RGMII_TD1__ 330 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
331 MX6QDL_PAD_RGMII_TD2__ 331 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
332 MX6QDL_PAD_RGMII_TD3__ 332 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
333 MX6QDL_PAD_RGMII_TX_CT 333 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
334 MX6QDL_PAD_ENET_REF_CL 334 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
335 MX6QDL_PAD_RGMII_RXC__ 335 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
336 MX6QDL_PAD_RGMII_RD0__ 336 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
337 MX6QDL_PAD_RGMII_RD1__ 337 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
338 MX6QDL_PAD_RGMII_RD2__ 338 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
339 MX6QDL_PAD_RGMII_RD3__ 339 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
340 MX6QDL_PAD_RGMII_RX_CT 340 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
341 MX6QDL_PAD_GPIO_16__EN 341 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
342 MX6QDL_PAD_GPIO_6__ENE 342 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
343 MX6QDL_PAD_ENET_RXD0__ 343 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
344 >; 344 >;
345 }; 345 };
346 346
347 pinctrl_i2c1: i2c1grp { 347 pinctrl_i2c1: i2c1grp {
348 fsl,pins = < 348 fsl,pins = <
349 MX6QDL_PAD_CSI0_DAT9__ 349 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
350 MX6QDL_PAD_CSI0_DAT8__ 350 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
351 >; 351 >;
352 }; 352 };
353 353
354 pinctrl_i2c2: i2c2grp { 354 pinctrl_i2c2: i2c2grp {
355 fsl,pins = < 355 fsl,pins = <
356 MX6QDL_PAD_KEY_COL3__I 356 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
357 MX6QDL_PAD_KEY_ROW3__I 357 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
358 >; 358 >;
359 }; 359 };
360 360
361 pinctrl_pwm2: pwm2grp { 361 pinctrl_pwm2: pwm2grp {
362 fsl,pins = < 362 fsl,pins = <
363 MX6QDL_PAD_GPIO_1__PWM 363 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
364 >; 364 >;
365 }; 365 };
366 366
367 pinctrl_reg_lvds: reqlvdsgrp { 367 pinctrl_reg_lvds: reqlvdsgrp {
368 fsl,pins = < 368 fsl,pins = <
369 /* LVDS_PPEN_OUT */ 369 /* LVDS_PPEN_OUT */
370 MX6QDL_PAD_SD1_DAT2__G 370 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
371 >; 371 >;
372 }; 372 };
373 373
374 pinctrl_uart1: uart1grp { 374 pinctrl_uart1: uart1grp {
375 fsl,pins = < 375 fsl,pins = <
376 MX6QDL_PAD_CSI0_DAT10_ 376 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
377 MX6QDL_PAD_CSI0_DAT11_ 377 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
378 >; 378 >;
379 }; 379 };
380 380
381 pinctrl_uart4: uart4grp { 381 pinctrl_uart4: uart4grp {
382 fsl,pins = < 382 fsl,pins = <
383 MX6QDL_PAD_KEY_COL0__U 383 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
384 MX6QDL_PAD_KEY_ROW0__U 384 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
385 MX6QDL_PAD_CSI0_DAT16_ 385 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
386 MX6QDL_PAD_CSI0_DAT17_ 386 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
387 >; 387 >;
388 }; 388 };
389 389
390 pinctrl_usdhc2: usdhc2grp { 390 pinctrl_usdhc2: usdhc2grp {
391 fsl,pins = < 391 fsl,pins = <
392 MX6QDL_PAD_SD2_CMD__SD 392 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
393 MX6QDL_PAD_SD2_CLK__SD 393 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
394 MX6QDL_PAD_SD2_DAT0__S 394 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
395 MX6QDL_PAD_SD2_DAT1__S 395 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
396 MX6QDL_PAD_SD2_DAT2__S 396 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
397 MX6QDL_PAD_SD2_DAT3__S 397 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
398 MX6QDL_PAD_GPIO_4__GPI 398 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1
399 >; 399 >;
400 }; 400 };
401 401
402 pinctrl_usdhc3: usdhc3grp { 402 pinctrl_usdhc3: usdhc3grp {
403 fsl,pins = < 403 fsl,pins = <
404 MX6QDL_PAD_SD3_CMD__SD 404 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
405 MX6QDL_PAD_SD3_CLK__SD 405 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
406 MX6QDL_PAD_SD3_DAT0__S 406 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
407 MX6QDL_PAD_SD3_DAT1__S 407 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
408 MX6QDL_PAD_SD3_DAT2__S 408 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
409 MX6QDL_PAD_SD3_DAT3__S 409 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
410 MX6QDL_PAD_SD3_DAT4__S 410 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
411 MX6QDL_PAD_SD3_DAT5__S 411 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
412 MX6QDL_PAD_SD3_DAT6__S 412 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
413 MX6QDL_PAD_SD3_DAT7__S 413 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
414 MX6QDL_PAD_SD3_RST__SD 414 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
415 >; 415 >;
416 }; 416 };
417 417
418 pinctrl_weim_cs0: weimcs0grp { 418 pinctrl_weim_cs0: weimcs0grp {
419 fsl,pins = < 419 fsl,pins = <
420 MX6QDL_PAD_EIM_CS0__EI 420 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
421 >; 421 >;
422 }; 422 };
423 423
424 pinctrl_weim_nor: weimnorgrp { 424 pinctrl_weim_nor: weimnorgrp {
425 fsl,pins = < 425 fsl,pins = <
426 MX6QDL_PAD_EIM_OE__EIM 426 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
427 MX6QDL_PAD_EIM_RW__EIM 427 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
428 MX6QDL_PAD_EIM_WAIT__E 428 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
429 MX6QDL_PAD_EIM_D16__EI 429 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
430 MX6QDL_PAD_EIM_D17__EI 430 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
431 MX6QDL_PAD_EIM_D18__EI 431 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
432 MX6QDL_PAD_EIM_D19__EI 432 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
433 MX6QDL_PAD_EIM_D20__EI 433 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
434 MX6QDL_PAD_EIM_D21__EI 434 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
435 MX6QDL_PAD_EIM_D22__EI 435 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
436 MX6QDL_PAD_EIM_D23__EI 436 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
437 MX6QDL_PAD_EIM_D24__EI 437 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
438 MX6QDL_PAD_EIM_D25__EI 438 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
439 MX6QDL_PAD_EIM_D26__EI 439 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
440 MX6QDL_PAD_EIM_D27__EI 440 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
441 MX6QDL_PAD_EIM_D28__EI 441 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
442 MX6QDL_PAD_EIM_D29__EI 442 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
443 MX6QDL_PAD_EIM_D30__EI 443 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
444 MX6QDL_PAD_EIM_D31__EI 444 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
445 MX6QDL_PAD_EIM_A23__EI 445 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
446 MX6QDL_PAD_EIM_A22__EI 446 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
447 MX6QDL_PAD_EIM_A21__EI 447 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
448 MX6QDL_PAD_EIM_A20__EI 448 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
449 MX6QDL_PAD_EIM_A19__EI 449 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
450 MX6QDL_PAD_EIM_A18__EI 450 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
451 MX6QDL_PAD_EIM_A17__EI 451 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
452 MX6QDL_PAD_EIM_A16__EI 452 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
453 MX6QDL_PAD_EIM_DA15__E 453 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
454 MX6QDL_PAD_EIM_DA14__E 454 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
455 MX6QDL_PAD_EIM_DA13__E 455 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
456 MX6QDL_PAD_EIM_DA12__E 456 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
457 MX6QDL_PAD_EIM_DA11__E 457 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
458 MX6QDL_PAD_EIM_DA10__E 458 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
459 MX6QDL_PAD_EIM_DA9__EI 459 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
460 MX6QDL_PAD_EIM_DA8__EI 460 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
461 MX6QDL_PAD_EIM_DA7__EI 461 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
462 MX6QDL_PAD_EIM_DA6__EI 462 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
463 MX6QDL_PAD_EIM_DA5__EI 463 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
464 MX6QDL_PAD_EIM_DA4__EI 464 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
465 MX6QDL_PAD_EIM_DA3__EI 465 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
466 MX6QDL_PAD_EIM_DA2__EI 466 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
467 MX6QDL_PAD_EIM_DA1__EI 467 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
468 MX6QDL_PAD_EIM_DA0__EI 468 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
469 >; 469 >;
470 }; 470 };
471 }; 471 };
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