1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright 2013 Freescale Semiconductor, Inc 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 */ 4 */ 5 5 6 #ifndef __DTS_IMX6Q_PINFUNC_H 6 #ifndef __DTS_IMX6Q_PINFUNC_H 7 #define __DTS_IMX6Q_PINFUNC_H 7 #define __DTS_IMX6Q_PINFUNC_H 8 8 9 /* 9 /* 10 * The pin function ID is a tuple of 10 * The pin function ID is a tuple of 11 * <mux_reg conf_reg input_reg mux_mode input_ 11 * <mux_reg conf_reg input_reg mux_mode input_val> 12 */ 12 */ 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 23 #define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 23 #define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 24 #define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 24 #define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 25 #define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 25 #define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 26 #define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 26 #define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 27 #define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 27 #define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 28 #define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 28 #define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 29 #define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 29 #define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 30 #define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 30 #define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 31 #define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 31 #define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 32 #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 32 #define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 33 #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 33 #define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 34 #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 34 #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 35 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_ 35 #define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 36 #define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 36 #define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 37 #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 37 #define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 38 #define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 38 #define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 39 #define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 39 #define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 40 #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 40 #define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 41 #define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 41 #define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 42 #define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 42 #define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 43 #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 43 #define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 44 #define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 44 #define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 45 #define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 45 #define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 46 #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 46 #define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 47 #define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 47 #define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 48 #define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 48 #define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 49 #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 49 #define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 50 #define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 50 #define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 51 #define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 51 #define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 52 #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 52 #define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 53 #define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 53 #define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 54 #define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 54 #define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 55 #define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 55 #define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 56 #define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 56 #define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 57 #define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 57 #define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 58 #define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 58 #define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 59 #define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 59 #define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 60 #define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 60 #define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 61 #define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 61 #define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 62 #define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 62 #define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 63 #define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 63 #define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 64 #define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 64 #define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 65 #define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 65 #define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 66 #define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 66 #define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 67 #define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 67 #define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 68 #define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 68 #define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 69 #define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 69 #define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 70 #define MX6QDL_PAD_EIM_A25__EIM_ADDR25 70 #define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 71 #define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 71 #define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 72 #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 72 #define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 73 #define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 73 #define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 74 #define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 74 #define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 75 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 75 #define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 76 #define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 76 #define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 77 #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 77 #define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 78 #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 78 #define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 79 #define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 79 #define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 80 #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 80 #define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 81 #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 81 #define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 82 #define MX6QDL_PAD_EIM_EB2__I2C2_SCL 82 #define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 83 #define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 83 #define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 84 #define MX6QDL_PAD_EIM_D16__EIM_DATA16 84 #define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 85 #define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 85 #define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 86 #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 86 #define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 87 #define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 87 #define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 88 #define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 88 #define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 89 #define MX6QDL_PAD_EIM_D16__GPIO3_IO16 89 #define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 90 #define MX6QDL_PAD_EIM_D16__I2C2_SDA 90 #define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 91 #define MX6QDL_PAD_EIM_D17__EIM_DATA17 91 #define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 92 #define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 92 #define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 93 #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 93 #define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 94 #define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 94 #define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 95 #define MX6QDL_PAD_EIM_D17__DCIC1_OUT 95 #define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 96 #define MX6QDL_PAD_EIM_D17__GPIO3_IO17 96 #define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 97 #define MX6QDL_PAD_EIM_D17__I2C3_SCL 97 #define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 98 #define MX6QDL_PAD_EIM_D18__EIM_DATA18 98 #define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 99 #define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 99 #define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 100 #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 100 #define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 101 #define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 101 #define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 102 #define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 102 #define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 103 #define MX6QDL_PAD_EIM_D18__GPIO3_IO18 103 #define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 104 #define MX6QDL_PAD_EIM_D18__I2C3_SDA 104 #define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 105 #define MX6QDL_PAD_EIM_D19__EIM_DATA19 105 #define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 106 #define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 106 #define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 107 #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 107 #define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 108 #define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 108 #define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 109 #define MX6QDL_PAD_EIM_D19__UART1_CTS_B 109 #define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 110 #define MX6QDL_PAD_EIM_D19__UART1_RTS_B 110 #define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 111 #define MX6QDL_PAD_EIM_D19__GPIO3_IO19 111 #define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 112 #define MX6QDL_PAD_EIM_D19__EPIT1_OUT 112 #define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 113 #define MX6QDL_PAD_EIM_D20__EIM_DATA20 113 #define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 114 #define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 114 #define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 115 #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 115 #define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 116 #define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 116 #define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 117 #define MX6QDL_PAD_EIM_D20__UART1_RTS_B 117 #define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 118 #define MX6QDL_PAD_EIM_D20__UART1_CTS_B 118 #define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 119 #define MX6QDL_PAD_EIM_D20__GPIO3_IO20 119 #define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 120 #define MX6QDL_PAD_EIM_D20__EPIT2_OUT 120 #define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 121 #define MX6QDL_PAD_EIM_D21__EIM_DATA21 121 #define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 122 #define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 122 #define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 123 #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 123 #define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 124 #define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 124 #define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 125 #define MX6QDL_PAD_EIM_D21__USB_OTG_OC 125 #define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 126 #define MX6QDL_PAD_EIM_D21__GPIO3_IO21 126 #define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 127 #define MX6QDL_PAD_EIM_D21__I2C1_SCL 127 #define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 128 #define MX6QDL_PAD_EIM_D21__SPDIF_IN 128 #define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 129 #define MX6QDL_PAD_EIM_D22__EIM_DATA22 129 #define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 130 #define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 130 #define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 131 #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 131 #define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 132 #define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 132 #define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 133 #define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 133 #define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 134 #define MX6QDL_PAD_EIM_D22__GPIO3_IO22 134 #define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 135 #define MX6QDL_PAD_EIM_D22__SPDIF_OUT 135 #define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 136 #define MX6QDL_PAD_EIM_D23__EIM_DATA23 136 #define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 137 #define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 137 #define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 138 #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 138 #define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 139 #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 139 #define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 140 #define MX6QDL_PAD_EIM_D23__UART1_DCD_B 140 #define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 141 #define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 141 #define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 142 #define MX6QDL_PAD_EIM_D23__GPIO3_IO23 142 #define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 143 #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 143 #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 144 #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 144 #define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 145 #define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 145 #define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 146 #define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 146 #define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 147 #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 147 #define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 148 #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 148 #define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 149 #define MX6QDL_PAD_EIM_EB3__UART1_RI_B 149 #define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 150 #define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 150 #define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 151 #define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 151 #define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 152 #define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 152 #define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 153 #define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 153 #define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 154 #define MX6QDL_PAD_EIM_D24__EIM_DATA24 154 #define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 155 #define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 155 #define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 156 #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 156 #define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 157 #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 157 #define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 158 #define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 158 #define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 159 #define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 159 #define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 160 #define MX6QDL_PAD_EIM_D24__GPIO3_IO24 160 #define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 161 #define MX6QDL_PAD_EIM_D24__AUD5_RXFS 161 #define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 162 #define MX6QDL_PAD_EIM_D24__UART1_DTR_B 162 #define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 163 #define MX6QDL_PAD_EIM_D25__EIM_DATA25 163 #define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 164 #define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 164 #define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 165 #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 165 #define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 166 #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 166 #define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 167 #define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 167 #define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 168 #define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 168 #define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 169 #define MX6QDL_PAD_EIM_D25__GPIO3_IO25 169 #define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 170 #define MX6QDL_PAD_EIM_D25__AUD5_RXC 170 #define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 171 #define MX6QDL_PAD_EIM_D25__UART1_DSR_B 171 #define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 172 #define MX6QDL_PAD_EIM_D26__EIM_DATA26 172 #define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 173 #define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 173 #define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 174 #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 174 #define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 175 #define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 175 #define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 176 #define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 176 #define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 177 #define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 177 #define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 178 #define MX6QDL_PAD_EIM_D26__GPIO3_IO26 178 #define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 179 #define MX6QDL_PAD_EIM_D26__IPU1_SISG2 179 #define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 180 #define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 180 #define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 181 #define MX6QDL_PAD_EIM_D27__EIM_DATA27 181 #define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 182 #define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 182 #define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 183 #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 183 #define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 184 #define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 184 #define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 185 #define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 185 #define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 186 #define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 186 #define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 187 #define MX6QDL_PAD_EIM_D27__GPIO3_IO27 187 #define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 188 #define MX6QDL_PAD_EIM_D27__IPU1_SISG3 188 #define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 189 #define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 189 #define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 190 #define MX6QDL_PAD_EIM_D28__EIM_DATA28 190 #define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 191 #define MX6QDL_PAD_EIM_D28__I2C1_SDA 191 #define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 192 #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 192 #define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 193 #define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 193 #define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 194 #define MX6QDL_PAD_EIM_D28__UART2_CTS_B 194 #define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 195 #define MX6QDL_PAD_EIM_D28__UART2_RTS_B 195 #define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 196 #define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 196 #define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0 197 #define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 197 #define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0 198 #define MX6QDL_PAD_EIM_D28__GPIO3_IO28 198 #define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 199 #define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 199 #define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 200 #define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 200 #define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 201 #define MX6QDL_PAD_EIM_D29__EIM_DATA29 201 #define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 202 #define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 202 #define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 203 #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 203 #define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 204 #define MX6QDL_PAD_EIM_D29__UART2_RTS_B 204 #define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 205 #define MX6QDL_PAD_EIM_D29__UART2_CTS_B 205 #define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 206 #define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 206 #define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0 207 #define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 207 #define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1 208 #define MX6QDL_PAD_EIM_D29__GPIO3_IO29 208 #define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 209 #define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 209 #define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 210 #define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 210 #define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 211 #define MX6QDL_PAD_EIM_D30__EIM_DATA30 211 #define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 212 #define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 212 #define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 213 #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 213 #define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 214 #define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 214 #define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 215 #define MX6QDL_PAD_EIM_D30__UART3_CTS_B 215 #define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 216 #define MX6QDL_PAD_EIM_D30__UART3_RTS_B 216 #define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 217 #define MX6QDL_PAD_EIM_D30__GPIO3_IO30 217 #define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 218 #define MX6QDL_PAD_EIM_D30__USB_H1_OC 218 #define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 219 #define MX6QDL_PAD_EIM_D31__EIM_DATA31 219 #define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 220 #define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 220 #define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 221 #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 221 #define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 222 #define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 222 #define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 223 #define MX6QDL_PAD_EIM_D31__UART3_RTS_B 223 #define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 224 #define MX6QDL_PAD_EIM_D31__UART3_CTS_B 224 #define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 225 #define MX6QDL_PAD_EIM_D31__GPIO3_IO31 225 #define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 226 #define MX6QDL_PAD_EIM_D31__USB_H1_PWR 226 #define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 227 #define MX6QDL_PAD_EIM_A24__EIM_ADDR24 227 #define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 228 #define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 228 #define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 229 #define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 229 #define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 230 #define MX6QDL_PAD_EIM_A24__IPU2_SISG2 230 #define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 231 #define MX6QDL_PAD_EIM_A24__IPU1_SISG2 231 #define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 232 #define MX6QDL_PAD_EIM_A24__GPIO5_IO04 232 #define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 233 #define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 233 #define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 234 #define MX6QDL_PAD_EIM_A23__EIM_ADDR23 234 #define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 235 #define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 235 #define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 236 #define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 236 #define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 237 #define MX6QDL_PAD_EIM_A23__IPU2_SISG3 237 #define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 238 #define MX6QDL_PAD_EIM_A23__IPU1_SISG3 238 #define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 239 #define MX6QDL_PAD_EIM_A23__GPIO6_IO06 239 #define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 240 #define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 240 #define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 241 #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 241 #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 242 #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 242 #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 243 #define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 243 #define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 244 #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 244 #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 245 #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 245 #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 246 #define MX6QDL_PAD_EIM_A21__EIM_ADDR21 246 #define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 247 #define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 247 #define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 248 #define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 248 #define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 249 #define MX6QDL_PAD_EIM_A21__GPIO2_IO17 249 #define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 250 #define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 250 #define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 251 #define MX6QDL_PAD_EIM_A20__EIM_ADDR20 251 #define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 252 #define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 252 #define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 253 #define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 253 #define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 254 #define MX6QDL_PAD_EIM_A20__GPIO2_IO18 254 #define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 255 #define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 255 #define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 256 #define MX6QDL_PAD_EIM_A19__EIM_ADDR19 256 #define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 257 #define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 257 #define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 258 #define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 258 #define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 259 #define MX6QDL_PAD_EIM_A19__GPIO2_IO19 259 #define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 260 #define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 260 #define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 261 #define MX6QDL_PAD_EIM_A18__EIM_ADDR18 261 #define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 262 #define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 262 #define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 263 #define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 263 #define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 264 #define MX6QDL_PAD_EIM_A18__GPIO2_IO20 264 #define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 265 #define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 265 #define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 266 #define MX6QDL_PAD_EIM_A17__EIM_ADDR17 266 #define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 267 #define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 267 #define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 268 #define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 268 #define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 269 #define MX6QDL_PAD_EIM_A17__GPIO2_IO21 269 #define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 270 #define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 270 #define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 271 #define MX6QDL_PAD_EIM_A16__EIM_ADDR16 271 #define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 272 #define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 272 #define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 273 #define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 273 #define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 274 #define MX6QDL_PAD_EIM_A16__GPIO2_IO22 274 #define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 275 #define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 275 #define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 276 #define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 276 #define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 277 #define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 277 #define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 278 #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 278 #define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 279 #define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 279 #define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 280 #define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 280 #define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 281 #define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 281 #define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 282 #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 282 #define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 283 #define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 283 #define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 284 #define MX6QDL_PAD_EIM_OE__EIM_OE_B 284 #define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 285 #define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 285 #define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 286 #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 286 #define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 287 #define MX6QDL_PAD_EIM_OE__GPIO2_IO25 287 #define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 288 #define MX6QDL_PAD_EIM_RW__EIM_RW 288 #define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 289 #define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 289 #define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 290 #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 290 #define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 291 #define MX6QDL_PAD_EIM_RW__GPIO2_IO26 291 #define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 292 #define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 292 #define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 293 #define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 293 #define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 294 #define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 294 #define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 295 #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 295 #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 296 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 296 #define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 297 #define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 297 #define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 298 #define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 298 #define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 299 #define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 299 #define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 300 #define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 300 #define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 301 #define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 301 #define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 302 #define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 302 #define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 303 #define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 303 #define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 304 #define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 304 #define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 305 #define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 305 #define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 306 #define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 306 #define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 307 #define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 307 #define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 308 #define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 308 #define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 309 #define MX6QDL_PAD_EIM_DA0__EIM_AD00 309 #define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 310 #define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 310 #define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 311 #define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 311 #define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 312 #define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 312 #define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 313 #define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 313 #define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 314 #define MX6QDL_PAD_EIM_DA1__EIM_AD01 314 #define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 315 #define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 315 #define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 316 #define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 316 #define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 317 #define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 317 #define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 318 #define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 318 #define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 319 #define MX6QDL_PAD_EIM_DA2__EIM_AD02 319 #define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 320 #define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 320 #define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 321 #define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 321 #define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 322 #define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 322 #define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 323 #define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 323 #define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 324 #define MX6QDL_PAD_EIM_DA3__EIM_AD03 324 #define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 325 #define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 325 #define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 326 #define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 326 #define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 327 #define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 327 #define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 328 #define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 328 #define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 329 #define MX6QDL_PAD_EIM_DA4__EIM_AD04 329 #define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 330 #define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 330 #define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 331 #define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 331 #define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 332 #define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 332 #define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 333 #define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 333 #define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 334 #define MX6QDL_PAD_EIM_DA5__EIM_AD05 334 #define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 335 #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 335 #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 336 #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 336 #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 337 #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 337 #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 338 #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 338 #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 339 #define MX6QDL_PAD_EIM_DA6__EIM_AD06 339 #define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 340 #define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 340 #define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 341 #define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 341 #define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 342 #define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 342 #define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 343 #define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 343 #define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 344 #define MX6QDL_PAD_EIM_DA7__EIM_AD07 344 #define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 345 #define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 345 #define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 346 #define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 346 #define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 347 #define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 347 #define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 348 #define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 348 #define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 349 #define MX6QDL_PAD_EIM_DA8__EIM_AD08 349 #define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 350 #define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 350 #define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 351 #define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 351 #define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 352 #define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 352 #define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 353 #define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 353 #define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 354 #define MX6QDL_PAD_EIM_DA9__EIM_AD09 354 #define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 355 #define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 355 #define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 356 #define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 356 #define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 357 #define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 357 #define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 358 #define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 358 #define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 359 #define MX6QDL_PAD_EIM_DA10__EIM_AD10 359 #define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 360 #define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 360 #define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 361 #define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 361 #define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 362 #define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 362 #define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 363 #define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 363 #define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 364 #define MX6QDL_PAD_EIM_DA11__EIM_AD11 364 #define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 365 #define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 365 #define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 366 #define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 366 #define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 367 #define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 367 #define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 368 #define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 368 #define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 369 #define MX6QDL_PAD_EIM_DA12__EIM_AD12 369 #define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 370 #define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 370 #define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 371 #define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 371 #define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 372 #define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 372 #define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 373 #define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 373 #define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 374 #define MX6QDL_PAD_EIM_DA13__EIM_AD13 374 #define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 375 #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 375 #define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 376 #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 376 #define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 377 #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 377 #define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 378 #define MX6QDL_PAD_EIM_DA14__EIM_AD14 378 #define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 379 #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 379 #define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 380 #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 380 #define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 381 #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 381 #define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 382 #define MX6QDL_PAD_EIM_DA15__EIM_AD15 382 #define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 383 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 383 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 384 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 384 #define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 385 #define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 385 #define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 386 #define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 386 #define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 387 #define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 387 #define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 388 #define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 388 #define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 389 #define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 389 #define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 390 #define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 390 #define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 391 #define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 391 #define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 392 #define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 392 #define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 393 #define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 393 #define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 394 #define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP 394 #define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 395 #define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP 395 #define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 396 #define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 396 #define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 397 #define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 397 #define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 398 #define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 398 #define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 399 #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 399 #define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 400 #define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 400 #define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 401 #define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 401 #define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 402 #define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 402 #define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 403 #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 403 #define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 404 #define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 404 #define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 405 #define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 405 #define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 406 #define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 406 #define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 407 #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 407 #define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 408 #define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 408 #define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 409 #define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 409 #define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 410 #define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 410 #define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 411 #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 411 #define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 412 #define MX6QDL_PAD_DI0_PIN4__SD1_WP 412 #define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 413 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 413 #define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 414 #define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA 414 #define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 415 #define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA 415 #define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 416 #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 416 #define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 417 #define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 417 #define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 418 #define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA 418 #define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 419 #define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA 419 #define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 420 #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 420 #define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 421 #define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 421 #define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 422 #define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA 422 #define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 423 #define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA 423 #define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 424 #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 424 #define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 425 #define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 425 #define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 426 #define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA 426 #define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 427 #define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA 427 #define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 428 #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 428 #define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 429 #define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 429 #define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 430 #define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA 430 #define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 431 #define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA 431 #define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 432 #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 432 #define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 433 #define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 433 #define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 434 #define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA 434 #define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 435 #define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA 435 #define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 436 #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 436 #define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 437 #define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 437 #define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 438 #define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 438 #define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 439 #define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA 439 #define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 440 #define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA 440 #define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 441 #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 441 #define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 442 #define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 442 #define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 443 #define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 443 #define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 444 #define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA 444 #define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 445 #define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA 445 #define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 446 #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 446 #define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 447 #define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 447 #define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 448 #define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA 448 #define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 449 #define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA 449 #define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 450 #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 450 #define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 451 #define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 451 #define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 452 #define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 452 #define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 453 #define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA 453 #define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 454 #define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA 454 #define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 455 #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 455 #define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 456 #define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 456 #define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 457 #define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 457 #define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 458 #define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DAT 458 #define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 459 #define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DAT 459 #define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 460 #define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 460 #define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 461 #define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DAT 461 #define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 462 #define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DAT 462 #define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 463 #define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 463 #define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 464 #define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DAT 464 #define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 465 #define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DAT 465 #define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 466 #define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 466 #define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 467 #define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DAT 467 #define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 468 #define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DAT 468 #define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 469 #define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 469 #define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 470 #define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 470 #define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 471 #define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DAT 471 #define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 472 #define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DAT 472 #define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 473 #define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 473 #define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 474 #define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 474 #define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 475 #define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DAT 475 #define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 476 #define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DAT 476 #define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 477 #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 477 #define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 478 #define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 478 #define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 479 #define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 479 #define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 480 #define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DAT 480 #define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 481 #define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DAT 481 #define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 482 #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 482 #define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 483 #define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 483 #define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 484 #define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT 484 #define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 485 #define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 485 #define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 486 #define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DAT 486 #define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 487 #define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DAT 487 #define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 488 #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 488 #define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 489 #define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 489 #define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 490 #define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT 490 #define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 491 #define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 491 #define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 492 #define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DAT 492 #define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 493 #define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DAT 493 #define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 494 #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 494 #define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 495 #define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 495 #define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 496 #define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 496 #define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 497 #define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 497 #define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 498 #define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 498 #define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 499 #define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DAT 499 #define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 500 #define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DAT 500 #define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 501 #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 501 #define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 502 #define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 502 #define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 503 #define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 503 #define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 504 #define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 504 #define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 505 #define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 505 #define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 506 #define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DAT 506 #define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 507 #define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DAT 507 #define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 508 #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 508 #define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 509 #define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 509 #define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 510 #define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 510 #define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 511 #define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DAT 511 #define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 512 #define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DAT 512 #define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 513 #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 513 #define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 514 #define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 514 #define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 515 #define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 515 #define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 516 #define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DAT 516 #define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 517 #define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DAT 517 #define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 518 #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 518 #define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 519 #define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 519 #define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 520 #define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 520 #define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 521 #define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DAT 521 #define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 522 #define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DAT 522 #define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 523 #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 523 #define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 524 #define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 524 #define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 525 #define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 525 #define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 526 #define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 526 #define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 527 #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 527 #define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 528 #define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1 528 #define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 529 #define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 529 #define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 530 #define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 530 #define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 531 #define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 531 #define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 532 #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 532 #define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 533 #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 533 #define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 534 #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 534 #define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 535 #define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 535 #define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100 536 #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 536 #define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 537 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 537 #define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 538 #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 538 #define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 539 #define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT 539 #define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 540 #define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 540 #define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 541 #define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 541 #define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 542 #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 542 #define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 543 #define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 543 #define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 544 #define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 544 #define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 545 #define MX6QDL_PAD_ENET_RXD1__MLB_SIG 545 #define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 546 #define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 546 #define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 547 #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 547 #define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 548 #define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3 548 #define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 549 #define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 549 #define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 550 #define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 550 #define MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x1e4 0x4f8 0x000 0x0 0x0 551 #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 551 #define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 552 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 552 #define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 553 #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 553 #define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 554 #define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 554 #define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 555 #define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 555 #define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 556 #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 556 #define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 557 #define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 557 #define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 558 #define MX6QDL_PAD_ENET_TXD1__MLB_CLK 558 #define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 559 #define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 559 #define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 560 #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 560 #define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 561 #define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0 561 #define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 562 #define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 562 #define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 563 #define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 563 #define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 564 #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 564 #define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 565 #define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 565 #define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 566 #define MX6QDL_PAD_ENET_MDC__MLB_DATA 566 #define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 567 #define MX6QDL_PAD_ENET_MDC__ENET_MDC 567 #define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 568 #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 568 #define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 569 #define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_ 569 #define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 570 #define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 570 #define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 571 #define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 571 #define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 572 #define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 572 #define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 573 #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 573 #define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 574 #define MX6QDL_PAD_KEY_COL0__KEY_COL0 574 #define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 575 #define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 575 #define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 576 #define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 576 #define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 577 #define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 577 #define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 578 #define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 578 #define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 579 #define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 579 #define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 580 #define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 580 #define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 581 #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 581 #define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 582 #define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 582 #define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 583 #define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 583 #define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 584 #define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 584 #define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 585 #define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 585 #define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 586 #define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 586 #define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 587 #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 587 #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 588 #define MX6QDL_PAD_KEY_COL1__ENET_MDIO 588 #define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 589 #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 589 #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 590 #define MX6QDL_PAD_KEY_COL1__KEY_COL1 590 #define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 591 #define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 591 #define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 592 #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 592 #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 593 #define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 593 #define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 594 #define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 594 #define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 595 #define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 595 #define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 596 #define MX6QDL_PAD_KEY_ROW1__ENET_COL 596 #define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 597 #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 597 #define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 598 #define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 598 #define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 599 #define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 599 #define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 600 #define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 600 #define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 601 #define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 601 #define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 602 #define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 602 #define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 603 #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 603 #define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 604 #define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 604 #define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 605 #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 605 #define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 606 #define MX6QDL_PAD_KEY_COL2__KEY_COL2 606 #define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 607 #define MX6QDL_PAD_KEY_COL2__ENET_MDC 607 #define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 608 #define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 608 #define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 609 #define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WA 609 #define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 610 #define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 610 #define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 611 #define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 611 #define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 612 #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 612 #define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 613 #define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 613 #define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 614 #define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 614 #define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 615 #define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 615 #define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 616 #define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 616 #define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 617 #define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 617 #define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 618 #define MX6QDL_PAD_KEY_COL3__ENET_CRS 618 #define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 619 #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 619 #define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 620 #define MX6QDL_PAD_KEY_COL3__KEY_COL3 620 #define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 621 #define MX6QDL_PAD_KEY_COL3__I2C2_SCL 621 #define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 622 #define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 622 #define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 623 #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 623 #define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 624 #define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 624 #define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 625 #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 625 #define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 626 #define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 626 #define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 627 #define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 627 #define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 628 #define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 628 #define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 629 #define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 629 #define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 630 #define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 630 #define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 631 #define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 631 #define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 632 #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 632 #define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 633 #define MX6QDL_PAD_KEY_COL4__KEY_COL4 633 #define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 634 #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 634 #define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 635 #define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 635 #define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 636 #define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 636 #define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 637 #define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 637 #define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 638 #define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 638 #define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 639 #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 639 #define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 640 #define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 640 #define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 641 #define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 641 #define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 642 #define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 642 #define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 643 #define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 643 #define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 644 #define MX6QDL_PAD_GPIO_0__CCM_CLKO1 644 #define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 645 #define MX6QDL_PAD_GPIO_0__KEY_COL5 645 #define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 646 #define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 646 #define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 647 #define MX6QDL_PAD_GPIO_0__EPIT1_OUT 647 #define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 648 #define MX6QDL_PAD_GPIO_0__GPIO1_IO00 648 #define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 649 #define MX6QDL_PAD_GPIO_0__USB_H1_PWR 649 #define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 650 #define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 650 #define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 651 #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 651 #define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 652 #define MX6QDL_PAD_GPIO_1__WDOG2_B 652 #define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 653 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 653 #define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 654 #define MX6QDL_PAD_GPIO_1__USB_OTG_ID 654 #define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101 655 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 655 #define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 656 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 656 #define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 657 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 657 #define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 658 #define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 658 #define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 659 #define MX6QDL_PAD_GPIO_9__WDOG1_B 659 #define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 660 #define MX6QDL_PAD_GPIO_9__KEY_COL6 660 #define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 661 #define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 661 #define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 662 #define MX6QDL_PAD_GPIO_9__PWM1_OUT 662 #define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 663 #define MX6QDL_PAD_GPIO_9__GPIO1_IO09 663 #define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 664 #define MX6QDL_PAD_GPIO_9__SD1_WP 664 #define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 665 #define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 665 #define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 666 #define MX6QDL_PAD_GPIO_3__I2C3_SCL 666 #define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 667 #define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 667 #define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 668 #define MX6QDL_PAD_GPIO_3__CCM_CLKO2 668 #define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 669 #define MX6QDL_PAD_GPIO_3__GPIO1_IO03 669 #define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 670 #define MX6QDL_PAD_GPIO_3__USB_H1_OC 670 #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 671 #define MX6QDL_PAD_GPIO_3__MLB_CLK 671 #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 672 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 672 #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 673 #define MX6QDL_PAD_GPIO_6__ENET_IRQ 673 #define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609 674 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 674 #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 675 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 675 #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 676 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 676 #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 677 #define MX6QDL_PAD_GPIO_6__MLB_SIG 677 #define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 678 #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 678 #define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 679 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 679 #define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 680 #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 680 #define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 681 #define MX6QDL_PAD_GPIO_2__SD2_WP 681 #define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 682 #define MX6QDL_PAD_GPIO_2__MLB_DATA 682 #define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 683 #define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 683 #define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 684 #define MX6QDL_PAD_GPIO_4__KEY_COL7 684 #define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 685 #define MX6QDL_PAD_GPIO_4__GPIO1_IO04 685 #define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 686 #define MX6QDL_PAD_GPIO_4__SD2_CD_B 686 #define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 687 #define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 687 #define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 688 #define MX6QDL_PAD_GPIO_5__KEY_ROW7 688 #define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 689 #define MX6QDL_PAD_GPIO_5__CCM_CLKO1 689 #define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 690 #define MX6QDL_PAD_GPIO_5__GPIO1_IO05 690 #define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 691 #define MX6QDL_PAD_GPIO_5__I2C3_SCL 691 #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 692 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 692 #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 693 #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 693 #define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 694 #define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 694 #define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 695 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 695 #define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 696 #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 696 #define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 697 #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 697 #define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 698 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 698 #define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 699 #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 699 #define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 700 #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 700 #define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 701 #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 701 #define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 702 #define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 702 #define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 703 #define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 703 #define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 704 #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 704 #define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 705 #define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 705 #define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 706 #define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 706 #define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 707 #define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 707 #define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 708 #define MX6QDL_PAD_GPIO_8__GPIO1_IO08 708 #define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 709 #define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 709 #define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 710 #define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAK 710 #define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 711 #define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 711 #define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 712 #define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_I 712 #define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 713 #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 713 #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 714 #define MX6QDL_PAD_GPIO_16__SD1_LCTL 714 #define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 715 #define MX6QDL_PAD_GPIO_16__SPDIF_IN 715 #define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 716 #define MX6QDL_PAD_GPIO_16__GPIO7_IO11 716 #define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 717 #define MX6QDL_PAD_GPIO_16__I2C3_SDA 717 #define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 718 #define MX6QDL_PAD_GPIO_16__JTAG_DE_B 718 #define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 719 #define MX6QDL_PAD_GPIO_17__ESAI_TX0 719 #define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 720 #define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_I 720 #define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 721 #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 721 #define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 722 #define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 722 #define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 723 #define MX6QDL_PAD_GPIO_17__SPDIF_OUT 723 #define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 724 #define MX6QDL_PAD_GPIO_17__GPIO7_IO12 724 #define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 725 #define MX6QDL_PAD_GPIO_18__ESAI_TX1 725 #define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 726 #define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 726 #define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 727 #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 727 #define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 728 #define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 728 #define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 729 #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 729 #define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 730 #define MX6QDL_PAD_GPIO_18__GPIO7_IO13 730 #define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 731 #define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 731 #define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 732 #define MX6QDL_PAD_GPIO_19__KEY_COL5 732 #define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 733 #define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_O 733 #define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 734 #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 734 #define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 735 #define MX6QDL_PAD_GPIO_19__CCM_CLKO1 735 #define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 736 #define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 736 #define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 737 #define MX6QDL_PAD_GPIO_19__GPIO4_IO05 737 #define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 738 #define MX6QDL_PAD_GPIO_19__ENET_TX_ER 738 #define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 739 #define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXC 739 #define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 740 #define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 740 #define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 741 #define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 741 #define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 742 #define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 742 #define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 743 #define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 743 #define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 744 #define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 744 #define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 745 #define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 745 #define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 746 #define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DAT 746 #define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 747 #define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 747 #define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 748 #define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 748 #define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 749 #define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 749 #define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 750 #define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 750 #define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 751 #define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 751 #define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 752 #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 752 #define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 753 #define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 753 #define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 754 #define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 754 #define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 755 #define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 755 #define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 756 #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 756 #define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 757 #define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 757 #define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 758 #define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 758 #define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 759 #define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 759 #define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 760 #define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 760 #define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 761 #define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 761 #define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 762 #define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 762 #define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 763 #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 763 #define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 764 #define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 764 #define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 765 #define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 765 #define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 766 #define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 766 #define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 767 #define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 767 #define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 768 #define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 768 #define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 769 #define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 769 #define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 770 #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 770 #define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 771 #define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 771 #define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 772 #define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 772 #define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 773 #define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 773 #define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 774 #define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 774 #define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 775 #define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 775 #define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 776 #define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 776 #define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 777 #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 777 #define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 778 #define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 778 #define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 779 #define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 779 #define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 780 #define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 780 #define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 781 #define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 781 #define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 782 #define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 782 #define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 783 #define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 783 #define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 784 #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 784 #define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 785 #define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 785 #define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 786 #define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 786 #define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 787 #define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 787 #define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 788 #define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 788 #define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 789 #define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 789 #define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 790 #define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 790 #define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 791 #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 791 #define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 792 #define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 792 #define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 793 #define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 793 #define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 794 #define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 794 #define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 795 #define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 795 #define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 796 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA1 796 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 797 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 797 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 798 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 798 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 799 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 799 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 800 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 800 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 801 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 801 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 802 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 802 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 803 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA1 803 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 804 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 804 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 805 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 805 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 806 #define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 806 #define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 807 #define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 807 #define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 808 #define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 808 #define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 809 #define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 809 #define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 810 #define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA1 810 #define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 811 #define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 811 #define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 812 #define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 812 #define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 813 #define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 813 #define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 814 #define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 814 #define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 815 #define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 815 #define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 816 #define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA1 816 #define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 817 #define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 817 #define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 818 #define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 818 #define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 819 #define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 819 #define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 820 #define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 820 #define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 821 #define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 821 #define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 822 #define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA1 822 #define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 823 #define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 823 #define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 824 #define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 824 #define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 825 #define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 825 #define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 826 #define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 826 #define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 827 #define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 827 #define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 828 #define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA1 828 #define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 829 #define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 829 #define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 830 #define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 830 #define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 831 #define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 831 #define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 832 #define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 832 #define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 833 #define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 833 #define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 834 #define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA1 834 #define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 835 #define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 835 #define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 836 #define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 836 #define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 837 #define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 837 #define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 838 #define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 838 #define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 839 #define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 839 #define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 840 #define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA1 840 #define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 841 #define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 841 #define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 842 #define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 842 #define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 843 #define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 843 #define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 844 #define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 844 #define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 845 #define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 845 #define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 846 #define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA1 846 #define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 847 #define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 847 #define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 848 #define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 848 #define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 849 #define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 849 #define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 850 #define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 850 #define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 851 #define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 851 #define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 852 #define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA1 852 #define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 853 #define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 853 #define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 854 #define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 854 #define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 855 #define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 855 #define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 856 #define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 856 #define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 857 #define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 857 #define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 858 #define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 858 #define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 859 #define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 859 #define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 860 #define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 860 #define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 861 #define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 861 #define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 862 #define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 862 #define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 863 #define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 863 #define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 864 #define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 864 #define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 865 #define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 865 #define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 866 #define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 866 #define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 867 #define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 867 #define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 868 #define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 868 #define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 869 #define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 869 #define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 870 #define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 870 #define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 871 #define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 871 #define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 872 #define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 872 #define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 873 #define MX6QDL_PAD_SD3_CMD__SD3_CMD 873 #define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 874 #define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 874 #define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 875 #define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 875 #define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 876 #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 876 #define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 877 #define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 877 #define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 878 #define MX6QDL_PAD_SD3_CLK__SD3_CLK 878 #define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 879 #define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 879 #define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 880 #define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 880 #define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 881 #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 881 #define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 882 #define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 882 #define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 883 #define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 883 #define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 884 #define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 884 #define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 885 #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 885 #define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 886 #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 886 #define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 887 #define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 887 #define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 888 #define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 888 #define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 889 #define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 889 #define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 890 #define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 890 #define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 891 #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 891 #define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 892 #define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 892 #define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 893 #define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 893 #define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 894 #define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 894 #define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 895 #define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 895 #define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 896 #define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 896 #define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 897 #define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 897 #define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 898 #define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 898 #define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 899 #define MX6QDL_PAD_SD3_RST__SD3_RESET 899 #define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 900 #define MX6QDL_PAD_SD3_RST__UART3_RTS_B 900 #define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 901 #define MX6QDL_PAD_SD3_RST__UART3_CTS_B 901 #define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 902 #define MX6QDL_PAD_SD3_RST__GPIO7_IO08 902 #define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 903 #define MX6QDL_PAD_NANDF_CLE__NAND_CLE 903 #define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 904 #define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 904 #define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 905 #define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 905 #define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 906 #define MX6QDL_PAD_NANDF_ALE__NAND_ALE 906 #define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 907 #define MX6QDL_PAD_NANDF_ALE__SD4_RESET 907 #define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 908 #define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 908 #define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 909 #define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 909 #define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 910 #define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 910 #define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 911 #define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 911 #define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 912 #define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 912 #define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 913 #define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 913 #define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 914 #define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 914 #define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 915 #define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 915 #define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 916 #define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 916 #define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 917 #define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 917 #define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 918 #define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 918 #define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 919 #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 919 #define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 920 #define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 920 #define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 921 #define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 921 #define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 922 #define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 922 #define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 923 #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 923 #define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 924 #define MX6QDL_PAD_NANDF_CS2__EIM_CRE 924 #define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 925 #define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 925 #define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 926 #define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 926 #define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 927 #define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 927 #define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 928 #define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 928 #define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 929 #define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 929 #define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 930 #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 930 #define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 931 #define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 931 #define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 932 #define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 932 #define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 933 #define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 933 #define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 934 #define MX6QDL_PAD_SD4_CMD__SD4_CMD 934 #define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 935 #define MX6QDL_PAD_SD4_CMD__NAND_RE_B 935 #define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 936 #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 936 #define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 937 #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 937 #define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 938 #define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 938 #define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 939 #define MX6QDL_PAD_SD4_CLK__SD4_CLK 939 #define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 940 #define MX6QDL_PAD_SD4_CLK__NAND_WE_B 940 #define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 941 #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 941 #define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 942 #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 942 #define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 943 #define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 943 #define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 944 #define MX6QDL_PAD_NANDF_D0__NAND_DATA00 944 #define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 945 #define MX6QDL_PAD_NANDF_D0__SD1_DATA4 945 #define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 946 #define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 946 #define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 947 #define MX6QDL_PAD_NANDF_D1__NAND_DATA01 947 #define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 948 #define MX6QDL_PAD_NANDF_D1__SD1_DATA5 948 #define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 949 #define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 949 #define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 950 #define MX6QDL_PAD_NANDF_D2__NAND_DATA02 950 #define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 951 #define MX6QDL_PAD_NANDF_D2__SD1_DATA6 951 #define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 952 #define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 952 #define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 953 #define MX6QDL_PAD_NANDF_D3__NAND_DATA03 953 #define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 954 #define MX6QDL_PAD_NANDF_D3__SD1_DATA7 954 #define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 955 #define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 955 #define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 956 #define MX6QDL_PAD_NANDF_D4__NAND_DATA04 956 #define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 957 #define MX6QDL_PAD_NANDF_D4__SD2_DATA4 957 #define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 958 #define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 958 #define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 959 #define MX6QDL_PAD_NANDF_D5__NAND_DATA05 959 #define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 960 #define MX6QDL_PAD_NANDF_D5__SD2_DATA5 960 #define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 961 #define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 961 #define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 962 #define MX6QDL_PAD_NANDF_D6__NAND_DATA06 962 #define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 963 #define MX6QDL_PAD_NANDF_D6__SD2_DATA6 963 #define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 964 #define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 964 #define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 965 #define MX6QDL_PAD_NANDF_D7__NAND_DATA07 965 #define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 966 #define MX6QDL_PAD_NANDF_D7__SD2_DATA7 966 #define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 967 #define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 967 #define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 968 #define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 968 #define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 969 #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 969 #define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 970 #define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 970 #define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 971 #define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 971 #define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 972 #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 972 #define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 973 #define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 973 #define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 974 #define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 974 #define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 975 #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 975 #define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 976 #define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 976 #define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 977 #define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 977 #define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 978 #define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 978 #define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 979 #define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 979 #define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 980 #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 980 #define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 981 #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 981 #define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 982 #define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 982 #define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 983 #define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 983 #define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 984 #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 984 #define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 985 #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 985 #define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 986 #define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 986 #define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 987 #define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 987 #define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 988 #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 988 #define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 989 #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 989 #define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 990 #define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 990 #define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 991 #define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 991 #define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 992 #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 992 #define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 993 #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 993 #define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 994 #define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 994 #define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 995 #define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 995 #define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 996 #define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 996 #define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 997 #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 997 #define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 998 #define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 998 #define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 999 #define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 999 #define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 1000 #define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 1000 #define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 1001 #define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 1001 #define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 1002 #define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 1002 #define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 1003 #define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 1003 #define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 1004 #define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 1004 #define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 1005 #define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 1005 #define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 1006 #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 1006 #define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 1007 #define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 1007 #define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 1008 #define MX6QDL_PAD_SD1_DAT3__WDOG2_B 1008 #define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 1009 #define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 1009 #define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 1010 #define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DE 1010 #define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 1011 #define MX6QDL_PAD_SD1_CMD__SD1_CMD 1011 #define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 1012 #define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 1012 #define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 1013 #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 1013 #define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 1014 #define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 1014 #define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 1015 #define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 1015 #define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 1016 #define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 1016 #define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 1017 #define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 1017 #define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 1018 #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 1018 #define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 1019 #define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 1019 #define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 1020 #define MX6QDL_PAD_SD1_DAT2__WDOG1_B 1020 #define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 1021 #define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 1021 #define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 1022 #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DE 1022 #define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 1023 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 1023 #define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 1024 #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 1024 #define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 1025 #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 1025 #define MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x350 0x738 0x000 0x2 0x0 1026 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 1026 #define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 1027 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 1027 #define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 1028 #define MX6QDL_PAD_SD2_CLK__SD2_CLK 1028 #define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 1029 #define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 1029 #define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 1030 #define MX6QDL_PAD_SD2_CLK__KEY_COL5 1030 #define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 1031 #define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 1031 #define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 1032 #define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 1032 #define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 1033 #define MX6QDL_PAD_SD2_CMD__SD2_CMD 1033 #define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 1034 #define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 1034 #define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 1035 #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 1035 #define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 1036 #define MX6QDL_PAD_SD2_CMD__AUD4_RXC 1036 #define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 1037 #define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 1037 #define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 1038 #define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 1038 #define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 1039 #define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 1039 #define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 1040 #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 1040 #define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 1041 #define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 1041 #define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 1042 #define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 1042 #define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 1043 1043 1044 #endif /* __DTS_IMX6Q_PINFUNC_H */ 1044 #endif /* __DTS_IMX6Q_PINFUNC_H */ 1045 1045
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