1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright (c) 2014 Protonic Holland 3 * Copyright (c) 2014 Protonic Holland
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include "imx6q.dtsi" 7 #include "imx6q.dtsi"
8 #include "imx6qdl-prti6q.dtsi" 8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/leds/common.h> 9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/sound/fsl-imx-audmux.h> 10 #include <dt-bindings/sound/fsl-imx-audmux.h>
11 11
12 / { 12 / {
13 model = "Protonic PRTI6Q board"; 13 model = "Protonic PRTI6Q board";
14 compatible = "prt,prti6q", "fsl,imx6q" 14 compatible = "prt,prti6q", "fsl,imx6q";
15 15
16 memory@10000000 { 16 memory@10000000 {
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x10000000 0xf0000000>; 18 reg = <0x10000000 0xf0000000>;
19 }; 19 };
20 20
21 backlight_lcd: backlight-lcd { 21 backlight_lcd: backlight-lcd {
22 compatible = "pwm-backlight"; 22 compatible = "pwm-backlight";
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_backligh 24 pinctrl-0 = <&pinctrl_backlight>;
25 pwms = <&pwm1 0 5000000 0>; 25 pwms = <&pwm1 0 5000000 0>;
26 brightness-levels = <0 16 64 2 26 brightness-levels = <0 16 64 255>;
27 num-interpolated-steps = <16>; 27 num-interpolated-steps = <16>;
28 default-brightness-level = <1> 28 default-brightness-level = <1>;
29 power-supply = <®_3v3>; 29 power-supply = <®_3v3>;
30 enable-gpios = <&gpio4 28 GPIO 30 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
31 }; 31 };
32 32
33 can_osc: can-osc { 33 can_osc: can-osc {
34 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
35 #clock-cells = <0>; 35 #clock-cells = <0>;
36 clock-frequency = <25000000>; 36 clock-frequency = <25000000>;
37 }; 37 };
38 38
39 leds { 39 leds {
40 compatible = "gpio-leds"; 40 compatible = "gpio-leds";
41 pinctrl-names = "default"; 41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_leds>; 42 pinctrl-0 = <&pinctrl_leds>;
43 43
44 led-debug0 { 44 led-debug0 {
45 function = LED_FUNCTIO 45 function = LED_FUNCTION_STATUS;
46 gpios = <&gpio1 8 GPIO 46 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
47 linux,default-trigger 47 linux,default-trigger = "heartbeat";
48 }; 48 };
49 49
50 led-debug1 { 50 led-debug1 {
51 function = LED_FUNCTIO 51 function = LED_FUNCTION_SD;
52 gpios = <&gpio1 9 GPIO 52 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
53 linux,default-trigger 53 linux,default-trigger = "disk-activity";
54 }; 54 };
55 }; 55 };
56 56
57 panel { 57 panel {
58 compatible = "kyo,tcg121xglp"; 58 compatible = "kyo,tcg121xglp";
59 backlight = <&backlight_lcd>; 59 backlight = <&backlight_lcd>;
60 60
61 port { 61 port {
62 panel_in: endpoint { 62 panel_in: endpoint {
63 remote-endpoin 63 remote-endpoint = <&lvds0_out>;
64 }; 64 };
65 }; 65 };
66 }; 66 };
67 67
68 reg_1v8: regulator-1v8 { 68 reg_1v8: regulator-1v8 {
69 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
70 regulator-name = "1v8"; 70 regulator-name = "1v8";
71 regulator-min-microvolt = <180 71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <180 72 regulator-max-microvolt = <1800000>;
73 }; 73 };
74 74
75 reg_wifi: regulator-wifi { 75 reg_wifi: regulator-wifi {
76 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
77 pinctrl-names = "default"; 77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_wifi_npd 78 pinctrl-0 = <&pinctrl_wifi_npd>;
79 enable-active-high; 79 enable-active-high;
80 gpio = <&gpio1 26 GPIO_ACTIVE_ 80 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
81 regulator-max-microvolt = <180 81 regulator-max-microvolt = <1800000>;
82 regulator-min-microvolt = <180 82 regulator-min-microvolt = <1800000>;
83 regulator-name = "regulator-WL 83 regulator-name = "regulator-WL12xx";
84 startup-delay-us = <70000>; 84 startup-delay-us = <70000>;
85 }; 85 };
86 86
87 sound { 87 sound {
88 compatible = "simple-audio-car 88 compatible = "simple-audio-card";
89 simple-audio-card,name = "prti 89 simple-audio-card,name = "prti6q-sgtl5000";
90 simple-audio-card,format = "i2 90 simple-audio-card,format = "i2s";
91 simple-audio-card,widgets = 91 simple-audio-card,widgets =
92 "Microphone", "Microph 92 "Microphone", "Microphone Jack",
93 "Line", "Line In Jack" 93 "Line", "Line In Jack",
94 "Headphone", "Headphon 94 "Headphone", "Headphone Jack",
95 "Speaker", "External S 95 "Speaker", "External Speaker";
96 simple-audio-card,routing = 96 simple-audio-card,routing =
97 "MIC_IN", "Microphone 97 "MIC_IN", "Microphone Jack",
98 "LINE_IN", "Line In Ja 98 "LINE_IN", "Line In Jack",
99 "Headphone Jack", "HP_ 99 "Headphone Jack", "HP_OUT",
100 "External Speaker", "L 100 "External Speaker", "LINE_OUT";
101 101
102 simple-audio-card,cpu { 102 simple-audio-card,cpu {
103 sound-dai = <&ssi1>; 103 sound-dai = <&ssi1>;
104 system-clock-frequency 104 system-clock-frequency = <0>;
105 }; 105 };
106 106
107 simple-audio-card,codec { 107 simple-audio-card,codec {
108 sound-dai = <&sgtl5000 108 sound-dai = <&sgtl5000>;
109 bitclock-master; 109 bitclock-master;
110 frame-master; 110 frame-master;
111 }; 111 };
112 }; 112 };
113 113
114 spdif_out: spdif-out { 114 spdif_out: spdif-out {
115 compatible = "linux,spdif-dit" 115 compatible = "linux,spdif-dit";
116 #sound-dai-cells = <0>; 116 #sound-dai-cells = <0>;
117 }; 117 };
118 118
119 spdif_in: spdif-in { 119 spdif_in: spdif-in {
120 compatible = "linux,spdif-dir" 120 compatible = "linux,spdif-dir";
121 #sound-dai-cells = <0>; 121 #sound-dai-cells = <0>;
122 }; 122 };
123 123
124 sound-spdif { 124 sound-spdif {
125 compatible = "fsl,imx-audio-sp 125 compatible = "fsl,imx-audio-spdif";
126 model = "imx-spdif"; 126 model = "imx-spdif";
127 audio-cpu = <&spdif>; 127 audio-cpu = <&spdif>;
128 audio-codec = <&spdif_out>, <& 128 audio-codec = <&spdif_out>, <&spdif_in>;
129 }; 129 };
130 }; 130 };
131 131
132 &audmux { 132 &audmux {
133 pinctrl-names = "default"; 133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_audmux>; 134 pinctrl-0 = <&pinctrl_audmux>;
135 status = "okay"; 135 status = "okay";
136 136
137 mux-ssi1 { 137 mux-ssi1 {
138 fsl,audmux-port = <0>; 138 fsl,audmux-port = <0>;
139 fsl,port-config = < 139 fsl,port-config = <
140 IMX_AUDMUX_V2_PTCR_SYN 140 IMX_AUDMUX_V2_PTCR_SYN 0
141 IMX_AUDMUX_V2_PTCR_TFS 141 IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
142 IMX_AUDMUX_V2_PTCR_TCS 142 IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
143 IMX_AUDMUX_V2_PTCR_TFS 143 IMX_AUDMUX_V2_PTCR_TFSDIR 0
144 IMX_AUDMUX_V2_PTCR_TCL 144 IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
145 >; 145 >;
146 }; 146 };
147 147
148 mux-pins3 { 148 mux-pins3 {
149 fsl,audmux-port = <2>; 149 fsl,audmux-port = <2>;
150 fsl,port-config = < 150 fsl,port-config = <
151 IMX_AUDMUX_V2_PTCR_SYN 151 IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
152 0 152 0 IMX_AUDMUX_V2_PDCR_TXRXEN
153 >; 153 >;
154 }; 154 };
155 }; 155 };
156 156
157 &can1 { 157 &can1 {
158 pinctrl-names = "default"; 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_can1>; 159 pinctrl-0 = <&pinctrl_can1>;
160 status = "okay"; 160 status = "okay";
161 }; 161 };
162 162
163 &can2 { 163 &can2 {
164 pinctrl-names = "default"; 164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_can2>; 165 pinctrl-0 = <&pinctrl_can2>;
166 status = "okay"; 166 status = "okay";
167 }; 167 };
168 168
169 &ecspi1 { 169 &ecspi1 {
170 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW> 170 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
171 pinctrl-names = "default"; 171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_ecspi1>; 172 pinctrl-0 = <&pinctrl_ecspi1>;
173 status = "okay"; 173 status = "okay";
174 174
175 flash@0 { 175 flash@0 {
176 compatible = "jedec,spi-nor"; 176 compatible = "jedec,spi-nor";
177 reg = <0>; 177 reg = <0>;
178 spi-max-frequency = <20000000> 178 spi-max-frequency = <20000000>;
179 }; 179 };
180 }; 180 };
181 181
182 &ecspi2 { 182 &ecspi2 {
183 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW> 183 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>;
184 pinctrl-names = "default"; 184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ 185 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
186 status = "okay"; 186 status = "okay";
187 187
188 can@0 { 188 can@0 {
189 compatible = "microchip,mcp251 189 compatible = "microchip,mcp2515";
190 reg = <0>; 190 reg = <0>;
191 pinctrl-names = "default"; 191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_can3>; 192 pinctrl-0 = <&pinctrl_can3>;
193 clocks = <&can_osc>; 193 clocks = <&can_osc>;
194 interrupts-extended = <&gpio3 194 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
195 spi-max-frequency = <5000000>; 195 spi-max-frequency = <5000000>;
196 }; 196 };
197 197
198 adc@1 { 198 adc@1 {
199 compatible = "ti,adc128s052"; 199 compatible = "ti,adc128s052";
200 reg = <1>; 200 reg = <1>;
201 spi-max-frequency = <2000000>; 201 spi-max-frequency = <2000000>;
202 vref-supply = <®_3v3>; 202 vref-supply = <®_3v3>;
203 }; 203 };
204 }; 204 };
205 205
206 &ecspi3 { 206 &ecspi3 {
207 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW> 207 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
208 pinctrl-names = "default"; 208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_ecspi3>; 209 pinctrl-0 = <&pinctrl_ecspi3>;
210 status = "okay"; 210 status = "okay";
211 }; 211 };
212 212
213 &fec { 213 &fec {
214 pinctrl-names = "default"; 214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_enet>; 215 pinctrl-0 = <&pinctrl_enet>;
216 phy-mode = "rgmii-id"; 216 phy-mode = "rgmii-id";
217 phy-handle = <&rgmii_phy>; 217 phy-handle = <&rgmii_phy>;
218 status = "okay"; 218 status = "okay";
219 219
220 mdio { 220 mdio {
221 #address-cells = <1>; 221 #address-cells = <1>;
222 #size-cells = <0>; 222 #size-cells = <0>;
223 223
224 /* Microchip KSZ9031RNX PHY */ 224 /* Microchip KSZ9031RNX PHY */
225 rgmii_phy: ethernet-phy@0 { 225 rgmii_phy: ethernet-phy@0 {
226 reg = <0>; 226 reg = <0>;
227 interrupts-extended = 227 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
228 reset-gpios = <&gpio1 228 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
229 reset-assert-us = <100 229 reset-assert-us = <10000>;
230 reset-deassert-us = <3 230 reset-deassert-us = <300>;
231 }; 231 };
232 }; 232 };
233 }; 233 };
234 234
235 &hdmi { 235 &hdmi {
236 pinctrl-names = "default"; 236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_hdmi>; 237 pinctrl-0 = <&pinctrl_hdmi>;
238 ddc-i2c-bus = <&i2c2>; 238 ddc-i2c-bus = <&i2c2>;
239 status = "okay"; 239 status = "okay";
240 }; 240 };
241 241
242 &i2c1 { 242 &i2c1 {
243 sgtl5000: audio-codec@a { 243 sgtl5000: audio-codec@a {
244 compatible = "fsl,sgtl5000"; 244 compatible = "fsl,sgtl5000";
245 reg = <0xa>; 245 reg = <0xa>;
246 #sound-dai-cells = <0>; 246 #sound-dai-cells = <0>;
247 clocks = <&clks 201>; 247 clocks = <&clks 201>;
248 VDDA-supply = <®_3v3>; 248 VDDA-supply = <®_3v3>;
249 VDDIO-supply = <®_3v3>; 249 VDDIO-supply = <®_3v3>;
250 VDDD-supply = <®_1v8>; 250 VDDD-supply = <®_1v8>;
251 }; 251 };
252 }; 252 };
253 253
254 /* DDC */ 254 /* DDC */
255 &i2c2 { 255 &i2c2 {
256 clock-frequency = <100000>; 256 clock-frequency = <100000>;
257 pinctrl-names = "default"; 257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_i2c2>; 258 pinctrl-0 = <&pinctrl_i2c2>;
259 status = "okay"; 259 status = "okay";
260 }; 260 };
261 261
262 &i2c3 { 262 &i2c3 {
263 adc@49 { 263 adc@49 {
264 compatible = "ti,ads1015"; 264 compatible = "ti,ads1015";
265 reg = <0x49>; 265 reg = <0x49>;
266 #address-cells = <1>; 266 #address-cells = <1>;
267 #size-cells = <0>; 267 #size-cells = <0>;
268 268
269 /* can2_l */ 269 /* can2_l */
270 channel@4 { 270 channel@4 {
271 reg = <4>; 271 reg = <4>;
272 ti,gain = <3>; 272 ti,gain = <3>;
273 ti,datarate = <3>; 273 ti,datarate = <3>;
274 }; 274 };
275 275
276 /* can2_h */ 276 /* can2_h */
277 channel@5 { 277 channel@5 {
278 reg = <5>; 278 reg = <5>;
279 ti,gain = <3>; 279 ti,gain = <3>;
280 ti,datarate = <3>; 280 ti,datarate = <3>;
281 }; 281 };
282 282
283 /* can1_l */ 283 /* can1_l */
284 channel@6 { 284 channel@6 {
285 reg = <6>; 285 reg = <6>;
286 ti,gain = <3>; 286 ti,gain = <3>;
287 ti,datarate = <3>; 287 ti,datarate = <3>;
288 }; 288 };
289 289
290 /* can1_h */ 290 /* can1_h */
291 channel@7 { 291 channel@7 {
292 reg = <7>; 292 reg = <7>;
293 ti,gain = <3>; 293 ti,gain = <3>;
294 ti,datarate = <3>; 294 ti,datarate = <3>;
295 }; 295 };
296 }; 296 };
297 }; 297 };
298 298
299 &pcie { 299 &pcie {
300 status = "okay"; 300 status = "okay";
301 }; 301 };
302 302
303 &pwm1 { 303 &pwm1 {
304 pinctrl-names = "default"; 304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_pwm1>; 305 pinctrl-0 = <&pinctrl_pwm1>;
306 status = "okay"; 306 status = "okay";
307 }; 307 };
308 308
309 &ldb { 309 &ldb {
310 status = "okay"; 310 status = "okay";
311 311
312 lvds-channel@0 { 312 lvds-channel@0 {
313 status = "okay"; 313 status = "okay";
314 314
315 port@4 { 315 port@4 {
316 reg = <4>; 316 reg = <4>;
317 317
318 lvds0_out: endpoint { 318 lvds0_out: endpoint {
319 remote-endpoin 319 remote-endpoint = <&panel_in>;
320 }; 320 };
321 }; 321 };
322 }; 322 };
323 }; 323 };
324 324
325 &sata { 325 &sata {
326 status = "okay"; 326 status = "okay";
327 }; 327 };
328 328
329 &snvs_poweroff { 329 &snvs_poweroff {
330 status = "okay"; 330 status = "okay";
331 }; 331 };
332 332
333 &spdif { 333 &spdif {
334 pinctrl-names = "default"; 334 pinctrl-names = "default";
335 pinctrl-0 = <&pinctrl_spdif>; 335 pinctrl-0 = <&pinctrl_spdif>;
336 status = "okay"; 336 status = "okay";
337 }; 337 };
338 338
339 &ssi1 { 339 &ssi1 {
340 #sound-dai-cells = <0>; 340 #sound-dai-cells = <0>;
341 fsl,mode = "ac97-slave"; 341 fsl,mode = "ac97-slave";
342 status = "okay"; 342 status = "okay";
343 }; 343 };
344 344
345 &uart2 { 345 &uart2 {
346 pinctrl-names = "default"; 346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_uart2>; 347 pinctrl-0 = <&pinctrl_uart2>;
348 status = "okay"; 348 status = "okay";
349 }; 349 };
350 350
351 &uart5 { 351 &uart5 {
352 pinctrl-names = "default"; 352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_uart5>; 353 pinctrl-0 = <&pinctrl_uart5>;
354 status = "okay"; 354 status = "okay";
355 }; 355 };
356 356
357 &usbotg { 357 &usbotg {
358 pinctrl-0 = <&pinctrl_usbotg &pinctrl_ 358 pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>;
359 }; 359 };
360 360
361 &usdhc2 { 361 &usdhc2 {
362 pinctrl-names = "default"; 362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_usdhc2>; 363 pinctrl-0 = <&pinctrl_usdhc2>;
364 non-removable; 364 non-removable;
365 vmmc-supply = <®_wifi>; 365 vmmc-supply = <®_wifi>;
366 cap-power-off-card; 366 cap-power-off-card;
367 keep-power-in-suspend; 367 keep-power-in-suspend;
368 status = "okay"; 368 status = "okay";
369 369
370 #address-cells = <1>; 370 #address-cells = <1>;
371 #size-cells = <0>; 371 #size-cells = <0>;
372 wifi@2 { 372 wifi@2 {
373 compatible = "ti,wl1271"; 373 compatible = "ti,wl1271";
374 reg = <2>; 374 reg = <2>;
375 pinctrl-names = "default"; 375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_wifi>; 376 pinctrl-0 = <&pinctrl_wifi>;
377 interrupts-extended = <&gpio1 377 interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>;
378 ref-clock-frequency = <3840000 378 ref-clock-frequency = <38400000>;
379 tcxo-clock-frequency = <192000 379 tcxo-clock-frequency = <19200000>;
380 }; 380 };
381 }; 381 };
382 382
383 &iomuxc { 383 &iomuxc {
384 pinctrl_audmux: audmuxgrp { 384 pinctrl_audmux: audmuxgrp {
385 fsl,pins = < 385 fsl,pins = <
386 MX6QDL_PAD_CSI0_MCLK__ 386 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
387 MX6QDL_PAD_CSI0_DAT7__ 387 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
388 MX6QDL_PAD_CSI0_DAT4__ 388 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
389 MX6QDL_PAD_CSI0_DAT5__ 389 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
390 MX6QDL_PAD_CSI0_DAT6__ 390 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
391 >; 391 >;
392 }; 392 };
393 393
394 pinctrl_backlight: backlightgrp { 394 pinctrl_backlight: backlightgrp {
395 fsl,pins = < 395 fsl,pins = <
396 MX6QDL_PAD_DISP0_DAT7_ 396 MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
397 >; 397 >;
398 }; 398 };
399 399
400 pinctrl_can2: can2grp { 400 pinctrl_can2: can2grp {
401 fsl,pins = < 401 fsl,pins = <
402 MX6QDL_PAD_KEY_COL4__F 402 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b008
403 MX6QDL_PAD_KEY_ROW4__F 403 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b008
404 >; 404 >;
405 }; 405 };
406 406
407 pinctrl_can3: can3grp { 407 pinctrl_can3: can3grp {
408 fsl,pins = < 408 fsl,pins = <
409 MX6QDL_PAD_EIM_D20__GP 409 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1
410 >; 410 >;
411 }; 411 };
412 412
413 pinctrl_ecspi1: ecspi1grp { 413 pinctrl_ecspi1: ecspi1grp {
414 fsl,pins = < 414 fsl,pins = <
415 MX6QDL_PAD_EIM_D17__EC 415 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
416 MX6QDL_PAD_EIM_D18__EC 416 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
417 MX6QDL_PAD_EIM_D16__EC 417 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
418 /* CS */ 418 /* CS */
419 MX6QDL_PAD_EIM_D19__GP 419 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1
420 >; 420 >;
421 }; 421 };
422 422
423 pinctrl_ecspi2: ecspi2grp { 423 pinctrl_ecspi2: ecspi2grp {
424 fsl,pins = < 424 fsl,pins = <
425 MX6QDL_PAD_EIM_OE__ECS 425 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
426 MX6QDL_PAD_EIM_CS0__EC 426 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
427 MX6QDL_PAD_EIM_CS1__EC 427 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
428 MX6QDL_PAD_EIM_RW__GPI 428 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
429 >; 429 >;
430 }; 430 };
431 431
432 pinctrl_ecspi2_cs: ecspi2csgrp { 432 pinctrl_ecspi2_cs: ecspi2csgrp {
433 fsl,pins = < 433 fsl,pins = <
434 /* ADC128S022 CS */ 434 /* ADC128S022 CS */
435 MX6QDL_PAD_DISP0_DAT4_ 435 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
436 >; 436 >;
437 }; 437 };
438 438
439 pinctrl_ecspi3: ecspi3grp { 439 pinctrl_ecspi3: ecspi3grp {
440 fsl,pins = < 440 fsl,pins = <
441 MX6QDL_PAD_DISP0_DAT0_ 441 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
442 MX6QDL_PAD_DISP0_DAT1_ 442 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
443 MX6QDL_PAD_DISP0_DAT2_ 443 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
444 MX6QDL_PAD_DISP0_DAT3_ 444 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
445 >; 445 >;
446 }; 446 };
447 447
448 pinctrl_enet: enetgrp { 448 pinctrl_enet: enetgrp {
449 fsl,pins = < 449 fsl,pins = <
450 MX6QDL_PAD_RGMII_RXC__ 450 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
451 MX6QDL_PAD_RGMII_RD0__ 451 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
452 MX6QDL_PAD_RGMII_RD1__ 452 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
453 MX6QDL_PAD_RGMII_RD2__ 453 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
454 MX6QDL_PAD_RGMII_RD3__ 454 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
455 MX6QDL_PAD_RGMII_RX_CT 455 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
456 MX6QDL_PAD_RGMII_TXC__ 456 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
457 MX6QDL_PAD_RGMII_TD0__ 457 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
458 MX6QDL_PAD_RGMII_TD1__ 458 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
459 MX6QDL_PAD_RGMII_TD2__ 459 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
460 MX6QDL_PAD_RGMII_TD3__ 460 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
461 MX6QDL_PAD_RGMII_TX_CT 461 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
462 MX6QDL_PAD_ENET_REF_CL 462 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
463 MX6QDL_PAD_ENET_MDIO__ 463 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
464 MX6QDL_PAD_ENET_MDC__E 464 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
465 465
466 /* Phy reset */ 466 /* Phy reset */
467 MX6QDL_PAD_ENET_CRS_DV 467 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
468 MX6QDL_PAD_ENET_TX_EN_ 468 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
469 >; 469 >;
470 }; 470 };
471 471
472 pinctrl_hdmi: hdmigrp { 472 pinctrl_hdmi: hdmigrp {
473 fsl,pins = < 473 fsl,pins = <
474 /* NOTE: DDC is done v 474 /* NOTE: DDC is done via I2C2, so DON'T
475 * configure DDC pins 475 * configure DDC pins for HDMI!
476 */ 476 */
477 MX6QDL_PAD_EIM_A25__HD 477 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
478 >; 478 >;
479 }; 479 };
480 480
481 /* DDC */ 481 /* DDC */
482 pinctrl_i2c2: i2c2grp { 482 pinctrl_i2c2: i2c2grp {
483 fsl,pins = < 483 fsl,pins = <
484 MX6QDL_PAD_KEY_COL3__I 484 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
485 MX6QDL_PAD_KEY_ROW3__I 485 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
486 >; 486 >;
487 }; 487 };
488 488
489 pinctrl_leds: ledsgrp { 489 pinctrl_leds: ledsgrp {
490 fsl,pins = < 490 fsl,pins = <
491 MX6QDL_PAD_GPIO_8__GPI 491 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
492 MX6QDL_PAD_GPIO_9__GPI 492 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
493 >; 493 >;
494 }; 494 };
495 495
496 pinctrl_pwm1: pwm1grp { 496 pinctrl_pwm1: pwm1grp {
497 fsl,pins = < 497 fsl,pins = <
498 MX6QDL_PAD_DISP0_DAT8_ 498 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
499 >; 499 >;
500 }; 500 };
501 501
502 pinctrl_spdif: spdifgrp { 502 pinctrl_spdif: spdifgrp {
503 fsl,pins = < 503 fsl,pins = <
504 MX6QDL_PAD_GPIO_16__SP 504 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
505 MX6QDL_PAD_GPIO_19__SP 505 MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
506 >; 506 >;
507 }; 507 };
508 508
509 pinctrl_uart2: uart2grp { 509 pinctrl_uart2: uart2grp {
510 fsl,pins = < 510 fsl,pins = <
511 MX6QDL_PAD_EIM_D26__UA 511 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
512 MX6QDL_PAD_EIM_D27__UA 512 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
513 MX6QDL_PAD_EIM_D28__UA 513 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
514 MX6QDL_PAD_EIM_D29__UA 514 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
515 >; 515 >;
516 }; 516 };
517 517
518 pinctrl_uart5: uart5grp { 518 pinctrl_uart5: uart5grp {
519 fsl,pins = < 519 fsl,pins = <
520 MX6QDL_PAD_KEY_COL1__U 520 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
521 MX6QDL_PAD_KEY_ROW1__U 521 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
522 >; 522 >;
523 }; 523 };
524 524
525 pinctrl_usbotg_id: usbotgidgrp { 525 pinctrl_usbotg_id: usbotgidgrp {
526 fsl,pins = < 526 fsl,pins = <
527 MX6QDL_PAD_ENET_RX_ER_ 527 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058
528 >; 528 >;
529 }; 529 };
530 530
531 pinctrl_usdhc2: usdhc2grp { 531 pinctrl_usdhc2: usdhc2grp {
532 fsl,pins = < 532 fsl,pins = <
533 MX6QDL_PAD_SD2_CMD__SD 533 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
534 MX6QDL_PAD_SD2_CLK__SD 534 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
535 MX6QDL_PAD_SD2_DAT0__S 535 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
536 MX6QDL_PAD_SD2_DAT1__S 536 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
537 MX6QDL_PAD_SD2_DAT2__S 537 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
538 MX6QDL_PAD_SD2_DAT3__S 538 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
539 >; 539 >;
540 }; 540 };
541 541
542 pinctrl_wifi: wifigrp { 542 pinctrl_wifi: wifigrp {
543 fsl,pins = < 543 fsl,pins = <
544 /* WL12xx IRQ */ 544 /* WL12xx IRQ */
545 MX6QDL_PAD_ENET_TXD0__ 545 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880
546 >; 546 >;
547 }; 547 };
548 548
549 pinctrl_wifi_npd: wifinpd { 549 pinctrl_wifi_npd: wifinpd {
550 fsl,pins = < 550 fsl,pins = <
551 MX6QDL_PAD_ENET_RXD1__ 551 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0
552 >; 552 >;
553 }; 553 };
554 }; 554 };
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