1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2015-2021 DH electronics GmbH 3 * Copyright (C) 2015-2021 DH electronics GmbH
4 * Copyright (C) 2018 Marek Vasut <marex@denx.d 4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */ 5 */
6 6
7 #include <dt-bindings/pwm/pwm.h> 7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx6qdl-clock.h> 9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 11
12 / { 12 / {
13 aliases { 13 aliases {
14 i2c0 = &i2c2; 14 i2c0 = &i2c2;
15 i2c1 = &i2c1; 15 i2c1 = &i2c1;
16 i2c2 = &i2c3; 16 i2c2 = &i2c3;
17 mmc0 = &usdhc2; 17 mmc0 = &usdhc2;
18 mmc1 = &usdhc3; 18 mmc1 = &usdhc3;
19 mmc2 = &usdhc4; 19 mmc2 = &usdhc4;
20 mmc3 = &usdhc1; 20 mmc3 = &usdhc1;
21 rtc0 = &rtc_i2c; 21 rtc0 = &rtc_i2c;
22 rtc1 = &snvs_rtc; 22 rtc1 = &snvs_rtc;
23 serial0 = &uart1; 23 serial0 = &uart1;
24 serial1 = &uart5; 24 serial1 = &uart5;
25 serial2 = &uart4; 25 serial2 = &uart4;
26 serial3 = &uart2; 26 serial3 = &uart2;
27 serial4 = &uart3; 27 serial4 = &uart3;
28 }; 28 };
29 29
30 memory@10000000 { /* Appropriate memor 30 memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0x10000000 0x20000000>; 32 reg = <0x10000000 0x20000000>;
33 }; 33 };
34 34
35 reg_3p3v: regulator-3P3V { 35 reg_3p3v: regulator-3P3V {
36 compatible = "regulator-fixed" 36 compatible = "regulator-fixed";
37 regulator-always-on; 37 regulator-always-on;
38 regulator-min-microvolt = <330 38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <330 39 regulator-max-microvolt = <3300000>;
40 regulator-name = "3P3V"; 40 regulator-name = "3P3V";
41 }; 41 };
42 42
43 reg_eth_vio: regulator-eth-vio { 43 reg_eth_vio: regulator-eth-vio {
44 compatible = "regulator-fixed" 44 compatible = "regulator-fixed";
45 gpio = <&gpio1 7 0>; 45 gpio = <&gpio1 7 0>;
46 pinctrl-0 = <&pinctrl_enet_vio 46 pinctrl-0 = <&pinctrl_enet_vio>;
47 pinctrl-names = "default"; 47 pinctrl-names = "default";
48 regulator-always-on; 48 regulator-always-on;
49 regulator-boot-on; 49 regulator-boot-on;
50 regulator-min-microvolt = <330 50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <330 51 regulator-max-microvolt = <3300000>;
52 regulator-name = "eth_vio"; 52 regulator-name = "eth_vio";
53 vin-supply = <&sw2_reg>; 53 vin-supply = <&sw2_reg>;
54 }; 54 };
55 55
56 /* OE pin of the latch is low active * 56 /* OE pin of the latch is low active */
57 reg_latch_oe_on: regulator-latch-oe-on 57 reg_latch_oe_on: regulator-latch-oe-on {
58 compatible = "regulator-fixed" 58 compatible = "regulator-fixed";
59 gpio = <&gpio3 22 0>; 59 gpio = <&gpio3 22 0>;
60 regulator-always-on; 60 regulator-always-on;
61 regulator-name = "latch_oe_on" 61 regulator-name = "latch_oe_on";
62 }; 62 };
63 63
64 reg_usb_h1_vbus: regulator-usb-h1-vbus 64 reg_usb_h1_vbus: regulator-usb-h1-vbus {
65 compatible = "regulator-fixed" 65 compatible = "regulator-fixed";
66 enable-active-high; 66 enable-active-high;
67 gpio = <&gpio3 31 0>; 67 gpio = <&gpio3 31 0>;
68 regulator-min-microvolt = <500 68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <500 69 regulator-max-microvolt = <5000000>;
70 regulator-name = "usb_h1_vbus" 70 regulator-name = "usb_h1_vbus";
71 }; 71 };
72 72
73 reg_usb_otg_vbus: regulator-usb-otg-vb 73 reg_usb_otg_vbus: regulator-usb-otg-vbus {
74 compatible = "regulator-fixed" 74 compatible = "regulator-fixed";
75 regulator-min-microvolt = <500 75 regulator-min-microvolt = <5000000>;
76 regulator-max-microvolt = <500 76 regulator-max-microvolt = <5000000>;
77 regulator-name = "usb_otg_vbus 77 regulator-name = "usb_otg_vbus";
78 }; 78 };
79 }; 79 };
80 80
81 &can1 { 81 &can1 {
82 pinctrl-0 = <&pinctrl_flexcan1>; 82 pinctrl-0 = <&pinctrl_flexcan1>;
83 pinctrl-names = "default"; 83 pinctrl-names = "default";
84 status = "okay"; 84 status = "okay";
85 }; 85 };
86 86
87 /* 87 /*
88 * Special SoM hardware required which uses th 88 * Special SoM hardware required which uses the pins from micro SD card. The
89 * pins SD3_DAT0 and SD3_DAT1 are muxed as can 89 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
90 * Tx and Rx are routed to the DHCOM UART1 rts 90 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on
91 * the board device tree file, the micro SD ca 91 * the board device tree file, the micro SD card must be disabled and the uart1
92 * rts/cts must be disabled or output on other 92 * rts/cts must be disabled or output on other DHCOM pins.
93 */ 93 */
94 &can2 { 94 &can2 {
95 pinctrl-0 = <&pinctrl_flexcan2>; 95 pinctrl-0 = <&pinctrl_flexcan2>;
96 pinctrl-names = "default"; 96 pinctrl-names = "default";
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99 99
100 &ecspi1 { 100 &ecspi1 {
101 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW> 101 cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
102 pinctrl-0 = <&pinctrl_ecspi1>; 102 pinctrl-0 = <&pinctrl_ecspi1>;
103 pinctrl-names = "default"; 103 pinctrl-names = "default";
104 status = "okay"; 104 status = "okay";
105 105
106 flash@0 { /* S25FL116K */ 106 flash@0 { /* S25FL116K */
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 compatible = "jedec,spi-nor"; 109 compatible = "jedec,spi-nor";
110 m25p,fast-read; 110 m25p,fast-read;
111 reg = <0>; 111 reg = <0>;
112 spi-max-frequency = <50000000> 112 spi-max-frequency = <50000000>;
113 }; 113 };
114 }; 114 };
115 115
116 &ecspi2 { 116 &ecspi2 {
117 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW> 117 cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
118 pinctrl-0 = <&pinctrl_ecspi2>; 118 pinctrl-0 = <&pinctrl_ecspi2>;
119 pinctrl-names = "default"; 119 pinctrl-names = "default";
120 status = "disabled"; 120 status = "disabled";
121 }; 121 };
122 122
123 &fec { 123 &fec {
124 phy-mode = "rmii"; 124 phy-mode = "rmii";
125 phy-handle = <ðphy0>; 125 phy-handle = <ðphy0>;
126 pinctrl-0 = <&pinctrl_enet_100M>; 126 pinctrl-0 = <&pinctrl_enet_100M>;
127 pinctrl-names = "default"; 127 pinctrl-names = "default";
128 status = "okay"; 128 status = "okay";
129 129
130 mdio { 130 mdio {
131 #address-cells = <1>; 131 #address-cells = <1>;
132 #size-cells = <0>; 132 #size-cells = <0>;
133 133
134 ethphy0: ethernet-phy@0 { /* S 134 ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
135 compatible = "ethernet 135 compatible = "ethernet-phy-id0007.c0f0",
136 "ethernet 136 "ethernet-phy-ieee802.3-c22";
137 interrupt-parent = <&g 137 interrupt-parent = <&gpio4>;
138 interrupts = <15 IRQ_T 138 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
139 pinctrl-0 = <&pinctrl_ 139 pinctrl-0 = <&pinctrl_ethphy0>;
140 pinctrl-names = "defau 140 pinctrl-names = "default";
141 reg = <0>; 141 reg = <0>;
142 reset-assert-us = <500 142 reset-assert-us = <500>;
143 reset-deassert-us = <5 143 reset-deassert-us = <500>;
144 reset-gpios = <&gpio5 144 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
145 smsc,disable-energy-de 145 smsc,disable-energy-detect; /* Make plugin detection reliable */
146 }; 146 };
147 }; 147 };
148 }; 148 };
149 149
150 &gpio1 { 150 &gpio1 {
151 gpio-line-names = 151 gpio-line-names =
152 "", "", "DHCOM-A", "", "DHCOM- 152 "", "", "DHCOM-A", "", "DHCOM-B", "DHCOM-C", "", "",
153 "", "", "", "", "", "", "", "" 153 "", "", "", "", "", "", "", "",
154 "DHCOM-R", "DHCOM-S", "DHCOM-Q 154 "DHCOM-R", "DHCOM-S", "DHCOM-Q", "DHCOM-T", "DHCOM-U", "", "", "",
155 "", "", "", "", "", "", "", "" 155 "", "", "", "", "", "", "", "";
156 }; 156 };
157 157
158 &gpio2 { 158 &gpio2 {
159 gpio-line-names = 159 gpio-line-names =
160 "", "", "", "", "", "", "", "" 160 "", "", "", "", "", "", "", "",
161 "", "", "", "", "", "", "", "" 161 "", "", "", "", "", "", "", "",
162 "SOM-HW2", "", "", "SOM-HW0", 162 "SOM-HW2", "", "", "SOM-HW0", "", "SOM-MEM1", "SOM-MEM0", "",
163 "", "", "", "", "", "", "", "" 163 "", "", "", "", "", "", "", "";
164 }; 164 };
165 165
166 &gpio3 { 166 &gpio3 {
167 gpio-line-names = 167 gpio-line-names =
168 "", "", "", "", "", "", "", "" 168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "" 169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "" 170 "", "", "", "", "", "", "", "",
171 "", "", "", "DHCOM-G", "", "", 171 "", "", "", "DHCOM-G", "", "", "", "";
172 }; 172 };
173 173
174 &gpio4 { 174 &gpio4 {
175 gpio-line-names = 175 gpio-line-names =
176 "", "", "", "", "", "DHCOM-E", 176 "", "", "", "", "", "DHCOM-E", "DHCOM-INT", "DHCOM-H",
177 "DHCOM-I", "DHCOM-L", "", "", 177 "DHCOM-I", "DHCOM-L", "", "", "", "", "", "",
178 "", "", "", "", "DHCOM-F", "", 178 "", "", "", "", "DHCOM-F", "", "", "",
179 "", "", "", "", "", "", "", "" 179 "", "", "", "", "", "", "", "";
180 }; 180 };
181 181
182 &gpio5 { 182 &gpio5 {
183 gpio-line-names = 183 gpio-line-names =
184 "", "", "", "", "", "", "", "" 184 "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "" 185 "", "", "", "", "", "", "", "",
186 "", "", "DHCOM-V", "DHCOM-W", 186 "", "", "DHCOM-V", "DHCOM-W", "", "DHCOM-O", "", "",
187 "", "", "", "", "", "", "", "" 187 "", "", "", "", "", "", "", "";
188 }; 188 };
189 189
190 &gpio6 { 190 &gpio6 {
191 gpio-line-names = 191 gpio-line-names =
192 "", "", "", "DHCOM-D", "", "", 192 "", "", "", "DHCOM-D", "", "", "SOM-HW1", "",
193 "", "", "", "", "", "", "DHCOM 193 "", "", "", "", "", "", "DHCOM-J", "DHCOM-K",
194 "", "", "", "", "", "", "", "" 194 "", "", "", "", "", "", "", "",
195 "", "", "", "", "", "", "", "" 195 "", "", "", "", "", "", "", "";
196 }; 196 };
197 197
198 &gpio7 { 198 &gpio7 {
199 gpio-line-names = 199 gpio-line-names =
200 "DHCOM-M", "DHCOM-N", "", "", 200 "DHCOM-M", "DHCOM-N", "", "", "", "", "", "",
201 "", "", "", "", "", "DHCOM-P", 201 "", "", "", "", "", "DHCOM-P", "", "",
202 "", "", "", "", "", "", "", "" 202 "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "" 203 "", "", "", "", "", "", "", "";
204 }; 204 };
205 205
206 &i2c1 { 206 &i2c1 {
207 /* 207 /*
208 * Info: According to erratum ERR00780 208 * Info: According to erratum ERR007805 clock frequency limit is 375000.
209 * The erratum for i.MX6S/DL is here [ 209 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
210 * [1] https://www.nxp.com/docs/en/err 210 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
211 * [2] https://www.nxp.com/docs/en/err 211 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
212 */ 212 */
213 clock-frequency = <100000>; 213 clock-frequency = <100000>;
214 pinctrl-0 = <&pinctrl_i2c1>; 214 pinctrl-0 = <&pinctrl_i2c1>;
215 pinctrl-1 = <&pinctrl_i2c1_gpio>; 215 pinctrl-1 = <&pinctrl_i2c1_gpio>;
216 pinctrl-names = "default", "gpio"; 216 pinctrl-names = "default", "gpio";
217 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HI 217 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
218 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HI 218 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
219 status = "okay"; 219 status = "okay";
220 }; 220 };
221 221
222 &i2c2 { 222 &i2c2 {
223 /* Info: Clock frequency limit is 3750 223 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
224 clock-frequency = <100000>; 224 clock-frequency = <100000>;
225 pinctrl-0 = <&pinctrl_i2c2>; 225 pinctrl-0 = <&pinctrl_i2c2>;
226 pinctrl-1 = <&pinctrl_i2c2_gpio>; 226 pinctrl-1 = <&pinctrl_i2c2_gpio>;
227 pinctrl-names = "default", "gpio"; 227 pinctrl-names = "default", "gpio";
228 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HI 228 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
229 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HI 229 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
230 status = "okay"; 230 status = "okay";
231 }; 231 };
232 232
233 &i2c3 { 233 &i2c3 {
234 /* Info: Clock frequency limit is 3750 234 /* Info: Clock frequency limit is 375000 (for details see i2c1) */
235 clock-frequency = <100000>; 235 clock-frequency = <100000>;
236 pinctrl-0 = <&pinctrl_i2c3>; 236 pinctrl-0 = <&pinctrl_i2c3>;
237 pinctrl-1 = <&pinctrl_i2c3_gpio>; 237 pinctrl-1 = <&pinctrl_i2c3_gpio>;
238 pinctrl-names = "default", "gpio"; 238 pinctrl-names = "default", "gpio";
239 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIG 239 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
240 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIG 240 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
241 status = "okay"; 241 status = "okay";
242 242
243 ltc3676: pmic@3c { 243 ltc3676: pmic@3c {
244 compatible = "lltc,ltc3676"; 244 compatible = "lltc,ltc3676";
245 interrupt-parent = <&gpio5>; 245 interrupt-parent = <&gpio5>;
246 interrupts = <2 IRQ_TYPE_EDGE_ 246 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
247 pinctrl-0 = <&pinctrl_pmic>; 247 pinctrl-0 = <&pinctrl_pmic>;
248 pinctrl-names = "default"; 248 pinctrl-names = "default";
249 reg = <0x3c>; 249 reg = <0x3c>;
250 250
251 regulators { 251 regulators {
252 sw1_reg: sw1 { 252 sw1_reg: sw1 {
253 lltc,fb-voltag 253 lltc,fb-voltage-divider = <100000 110000>;
254 regulator-alwa 254 regulator-always-on;
255 regulator-boot 255 regulator-boot-on;
256 regulator-max- 256 regulator-max-microvolt = <1527272>;
257 regulator-min- 257 regulator-min-microvolt = <787500>;
258 regulator-ramp 258 regulator-ramp-delay = <7000>;
259 regulator-susp 259 regulator-suspend-mem-microvolt = <1040000>;
260 }; 260 };
261 261
262 sw2_reg: sw2 { 262 sw2_reg: sw2 {
263 lltc,fb-voltag 263 lltc,fb-voltage-divider = <100000 28000>;
264 regulator-alwa 264 regulator-always-on;
265 regulator-boot 265 regulator-boot-on;
266 regulator-max- 266 regulator-max-microvolt = <3657142>;
267 regulator-min- 267 regulator-min-microvolt = <1885714>;
268 regulator-ramp 268 regulator-ramp-delay = <7000>;
269 }; 269 };
270 270
271 sw3_reg: sw3 { 271 sw3_reg: sw3 {
272 lltc,fb-voltag 272 lltc,fb-voltage-divider = <100000 110000>;
273 regulator-alwa 273 regulator-always-on;
274 regulator-boot 274 regulator-boot-on;
275 regulator-max- 275 regulator-max-microvolt = <1527272>;
276 regulator-min- 276 regulator-min-microvolt = <787500>;
277 regulator-ramp 277 regulator-ramp-delay = <7000>;
278 regulator-susp 278 regulator-suspend-mem-microvolt = <980000>;
279 }; 279 };
280 280
281 sw4_reg: sw4 { 281 sw4_reg: sw4 {
282 lltc,fb-voltag 282 lltc,fb-voltage-divider = <100000 93100>;
283 regulator-alwa 283 regulator-always-on;
284 regulator-boot 284 regulator-boot-on;
285 regulator-max- 285 regulator-max-microvolt = <1659291>;
286 regulator-min- 286 regulator-min-microvolt = <855571>;
287 regulator-ramp 287 regulator-ramp-delay = <7000>;
288 }; 288 };
289 289
290 ldo1_reg: ldo1 { 290 ldo1_reg: ldo1 {
291 lltc,fb-voltag 291 lltc,fb-voltage-divider = <102000 29400>;
292 regulator-alwa 292 regulator-always-on;
293 regulator-boot 293 regulator-boot-on;
294 regulator-max- 294 regulator-max-microvolt = <3240306>;
295 regulator-min- 295 regulator-min-microvolt = <3240306>;
296 }; 296 };
297 297
298 ldo2_reg: ldo2 { 298 ldo2_reg: ldo2 {
299 lltc,fb-voltag 299 lltc,fb-voltage-divider = <100000 41200>;
300 regulator-alwa 300 regulator-always-on;
301 regulator-boot 301 regulator-boot-on;
302 regulator-max- 302 regulator-max-microvolt = <2484708>;
303 regulator-min- 303 regulator-min-microvolt = <2484708>;
304 }; 304 };
305 }; 305 };
306 }; 306 };
307 307
308 touchscreen@49 { /* TSC2004 */ 308 touchscreen@49 { /* TSC2004 */
309 compatible = "ti,tsc2004"; 309 compatible = "ti,tsc2004";
310 interrupts-extended = <&gpio4 310 interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
311 pinctrl-0 = <&pinctrl_tsc2004> 311 pinctrl-0 = <&pinctrl_tsc2004>;
312 pinctrl-names = "default"; 312 pinctrl-names = "default";
313 reg = <0x49>; 313 reg = <0x49>;
314 vio-supply = <®_3p3v>; 314 vio-supply = <®_3p3v>;
315 status = "disabled"; 315 status = "disabled";
316 }; 316 };
317 317
318 eeprom@50 { 318 eeprom@50 {
319 compatible = "atmel,24c02"; 319 compatible = "atmel,24c02";
320 pagesize = <16>; 320 pagesize = <16>;
321 reg = <0x50>; 321 reg = <0x50>;
322 }; 322 };
323 323
324 rtc_i2c: rtc@56 { 324 rtc_i2c: rtc@56 {
325 compatible = "microcrystal,rv3 325 compatible = "microcrystal,rv3029";
326 interrupt-parent = <&gpio7>; 326 interrupt-parent = <&gpio7>;
327 interrupts = <12 IRQ_TYPE_EDGE 327 interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
328 pinctrl-0 = <&pinctrl_rtc>; 328 pinctrl-0 = <&pinctrl_rtc>;
329 pinctrl-names = "default"; 329 pinctrl-names = "default";
330 reg = <0x56>; 330 reg = <0x56>;
331 }; 331 };
332 }; 332 };
333 333
334 &pcie { 334 &pcie {
335 pinctrl-0 = <&pinctrl_pcie>; 335 pinctrl-0 = <&pinctrl_pcie>;
336 pinctrl-names = "default"; 336 pinctrl-names = "default";
337 }; 337 };
338 338
339 &pwm1 { 339 &pwm1 {
340 pinctrl-0 = <&pinctrl_pwm1>; 340 pinctrl-0 = <&pinctrl_pwm1>;
341 pinctrl-names = "default"; 341 pinctrl-names = "default";
342 }; 342 };
343 343
344 ®_arm { 344 ®_arm {
345 vin-supply = <&sw3_reg>; 345 vin-supply = <&sw3_reg>;
346 }; 346 };
347 347
348 ®_pu { 348 ®_pu {
349 vin-supply = <&sw1_reg>; 349 vin-supply = <&sw1_reg>;
350 }; 350 };
351 351
352 ®_soc { 352 ®_soc {
353 vin-supply = <&sw1_reg>; 353 vin-supply = <&sw1_reg>;
354 }; 354 };
355 355
356 ®_vdd1p1 { 356 ®_vdd1p1 {
357 vin-supply = <&sw2_reg>; 357 vin-supply = <&sw2_reg>;
358 }; 358 };
359 359
360 ®_vdd2p5 { 360 ®_vdd2p5 {
361 vin-supply = <&sw2_reg>; 361 vin-supply = <&sw2_reg>;
362 }; 362 };
363 363
364 &uart1 { /* DHCOM UART1 */ 364 &uart1 { /* DHCOM UART1 */
365 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW 365 dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
366 dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW 366 dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
367 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW 367 dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
368 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW 368 rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
369 pinctrl-0 = <&pinctrl_uart1>; 369 pinctrl-0 = <&pinctrl_uart1>;
370 pinctrl-names = "default"; 370 pinctrl-names = "default";
371 uart-has-rtscts; 371 uart-has-rtscts;
372 status = "okay"; 372 status = "okay";
373 }; 373 };
374 374
375 &uart4 { /* DHCOM UART3 */ 375 &uart4 { /* DHCOM UART3 */
376 pinctrl-0 = <&pinctrl_uart4>; 376 pinctrl-0 = <&pinctrl_uart4>;
377 pinctrl-names = "default"; 377 pinctrl-names = "default";
378 status = "okay"; 378 status = "okay";
379 }; 379 };
380 380
381 &uart5 { /* DHCOM UART2 */ 381 &uart5 { /* DHCOM UART2 */
382 pinctrl-0 = <&pinctrl_uart5>; 382 pinctrl-0 = <&pinctrl_uart5>;
383 pinctrl-names = "default"; 383 pinctrl-names = "default";
384 uart-has-rtscts; 384 uart-has-rtscts;
385 status = "okay"; 385 status = "okay";
386 }; 386 };
387 387
388 &usbh1 { 388 &usbh1 {
389 dr_mode = "host"; 389 dr_mode = "host";
390 pinctrl-0 = <&pinctrl_usbh1>; 390 pinctrl-0 = <&pinctrl_usbh1>;
391 pinctrl-names = "default"; 391 pinctrl-names = "default";
392 vbus-supply = <®_usb_h1_vbus>; 392 vbus-supply = <®_usb_h1_vbus>;
393 status = "okay"; 393 status = "okay";
394 }; 394 };
395 395
396 &usbotg { 396 &usbotg {
397 disable-over-current; 397 disable-over-current;
398 dr_mode = "otg"; 398 dr_mode = "otg";
399 pinctrl-0 = <&pinctrl_usbotg>; 399 pinctrl-0 = <&pinctrl_usbotg>;
400 pinctrl-names = "default"; 400 pinctrl-names = "default";
401 vbus-supply = <®_usb_otg_vbus>; 401 vbus-supply = <®_usb_otg_vbus>;
402 status = "okay"; 402 status = "okay";
403 }; 403 };
404 404
405 &usdhc2 { /* External SD card via DHCOM */ 405 &usdhc2 { /* External SD card via DHCOM */
406 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH 406 cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
407 keep-power-in-suspend; 407 keep-power-in-suspend;
408 pinctrl-0 = <&pinctrl_usdhc2>; 408 pinctrl-0 = <&pinctrl_usdhc2>;
409 pinctrl-names = "default"; 409 pinctrl-names = "default";
410 status = "disabled"; 410 status = "disabled";
411 }; 411 };
412 412
413 &usdhc3 { /* Micro SD card on module */ 413 &usdhc3 { /* Micro SD card on module */
414 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; 414 cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
415 fsl,wp-controller; 415 fsl,wp-controller;
416 keep-power-in-suspend; 416 keep-power-in-suspend;
417 pinctrl-0 = <&pinctrl_usdhc3>; 417 pinctrl-0 = <&pinctrl_usdhc3>;
418 pinctrl-names = "default"; 418 pinctrl-names = "default";
419 status = "okay"; 419 status = "okay";
420 }; 420 };
421 421
422 &usdhc4 { /* eMMC on module */ 422 &usdhc4 { /* eMMC on module */
423 bus-width = <8>; 423 bus-width = <8>;
424 keep-power-in-suspend; 424 keep-power-in-suspend;
425 no-1-8-v; 425 no-1-8-v;
426 non-removable; 426 non-removable;
427 pinctrl-0 = <&pinctrl_usdhc4>; 427 pinctrl-0 = <&pinctrl_usdhc4>;
428 pinctrl-names = "default"; 428 pinctrl-names = "default";
429 status = "okay"; 429 status = "okay";
430 }; 430 };
431 431
432 &weim { 432 &weim {
433 #address-cells = <2>; 433 #address-cells = <2>;
434 #size-cells = <1>; 434 #size-cells = <1>;
435 fsl,weim-cs-gpr = <&gpr>; 435 fsl,weim-cs-gpr = <&gpr>;
436 pinctrl-0 = <&pinctrl_weim &pinctrl_we 436 pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
437 pinctrl-names = "default"; 437 pinctrl-names = "default";
438 /* It is necessary to setup 2x 64MB ot 438 /* It is necessary to setup 2x 64MB otherwise setting gpr fails */
439 ranges = <0 0 0x08000000 0x04000000>, 439 ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
440 <1 0 0x0c000000 0x04000000>; 440 <1 0 0x0c000000 0x04000000>; /* CS1 */
441 status = "disabled"; 441 status = "disabled";
442 }; 442 };
443 443
444 &iomuxc { 444 &iomuxc {
445 pinctrl-0 = < 445 pinctrl-0 = <
446 &pinctrl_hog_base 446 &pinctrl_hog_base
447 &pinctrl_dhcom_a &pinc 447 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
448 &pinctrl_dhcom_d &pinc 448 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
449 &pinctrl_dhcom_g &pinc 449 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
450 &pinctrl_dhcom_j &pinc 450 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
451 &pinctrl_dhcom_m &pinc 451 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o
452 &pinctrl_dhcom_p &pinc 452 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r
453 &pinctrl_dhcom_s &pinc 453 &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
454 &pinctrl_dhcom_v &pinc 454 &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
455 >; 455 >;
456 pinctrl-names = "default"; 456 pinctrl-names = "default";
457 457
458 pinctrl_hog_base: hog-base-grp { 458 pinctrl_hog_base: hog-base-grp {
459 fsl,pins = < 459 fsl,pins = <
460 /* GPIOs for memory co 460 /* GPIOs for memory coding */
461 MX6QDL_PAD_EIM_A16__GP 461 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x120b0
462 MX6QDL_PAD_EIM_A17__GP 462 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x120b0
463 /* GPIOs for hardware 463 /* GPIOs for hardware coding */
464 MX6QDL_PAD_EIM_A19__GP 464 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x120b0
465 MX6QDL_PAD_EIM_A22__GP 465 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x120b0
466 MX6QDL_PAD_EIM_A23__GP 466 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x120b0
467 >; 467 >;
468 }; 468 };
469 469
470 /* DHCOM GPIOs */ 470 /* DHCOM GPIOs */
471 pinctrl_dhcom_a: dhcom-a-grp { 471 pinctrl_dhcom_a: dhcom-a-grp {
472 fsl,pins = <MX6QDL_PAD_GPIO_2_ 472 fsl,pins = <MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x400120b0>;
473 }; 473 };
474 474
475 pinctrl_dhcom_b: dhcom-b-grp { 475 pinctrl_dhcom_b: dhcom-b-grp {
476 fsl,pins = <MX6QDL_PAD_GPIO_4_ 476 fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0>;
477 }; 477 };
478 478
479 pinctrl_dhcom_c: dhcom-c-grp { 479 pinctrl_dhcom_c: dhcom-c-grp {
480 fsl,pins = <MX6QDL_PAD_GPIO_5_ 480 fsl,pins = <MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0>;
481 }; 481 };
482 482
483 pinctrl_dhcom_d: dhcom-d-grp { 483 pinctrl_dhcom_d: dhcom-d-grp {
484 fsl,pins = <MX6QDL_PAD_CSI0_DA 484 fsl,pins = <MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0>;
485 }; 485 };
486 486
487 pinctrl_dhcom_e: dhcom-e-grp { 487 pinctrl_dhcom_e: dhcom-e-grp {
488 fsl,pins = <MX6QDL_PAD_GPIO_19 488 fsl,pins = <MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x400120b0>;
489 }; 489 };
490 490
491 pinctrl_dhcom_f: dhcom-f-grp { 491 pinctrl_dhcom_f: dhcom-f-grp {
492 fsl,pins = <MX6QDL_PAD_DI0_PIN 492 fsl,pins = <MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0>;
493 }; 493 };
494 494
495 pinctrl_dhcom_g: dhcom-g-grp { 495 pinctrl_dhcom_g: dhcom-g-grp {
496 fsl,pins = <MX6QDL_PAD_EIM_D27 496 fsl,pins = <MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400120b0>;
497 }; 497 };
498 498
499 pinctrl_dhcom_h: dhcom-h-grp { 499 pinctrl_dhcom_h: dhcom-h-grp {
500 fsl,pins = <MX6QDL_PAD_KEY_ROW 500 fsl,pins = <MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x400120b0>;
501 }; 501 };
502 502
503 pinctrl_dhcom_i: dhcom-i-grp { 503 pinctrl_dhcom_i: dhcom-i-grp {
504 fsl,pins = <MX6QDL_PAD_KEY_COL 504 fsl,pins = <MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0>;
505 }; 505 };
506 506
507 pinctrl_dhcom_j: dhcom-j-grp { 507 pinctrl_dhcom_j: dhcom-j-grp {
508 fsl,pins = <MX6QDL_PAD_NANDF_C 508 fsl,pins = <MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0>;
509 }; 509 };
510 510
511 pinctrl_dhcom_k: dhcom-k-grp { 511 pinctrl_dhcom_k: dhcom-k-grp {
512 fsl,pins = <MX6QDL_PAD_NANDF_C 512 fsl,pins = <MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x400120b0>;
513 }; 513 };
514 514
515 pinctrl_dhcom_l: dhcom-l-grp { 515 pinctrl_dhcom_l: dhcom-l-grp {
516 fsl,pins = <MX6QDL_PAD_KEY_ROW 516 fsl,pins = <MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x400120b0>;
517 }; 517 };
518 518
519 pinctrl_dhcom_m: dhcom-m-grp { 519 pinctrl_dhcom_m: dhcom-m-grp {
520 fsl,pins = <MX6QDL_PAD_SD3_DAT 520 fsl,pins = <MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x400120b0>;
521 }; 521 };
522 522
523 pinctrl_dhcom_n: dhcom-n-grp { 523 pinctrl_dhcom_n: dhcom-n-grp {
524 fsl,pins = <MX6QDL_PAD_SD3_DAT 524 fsl,pins = <MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x400120b0>;
525 }; 525 };
526 526
527 pinctrl_dhcom_o: dhcom-o-grp { 527 pinctrl_dhcom_o: dhcom-o-grp {
528 fsl,pins = <MX6QDL_PAD_CSI0_VS 528 fsl,pins = <MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x400120b0>;
529 }; 529 };
530 530
531 pinctrl_dhcom_p: dhcom-p-grp { 531 pinctrl_dhcom_p: dhcom-p-grp {
532 fsl,pins = <MX6QDL_PAD_GPIO_18 532 fsl,pins = <MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x400120b0>;
533 }; 533 };
534 534
535 pinctrl_dhcom_q: dhcom-q-grp { 535 pinctrl_dhcom_q: dhcom-q-grp {
536 fsl,pins = <MX6QDL_PAD_SD1_CMD 536 fsl,pins = <MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x400120b0>;
537 }; 537 };
538 538
539 pinctrl_dhcom_r: dhcom-r-grp { 539 pinctrl_dhcom_r: dhcom-r-grp {
540 fsl,pins = <MX6QDL_PAD_SD1_DAT 540 fsl,pins = <MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x400120b0>;
541 }; 541 };
542 542
543 pinctrl_dhcom_s: dhcom-s-grp { 543 pinctrl_dhcom_s: dhcom-s-grp {
544 fsl,pins = <MX6QDL_PAD_SD1_DAT 544 fsl,pins = <MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x400120b0>;
545 }; 545 };
546 546
547 pinctrl_dhcom_t: dhcom-t-grp { 547 pinctrl_dhcom_t: dhcom-t-grp {
548 fsl,pins = <MX6QDL_PAD_SD1_DAT 548 fsl,pins = <MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x400120b0>;
549 }; 549 };
550 550
551 pinctrl_dhcom_u: dhcom-u-grp { 551 pinctrl_dhcom_u: dhcom-u-grp {
552 fsl,pins = <MX6QDL_PAD_SD1_CLK 552 fsl,pins = <MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x400120b0>;
553 }; 553 };
554 554
555 pinctrl_dhcom_v: dhcom-v-grp { 555 pinctrl_dhcom_v: dhcom-v-grp {
556 fsl,pins = <MX6QDL_PAD_CSI0_PI 556 fsl,pins = <MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x400120b0>;
557 }; 557 };
558 558
559 pinctrl_dhcom_w: dhcom-w-grp { 559 pinctrl_dhcom_w: dhcom-w-grp {
560 fsl,pins = <MX6QDL_PAD_CSI0_MC 560 fsl,pins = <MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x400120b0>;
561 }; 561 };
562 562
563 pinctrl_dhcom_int: dhcom-int-grp { 563 pinctrl_dhcom_int: dhcom-int-grp {
564 fsl,pins = <MX6QDL_PAD_KEY_COL 564 fsl,pins = <MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x400120b0>;
565 }; 565 };
566 566
567 pinctrl_ecspi1: ecspi1-grp { 567 pinctrl_ecspi1: ecspi1-grp {
568 fsl,pins = < 568 fsl,pins = <
569 MX6QDL_PAD_EIM_D16__EC 569 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
570 MX6QDL_PAD_EIM_D17__EC 570 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
571 MX6QDL_PAD_EIM_D18__EC 571 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
572 MX6QDL_PAD_EIM_EB2__GP 572 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
573 MX6QDL_PAD_KEY_ROW2__G 573 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
574 >; 574 >;
575 }; 575 };
576 576
577 pinctrl_ecspi2: ecspi2-grp { 577 pinctrl_ecspi2: ecspi2-grp {
578 fsl,pins = < 578 fsl,pins = <
579 MX6QDL_PAD_CSI0_DAT8__ 579 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
580 MX6QDL_PAD_CSI0_DAT9__ 580 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
581 MX6QDL_PAD_CSI0_DAT10_ 581 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
582 MX6QDL_PAD_CSI0_DAT11_ 582 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
583 >; 583 >;
584 }; 584 };
585 585
586 pinctrl_enet_100M: enet-100M-grp { 586 pinctrl_enet_100M: enet-100M-grp {
587 fsl,pins = < 587 fsl,pins = <
588 MX6QDL_PAD_ENET_CRS_DV 588 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
589 MX6QDL_PAD_ENET_MDC__E 589 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
590 MX6QDL_PAD_ENET_MDIO__ 590 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
591 MX6QDL_PAD_ENET_RX_ER_ 591 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
592 MX6QDL_PAD_ENET_RXD0__ 592 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
593 MX6QDL_PAD_ENET_RXD1__ 593 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
594 MX6QDL_PAD_ENET_TX_EN_ 594 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
595 MX6QDL_PAD_ENET_TXD0__ 595 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
596 MX6QDL_PAD_ENET_TXD1__ 596 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
597 MX6QDL_PAD_GPIO_16__EN 597 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
598 >; 598 >;
599 }; 599 };
600 600
601 pinctrl_enet_vio: enet-vio-grp { 601 pinctrl_enet_vio: enet-vio-grp {
602 fsl,pins = < 602 fsl,pins = <
603 MX6QDL_PAD_GPIO_7__GPI 603 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
604 >; 604 >;
605 }; 605 };
606 606
607 pinctrl_ethphy0: ethphy0-grp { 607 pinctrl_ethphy0: ethphy0-grp {
608 fsl,pins = < 608 fsl,pins = <
609 MX6QDL_PAD_EIM_WAIT__G 609 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */
610 MX6QDL_PAD_KEY_ROW4__G 610 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */
611 >; 611 >;
612 }; 612 };
613 613
614 pinctrl_flexcan1: flexcan1-grp { 614 pinctrl_flexcan1: flexcan1-grp {
615 fsl,pins = < 615 fsl,pins = <
616 MX6QDL_PAD_GPIO_8__FLE 616 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
617 MX6QDL_PAD_KEY_COL2__F 617 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
618 >; 618 >;
619 }; 619 };
620 620
621 pinctrl_flexcan2: flexcan2-grp { 621 pinctrl_flexcan2: flexcan2-grp {
622 fsl,pins = < 622 fsl,pins = <
623 MX6QDL_PAD_SD3_DAT0__F 623 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
624 MX6QDL_PAD_SD3_DAT1__F 624 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
625 >; 625 >;
626 }; 626 };
627 627
628 pinctrl_i2c1: i2c1-grp { 628 pinctrl_i2c1: i2c1-grp {
629 fsl,pins = < 629 fsl,pins = <
630 MX6QDL_PAD_EIM_D21__I2 630 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
631 MX6QDL_PAD_EIM_D28__I2 631 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
632 >; 632 >;
633 }; 633 };
634 634
635 pinctrl_i2c1_gpio: i2c1-gpio-grp { 635 pinctrl_i2c1_gpio: i2c1-gpio-grp {
636 fsl,pins = < 636 fsl,pins = <
637 MX6QDL_PAD_EIM_D21__GP 637 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
638 MX6QDL_PAD_EIM_D28__GP 638 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
639 >; 639 >;
640 }; 640 };
641 641
642 pinctrl_i2c2: i2c2-grp { 642 pinctrl_i2c2: i2c2-grp {
643 fsl,pins = < 643 fsl,pins = <
644 MX6QDL_PAD_KEY_COL3__I 644 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
645 MX6QDL_PAD_KEY_ROW3__I 645 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
646 >; 646 >;
647 }; 647 };
648 648
649 pinctrl_i2c2_gpio: i2c2-gpio-grp { 649 pinctrl_i2c2_gpio: i2c2-gpio-grp {
650 fsl,pins = < 650 fsl,pins = <
651 MX6QDL_PAD_KEY_COL3__G 651 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
652 MX6QDL_PAD_KEY_ROW3__G 652 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
653 >; 653 >;
654 }; 654 };
655 655
656 pinctrl_i2c3: i2c3-grp { 656 pinctrl_i2c3: i2c3-grp {
657 fsl,pins = < 657 fsl,pins = <
658 MX6QDL_PAD_GPIO_3__I2C 658 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
659 MX6QDL_PAD_GPIO_6__I2C 659 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
660 >; 660 >;
661 }; 661 };
662 662
663 pinctrl_i2c3_gpio: i2c3-gpio-grp { 663 pinctrl_i2c3_gpio: i2c3-gpio-grp {
664 fsl,pins = < 664 fsl,pins = <
665 MX6QDL_PAD_GPIO_3__GPI 665 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
666 MX6QDL_PAD_GPIO_6__GPI 666 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
667 >; 667 >;
668 }; 668 };
669 669
670 pinctrl_ipu1_lcdif: ipu1-lcdif-grp { 670 pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
671 fsl,pins = < 671 fsl,pins = <
672 MX6QDL_PAD_DI0_DISP_CL 672 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
673 MX6QDL_PAD_DI0_PIN2__I 673 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
674 MX6QDL_PAD_DI0_PIN3__I 674 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
675 MX6QDL_PAD_DI0_PIN15__ 675 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
676 MX6QDL_PAD_DISP0_DAT0_ 676 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
677 MX6QDL_PAD_DISP0_DAT1_ 677 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
678 MX6QDL_PAD_DISP0_DAT2_ 678 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
679 MX6QDL_PAD_DISP0_DAT3_ 679 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
680 MX6QDL_PAD_DISP0_DAT4_ 680 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
681 MX6QDL_PAD_DISP0_DAT5_ 681 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
682 MX6QDL_PAD_DISP0_DAT6_ 682 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
683 MX6QDL_PAD_DISP0_DAT7_ 683 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
684 MX6QDL_PAD_DISP0_DAT8_ 684 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
685 MX6QDL_PAD_DISP0_DAT9_ 685 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
686 MX6QDL_PAD_DISP0_DAT10 686 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
687 MX6QDL_PAD_DISP0_DAT11 687 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
688 MX6QDL_PAD_DISP0_DAT12 688 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
689 MX6QDL_PAD_DISP0_DAT13 689 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
690 MX6QDL_PAD_DISP0_DAT14 690 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
691 MX6QDL_PAD_DISP0_DAT15 691 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
692 MX6QDL_PAD_DISP0_DAT16 692 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
693 MX6QDL_PAD_DISP0_DAT17 693 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
694 MX6QDL_PAD_DISP0_DAT18 694 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
695 MX6QDL_PAD_DISP0_DAT19 695 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
696 MX6QDL_PAD_DISP0_DAT20 696 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
697 MX6QDL_PAD_DISP0_DAT21 697 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
698 MX6QDL_PAD_DISP0_DAT22 698 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
699 MX6QDL_PAD_DISP0_DAT23 699 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
700 >; 700 >;
701 }; 701 };
702 702
703 pinctrl_pcie: pcie-grp { 703 pinctrl_pcie: pcie-grp {
704 fsl,pins = < 704 fsl,pins = <
705 MX6QDL_PAD_CSI0_DATA_E 705 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */
706 >; 706 >;
707 }; 707 };
708 708
709 pinctrl_pmic: pmic-grp { 709 pinctrl_pmic: pmic-grp {
710 fsl,pins = < 710 fsl,pins = <
711 MX6QDL_PAD_EIM_A25__GP 711 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0
712 >; 712 >;
713 }; 713 };
714 714
715 pinctrl_pwm1: pwm1-grp { 715 pinctrl_pwm1: pwm1-grp {
716 fsl,pins = < 716 fsl,pins = <
717 MX6QDL_PAD_SD1_DAT3__P 717 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
718 >; 718 >;
719 }; 719 };
720 720
721 pinctrl_rtc: rtc-grp { 721 pinctrl_rtc: rtc-grp {
722 fsl,pins = < 722 fsl,pins = <
723 MX6QDL_PAD_GPIO_17__GP 723 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0
724 >; 724 >;
725 }; 725 };
726 726
727 pinctrl_tsc2004: tsc2004-grp { 727 pinctrl_tsc2004: tsc2004-grp {
728 fsl,pins = < 728 fsl,pins = <
729 MX6QDL_PAD_KEY_COL4__G 729 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x120b0
730 >; 730 >;
731 }; 731 };
732 732
733 pinctrl_uart1: uart1-grp { 733 pinctrl_uart1: uart1-grp {
734 fsl,pins = < 734 fsl,pins = <
735 MX6QDL_PAD_EIM_D19__UA 735 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x4001b0b1
736 MX6QDL_PAD_EIM_D20__UA 736 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
737 MX6QDL_PAD_EIM_D23__GP 737 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x4001b0b1
738 MX6QDL_PAD_EIM_D24__GP 738 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x4001b0b1
739 MX6QDL_PAD_EIM_D25__GP 739 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x4001b0b1
740 MX6QDL_PAD_EIM_EB3__GP 740 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x4001b0b1
741 MX6QDL_PAD_SD3_DAT6__U 741 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
742 MX6QDL_PAD_SD3_DAT7__U 742 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
743 >; 743 >;
744 }; 744 };
745 745
746 pinctrl_uart4: uart4-grp { 746 pinctrl_uart4: uart4-grp {
747 fsl,pins = < 747 fsl,pins = <
748 MX6QDL_PAD_CSI0_DAT12_ 748 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
749 MX6QDL_PAD_CSI0_DAT13_ 749 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
750 >; 750 >;
751 }; 751 };
752 752
753 pinctrl_uart5: uart5-grp { 753 pinctrl_uart5: uart5-grp {
754 fsl,pins = < 754 fsl,pins = <
755 MX6QDL_PAD_CSI0_DAT14_ 755 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
756 MX6QDL_PAD_CSI0_DAT15_ 756 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
757 MX6QDL_PAD_CSI0_DAT18_ 757 MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x1b0b1
758 MX6QDL_PAD_CSI0_DAT19_ 758 MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x4001b0b1
759 >; 759 >;
760 }; 760 };
761 761
762 pinctrl_usbh1: usbh1-grp { 762 pinctrl_usbh1: usbh1-grp {
763 fsl,pins = < 763 fsl,pins = <
764 MX6QDL_PAD_EIM_D31__GP 764 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x120b0
765 MX6QDL_PAD_EIM_D30__US 765 MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b0b1
766 >; 766 >;
767 }; 767 };
768 768
769 pinctrl_usbotg: usbotg-grp { 769 pinctrl_usbotg: usbotg-grp {
770 fsl,pins = < 770 fsl,pins = <
771 MX6QDL_PAD_GPIO_1__USB 771 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
772 >; 772 >;
773 }; 773 };
774 774
775 pinctrl_usdhc2: usdhc2-grp { 775 pinctrl_usdhc2: usdhc2-grp {
776 fsl,pins = < 776 fsl,pins = <
777 MX6QDL_PAD_NANDF_CS3__ 777 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x120b0
778 MX6QDL_PAD_SD2_CLK__SD 778 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
779 MX6QDL_PAD_SD2_CMD__SD 779 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
780 MX6QDL_PAD_SD2_DAT0__S 780 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
781 MX6QDL_PAD_SD2_DAT1__S 781 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
782 MX6QDL_PAD_SD2_DAT2__S 782 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
783 MX6QDL_PAD_SD2_DAT3__S 783 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
784 >; 784 >;
785 }; 785 };
786 786
787 pinctrl_usdhc3: usdhc3-grp { 787 pinctrl_usdhc3: usdhc3-grp {
788 fsl,pins = < 788 fsl,pins = <
789 MX6QDL_PAD_SD3_CLK__SD 789 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
790 MX6QDL_PAD_SD3_CMD__SD 790 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
791 MX6QDL_PAD_SD3_DAT0__S 791 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
792 MX6QDL_PAD_SD3_DAT1__S 792 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
793 MX6QDL_PAD_SD3_DAT2__S 793 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
794 MX6QDL_PAD_SD3_DAT3__S 794 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
795 MX6QDL_PAD_SD3_RST__GP 795 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x120b0
796 >; 796 >;
797 }; 797 };
798 798
799 pinctrl_usdhc4: usdhc4-grp { 799 pinctrl_usdhc4: usdhc4-grp {
800 fsl,pins = < 800 fsl,pins = <
801 MX6QDL_PAD_SD4_CLK__SD 801 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
802 MX6QDL_PAD_SD4_CMD__SD 802 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
803 MX6QDL_PAD_SD4_DAT0__S 803 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
804 MX6QDL_PAD_SD4_DAT1__S 804 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
805 MX6QDL_PAD_SD4_DAT2__S 805 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
806 MX6QDL_PAD_SD4_DAT3__S 806 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
807 MX6QDL_PAD_SD4_DAT4__S 807 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
808 MX6QDL_PAD_SD4_DAT5__S 808 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
809 MX6QDL_PAD_SD4_DAT6__S 809 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
810 MX6QDL_PAD_SD4_DAT7__S 810 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
811 >; 811 >;
812 }; 812 };
813 813
814 pinctrl_weim: weim-grp { 814 pinctrl_weim: weim-grp {
815 fsl,pins = < 815 fsl,pins = <
816 MX6QDL_PAD_EIM_DA0__EI 816 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0a6
817 MX6QDL_PAD_EIM_DA1__EI 817 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0a6
818 MX6QDL_PAD_EIM_DA2__EI 818 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0a6
819 MX6QDL_PAD_EIM_DA3__EI 819 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0a6
820 MX6QDL_PAD_EIM_DA4__EI 820 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0a6
821 MX6QDL_PAD_EIM_DA5__EI 821 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0a6
822 MX6QDL_PAD_EIM_DA6__EI 822 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0a6
823 MX6QDL_PAD_EIM_DA7__EI 823 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0a6
824 MX6QDL_PAD_EIM_DA8__EI 824 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0a6
825 MX6QDL_PAD_EIM_DA9__EI 825 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0a6
826 MX6QDL_PAD_EIM_DA10__E 826 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0a6
827 MX6QDL_PAD_EIM_DA11__E 827 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0a6
828 MX6QDL_PAD_EIM_DA12__E 828 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0a6
829 MX6QDL_PAD_EIM_DA13__E 829 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0a6
830 MX6QDL_PAD_EIM_DA14__E 830 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0a6
831 MX6QDL_PAD_EIM_DA15__E 831 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0a6
832 MX6QDL_PAD_EIM_D22__GP 832 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0
833 MX6QDL_PAD_EIM_LBA__EI 833 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb060 /* LE */
834 MX6QDL_PAD_EIM_OE__EIM 834 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0a6
835 MX6QDL_PAD_EIM_RW__EIM 835 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0a6 /* WE */
836 >; 836 >;
837 }; 837 };
838 838
839 pinctrl_weim_cs0: weim-cs0-grp { 839 pinctrl_weim_cs0: weim-cs0-grp {
840 fsl,pins = < 840 fsl,pins = <
841 MX6QDL_PAD_EIM_CS0__EI 841 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
842 >; 842 >;
843 }; 843 };
844 844
845 pinctrl_weim_cs1: weim-cs1-grp { 845 pinctrl_weim_cs1: weim-cs1-grp {
846 fsl,pins = < 846 fsl,pins = <
847 MX6QDL_PAD_EIM_CS1__EI 847 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
848 >; 848 >;
849 }; 849 };
850 }; 850 };
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